There is an analogous change for ARM here:
https://patchwork.kernel.org/patch/10649857
---
target/riscv/csr.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6083c782a1..1ec1222da1 100644
--- a/target/riscv/csr.c
+++ b/target/ris
Argh, meant to include a signed off by line:
Signed-off-by: Jonathan Behrens
On Mon, May 6, 2019 at 11:31 AM Jonathan Behrens wrote:
> There is an analogous change for ARM here:
> https://patchwork.kernel.org/patch/10649857
> ---
> target/riscv/csr.c | 4 +++-
> 1 file change
Signed-off-by: Jonathan Behrens
---
target/riscv/csr.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 1ec1222da1..fff7d834e8 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -246,6 +246,7 @@ static con
if it
works and I'll resend the other patch the same way. Sorry about this!
Jonathan
On Tue, May 7, 2019 at 1:52 PM Palmer Dabbelt wrote:
> On Mon, 06 May 2019 08:52:43 PDT (-0700), finte...@gmail.com wrote:
> > According to the spec, "All bits besides SSIP, USIP, and UEIP in
Signed-off-by: Jonathan Behrens
---
target/riscv/csr.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 1ec1222da1..fff7d834e8 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -246,6 +246,7 @@ static con
There is an analogous change for ARM here:
https://patchwork.kernel.org/patch/10649857
Signed-off-by: Jonathan Behrens
---
target/riscv/csr.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6083c782a1..1ec1222da1 100644
--- a
Signed-off-by: Jonathan Behrens
---
hw/net/cadence_gem.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 7f63411430..37cb8a4e5c 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -146,7 +146,6 @@
#define GEM_DESCONF7
se
> Signed-off-by: Dongjiu Geng
Hi Dongjiu,
Good to see this moving forwards again.
A few really minor things inline.
Thanks,
Jonathan
> ---
> hw/acpi/acpi_ghes.c | 177
>
> include/hw/acpi/acpi_ghes.h | 6 +-
&g
ilar).
Might be better to drop it for now and simplify this set a little bit?
Note I'm using the gpio path for CCIX PER error emulation so have it hooked up.
The code here is fine, just not used (I think).
Thanks,
Jonathan
> ---
> default-configs/arm-softmmu.mak | 1 +
> hw/a
Ping! What is the status of this patch?
On Wed, Jul 3, 2019 at 2:02 PM Jonathan Behrens
wrote:
> Bin, that proposal proved to be somewhat more controversial than I was
> expecting, since it was different than how currently available hardware
> worked. This option seemed much more lik
On Fri, 16 Aug 2019 13:59:02 +0100
Peter Maydell wrote:
> On Tue, 25 Jun 2019 at 12:28, Jonathan Cameron
> wrote:
> >
> > CCIX topologies are 'layered' on top of PCIe tree topologies.
> > This is done primarily by allowing a single CCIX device to appear as
Reviewed-by: Jonathan Behrens
On Thu, Jul 25, 2019 at 2:56 PM Alistair Francis
wrote:
> Signed-off-by: Alistair Francis
> ---
> hw/riscv/sifive_plic.c | 12
> include/hw/riscv/sifive_plic.h | 3 ---
> 2 files changed, 15 deletions(-)
>
>
e, 3=M-mode.
I also tested by booting RVirt <https://github.com/mit-pdos/RVirt> with a
Linux guest and found that this patch caused it to instantly crash because
guest CSR accesses weren't intercepted.
Jonathan
On Fri, Jul 26, 2019 at 4:28 PM Alistair Francis
wrote:
> On Thu, Jul
I'm not familiar with QEMU conventions on this, but would it make sense to
require having exactly 5 CPUs to match the real board?
Jonathan
On Mon, Aug 5, 2019 at 12:05 PM Bin Meng wrote:
> It is not useful if we only have one management CPU.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Jonathan Behrens
On Mon, Aug 5, 2019 at 12:07 PM Bin Meng wrote:
> This updates the UART base address to match the hardware.
>
> Signed-off-by: Bin Meng
> ---
>
> hw/riscv/sifive_u.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
riority=7 is now assumed.
Reviewed-by: Jonathan Behrens
On Mon, Aug 5, 2019 at 12:10 PM Bin Meng wrote:
> This removes "reg-names" and "riscv,max-priority" properties of the
> PLIC node from device tree, and updates its compatible string, to
> keep in sync with th
For reference alongside this patch set.
Evaluation version of the CCIX 1.0a base specification now available,
(though there is a form to complete and license agreement)..
https://www.ccixconsortium.com/ccix-library/download-form/
Thanks,
Jonathan
On Tue, 25 Jun 2019 19:27:45 +0800
Jonathan
lity
in how this code is reused than actually 'fixing' anything here.
If you don't make the change here, I'll just add a precursor patch to my
series. Just seems nice to tidy it up at source.
The rest of the parts of this s
L 2.0 spec
(nothing stops others using it though AFAIK).
However, then we'd actually need either dynamic node creation in the OS, or
some sort of reserved pool of extra nodes. Long term it may be the most
flexible option.
Jonathan
>
> I'm certainly no SRAT expert, but seems li
i Ben, Saransh
I have a forward port of the series + DOE etc to near current QEMU that is
lightly tested,
and can look to push that out publicly later this week.
I'd also like to push QEMU support forwards and to start getting this upstream
in QEMU
+ fill in some of th
On Wed, 17 Nov 2021 19:08:28 +0100
David Hildenbrand wrote:
> On 17.11.21 15:30, Jonathan Cameron wrote:
> > On Tue, 16 Nov 2021 12:11:29 +0100
> > David Hildenbrand wrote:
> >
> >>>>
> >>>> Examples include exposing HBM or PMEM to the VM.
On Thu, 18 Nov 2021 12:06:27 +0100
David Hildenbrand wrote:
> On 18.11.21 11:28, Jonathan Cameron wrote:
> > On Wed, 17 Nov 2021 19:08:28 +0100
> > David Hildenbrand wrote:
> >
> >> On 17.11.21 15:30, Jonathan Cameron wrote:
> >>> On Tue, 16 Nov 2
On Thu, 18 Nov 2021 11:23:06 +
Jonathan Cameron wrote:
> On Thu, 18 Nov 2021 12:06:27 +0100
> David Hildenbrand wrote:
>
> > On 18.11.21 11:28, Jonathan Cameron wrote:
> > > On Wed, 17 Nov 2021 19:08:28 +0100
> > > David Hildenbrand wrote:
> > &g
On Fri, 19 Nov 2021 12:33:27 +0100
David Hildenbrand wrote:
> On 19.11.21 11:58, Jonathan Cameron wrote:
> > On Thu, 18 Nov 2021 11:23:06 +
> > Jonathan Cameron wrote:
> >
> >> On Thu, 18 Nov 2021 12:06:27 +0100
> >> David Hildenbrand wrote:
&
On Thu, 18 Nov 2021 17:52:07 -0800
Ben Widawsky wrote:
> On 21-11-18 15:20:34, Saransh Gupta1 wrote:
> > Hi Ben and Jonathan,
> >
> > Thanks for your replies. I'm looking forward to the patches.
> >
> > For QEMU, I see hotplug support as an item on the lis
From: Michael Kropaczek
Description:
Currently namespaces could be configured as follows:
1. Legacy Namespace - just one namespace within Nvme controller's
where the back-end was specified for nvme device by -drive parameter
pointing directly to the image file.
2. Additional Namespaces - s
From: Michael Kropaczek
Added support for NVMEe NameSpaces Mangement allowing the guest OS to
create namespaces by issuing nvme create-ns command.
It is an extension to currently implemented Qemu nvme virtual device.
Virtual devices representing namespaces will be created and/or deleted
during Qe
From: Michael Kropaczek
Added support for NVMEe NameSpaces Mangement allowing the guest OS to
delete namespaces by issuing nvme delete-ns command.
It is an extension to currently implemented Qemu nvme virtual device.
Virtual devices representing namespaces will be created and/or deleted
during Qe
From: Michael Kropaczek
Description:
Currently namespaces could be configured as follows:
1. Legacy Namespace - just one namespace within Nvme controller's
where the back-end was specified for nvme device by -drive parameter
pointing directly to the image file.
2. Additional Namespaces - s
From: Michael Kropaczek
Added support for NVMEe NameSpaces Mangement allowing the guest OS to
delete namespaces by issuing nvme delete-ns command.
It is an extension to currently implemented Qemu nvme virtual device.
Virtual devices representing namespaces will be created and/or deleted
during Qe
From: Michael Kropaczek
Added support for NVMEe NameSpaces Mangement allowing the guest OS to
create namespaces by issuing nvme create-ns command.
It is an extension to currently implemented Qemu nvme virtual device.
Virtual devices representing namespaces will be created and/or deleted
during Qe
From: Michael Kropaczek
Added support for NVMEe NameSpaces Mangement allowing the guest OS to
delete namespaces by issuing nvme delete-ns command.
It is an extension to currently implemented Qemu nvme virtual device.
Virtual devices representing namespaces will be created and/or deleted
during Qe
From: Michael Kropaczek
Added support for NVMEe NameSpaces Mangement allowing the guest OS to
create namespaces by issuing nvme create-ns command.
It is an extension to currently implemented Qemu nvme virtual device.
Virtual devices representing namespaces will be created and/or deleted
during Qe
From: Michael Kropaczek
Description:
Currently namespaces could be configured as follows:
1. Legacy Namespace - just one namespace within Nvme controller's
where the back-end was specified for nvme device by -drive parameter
pointing directly to the image file.
2. Additional Namespaces - s
Introduction
If we think application specific memory (including inter-host shared memory) is
a thing, it will also be a thing people want to use with virtual machines,
potentially nested. So how do we present it at the Host to VM boundary?
This RFC is perhaps premature given we haven
On Fri, 16 Aug 2024 09:05:46 +0200
Hannes Reinecke wrote:
> On 8/15/24 18:22, Jonathan Cameron wrote:
> > Introduction
> >
> >
> > If we think application specific memory (including inter-host shared
> > memory) is
> > a thing, it will
On Sun, 18 Aug 2024 21:12:34 -0500
John Groves wrote:
> On 24/08/15 05:22PM, Jonathan Cameron wrote:
> > Introduction
> >
> >
> > If we think application specific memory (including inter-host shared
> > memory) is
> > a thing, it will
On Tue, 17 Sep 2024 19:37:21 +
Jonathan Cameron wrote:
> Plan is currently to meet at lpc registration desk 2pm tomorrow Wednesday and
> we will find a room.
>
And now the internet maybe knows my phone number (serves me right for using
my company mobile app that auto added a sig
xt4 -F /dev/nvme0n1
Signed-off-by: Francis Pravin AntonyX Michael Raj
Signed-off-by: Michael Kropaczek
Signed-off-by: Jonathan Derrick
---
hw/nvme/ctrl.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index 03760ddeae..74540a03d5 100644
--- a/hw/nvme/ctrl.c
+
On Mon, 11 Oct 2021 08:19:01 -0400
"Michael S. Tsirkin" wrote:
> On Mon, Oct 11, 2021 at 12:13:55PM +0200, BALATON Zoltan wrote:
> > On Mon, 11 Oct 2021, Philippe Mathieu-Daudé wrote:
> > > On 10/10/21 15:24, BALATON Zoltan wrote:
> > > > Hello,
> > > >
> > > > I'm trying to fix shutdown and
matches against
'solaris' instead of 'sunos' for uname.
First time submitting a patch here, hope I did it correctly. Thanks.
Signed-off-by: Jonathan Perkin
---
meson.build | 4 ++--
net/meson.build | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff -
On Thu, 27 Oct 2016 02:59:26 +0530
Kirti Wankhede wrote:
> The Sample driver creates mdev device that simulates serial port over PCI
> card.
>
> Signed-off-by: Kirti Wankhede
> Signed-off-by: Neo Jia
> Change-Id: I857f8f12f8b275f2498dfe8c628a5cdc7193b1b2
> ---
> Documentation/vfio-mdev/Makefi
t; Signed-off-by: Li Qiang
> ---
> hw/audio/ac97.c | 8
> 1 file changed, 8 insertions(+)
Regards,
Jonathan Neuschäfer
signature.asc
Description: PGP signature
tmp += 1
atomic_set(&sl->sequence, tmp)
atomic_set(&sl->sequence, tmp)
... where sl->sequence will effectively only be incremented once (as far
as I can see).
Regards,
Jonathan Neuschäfer
signature.asc
Description: PGP signature
On Fri, Sep 30, 2016 at 11:45:19PM +0100, Alex Bennée wrote:
>
> Jonathan Neuschäfer writes:
>
> > On Fri, Sep 30, 2016 at 10:30:56PM +0100, Alex Bennée wrote:
> >> From: Paolo Bonzini
> >>
> >> There is a data race if the sequence is written concu
nformation I removed (e.g. basic
> block unchaining) was obsolete.
>
> Signed-off-by: Paolo Bonzini
> ---
[...]
> +@item Threading:
> +On Linux, QEMU can emulate the @code{clone} and create a real host
s/@code{clone}/@code{clone} syscall/ ?
Thanks for reworking the documentation!
Wow, a full 3 years later!
Well, better late than never...
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https://bugs.launchpad.net/bugs/1201446
Title:
Instructions not supported by targeted CPU do not throw SIGILL
Status in QE
I would like to use my two monitors with qemu. I was working before
with qemu & virtio, but then the fullscreen mode was not a problem.
But since, I have two monitors I cannot be in fullscreen mode otherwise
I lost the other monitor, can't use it. I heard that qxl could fix
this. When I star
igrations to
proceed regardless of what USB packets have been generated by the guest.
Signed-off-by: Jonathan Davies
---
hw/usb/bus.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/hw/usb/bus.c b/hw/usb/bus.c
index bf796d67e6..6fffab7bfa 100644
--- a/hw/usb/bus.c
+++ b/hw/us
Oh, I forgot, I should have also posted the relevant DTS contents:
pcie@1000 {
interrupt-map-mask = <0x1800 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 0x8001 0x0 0x0 0x0 0x3 0x4 0x0
0x0 0x0 0x2 0x8001 0x0 0x0 0x0 0x4 0x4 0x0 0x0 0x0 0x3 0x8001 0x0 0
Public bug reported:
This occurs on qemu_v3.0.0 but not on qemu_v2.12.2 (built from
qemu_v3.0.0 tag on github)
Symptom: You'll see something like this in the kernel output:
[1.285210] OF: PCI: host bridge /pcie@1000 ranges:
[1.286246] OF: PCI:IO 0x3eff..0x3eff -> 0x00
I tried to triage this a bit today.
I'm running a 32-bit linux kernel and I think that's the problem. The
ECAM address base is at 0x401000, but it gets truncated to
0x1000 because it's only a 32-bit kernel, but since it's truncated,
it conflicts with VIRT_PCIE_MMIO (see hw/arm/virt.c) who
** Summary changed:
- arm virt ecam pcie conflict
+ Default arm virt machine broken
** Description changed:
This occurs on qemu_v3.0.0 but not on qemu_v2.12.2 (built from
qemu_v3.0.0 tag on github)
Symptom: You'll see something like this in the kernel output:
[1.285210] OF: PCI
LPAE is actually disabled in my kernel config. Knowing the cause now, I
can see that qemu would not be able to detect this problem. This error
should have been detected in the linux kernel with an indication that
the ECAM window was using a 40-bit address but LPAE was not enabled.
** Changed in:
Public bug reported:
I was unable to figure out why my VM wasn't booting when I added a
"-initrd" image. I would launch qemu and get no output, and no error
message, it would just spin.
Turns out my initrd image was around 270 MB but I wasn't giving an
explicit ram size to qemu. I was told the
iliang
[...]
> +COLO Proxy:
> +Delivers packets to Primary and Seconday, and then compare the responses from
"Secondary"
> +both side. Then decide whether to start a checkpoint according to some rules.
"both sides"
Thanks,
Jonathan Neuschäfer
signature.asc
Description: PGP signature
Signed-off-by: Jonathan Neuschäfer
---
CODING_STYLE | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/CODING_STYLE b/CODING_STYLE
index e7fde15..a03a994 100644
--- a/CODING_STYLE
+++ b/CODING_STYLE
@@ -9,7 +9,7 @@ patches before submitting.
Of course, the most important aspect
On Thu, Sep 29, 2016 at 06:14:49PM -0300, Eduardo Habkost wrote:
> Add a new test case to ensure the existing behavior of the
> feature parsing code wlil be kept.
s/wlil/will/
>
> Signed-off-by: Eduardo Habkost
Jonathan Neuschäfer
signature.asc
Description: PGP signature
On Thu, Sep 29, 2016 at 03:14:45PM -0700, Peter Maydell wrote:
> On 29 September 2016 at 13:46, Jonathan Neuschäfer
> wrote:
> > Signed-off-by: Jonathan Neuschäfer
> > ---
> > CODING_STYLE | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> >
Signed-off-by: Jonathan Neuschäfer
---
v2:
- Preserve the poetic sound of "Many a flamewar", which Peter Maydell
pointed out.
---
CODING_STYLE | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/CODING_STYLE b/CODING_STYLE
index e7fde15..f53180b 100644
--- a/CODING_S
tatic void passthru_exitfn(CCIDCardState *base)
> {
> -return 0;
> +return;
> }
Have you compile-tested this change? I think you'll have to adjust the
definition of exitfn in CCIDCardClass, and ccid_card_exitfn (in
hw/usb/dev-smartcard-reader.c) as well.
Regards,
Jonathan Neuschäfer
signature.asc
Description: PGP signature
On 02/05/2018 04:08 AM, Tomáš Golembiovský wrote:
ping
On Tue, 5 Dec 2017 13:14:46 +0100
Tomáš Golembiovský wrote:
It would be good to include the corresponding upstream kernel change in
the commit message. This would be similar to a previous change:
https://lists.gnu.org/archive/html/q
qemu should read and report huge page allocation
statistics exported in the following kernel patch:
commit 01be4bb1aafeab73feba628c6dd120cd6647faae
Author: Jonathan Helman
Date: Thu Feb 15 10:59:03 2018 -0800
virtio_balloon: export huge page allocation statistics
Export
#x27;available' counter
>
> and
>
>commit bf1e7140ef0b3a149860ab9f05b36665133238f6
>Author: Tomáš Golembiovský
>Date: Tue Dec 5 13:14:46 2017 +0100
>
>virtio-balloon: include statistics of disk/file caches
>
> Signed-off-by: Tomáš Golemb
> On Feb 19, 2018, at 5:11 AM, Tomáš Golembiovský wrote:
>
> On Wed, 14 Feb 2018 00:07:53 +0200
> "Michael S. Tsirkin" wrote:
>
>> On Tue, Feb 13, 2018 at 12:29:39PM -0800, Jonathan Helman wrote:
>>>
>>>
>>> On 02/05/2018 04:08 AM, T
qemu should read and report hugetlb page allocation
counts exported in the following kernel patch:
commit 4c3ca37c4a4394978fd0f005625f6064ed2b9a64
Author: Jonathan Helman
Date: Mon Mar 19 11:00:35 2018 -0700
virtio_balloon: export hugetlb page allocation counts
Export the
defined in this array by the Linux kernel
do not match up with those defined internally by QEMU. This patch
fixes this inconsistency by changing the QEMU stat names to match
those defined by the Linux kernel.
Signed-off-by: Jonathan Helman
Cc: Rob Gardner
Cc: Thomas Tai
---
docs/virtio-balloon
Signed-off-by: Jonathan Marler
---
device_tree.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/device_tree.c b/device_tree.c
index 52c3358..2b75905 100644
--- a/device_tree.c
+++ b/device_tree.c
@@ -379,8 +379,12 @@ uint32_t qemu_fdt_get_phandle(void *fdt, const
nning as a guest inside the emulated host without kvm.
This is a bit too much of a case of Russian dolls so I'm not even sure
how to get any useful debug information.
Thanks,
Jonathan
>
> -- PMM
>
On Tue, 31 Mar 2020 16:33:24 +0100
Jonathan Cameron wrote:
> On Fri, 7 Feb 2020 11:52:46 +
> Peter Maydell wrote:
>
> > On Thu, 6 Feb 2020 at 10:54, Richard Henderson
> > wrote:
> > >
> > > Version 7 has one more tweak to the vhe tlb flushing
&
On Tue, 31 Mar 2020 11:59:13 -0700
Richard Henderson wrote:
> On 3/31/20 8:33 AM, Jonathan Cameron wrote:
> > Just wondering if there are any known issues with this?
>
> Nope. It works for me.
> Can you give us any more details.
>
Unfortunately not a lot more to ad
On Wed, 1 Apr 2020 11:45:22 +0100
Jonathan Cameron wrote:
> On Tue, 31 Mar 2020 11:59:13 -0700
> Richard Henderson wrote:
>
> > On 3/31/20 8:33 AM, Jonathan Cameron wrote:
> > > Just wondering if there are any known issues with this?
> >
> > Nope.
Which means that given an argument of type T * const this defines a
local variable that is also T * const, and then tries to store the
result of the atomic load into that const variable:
```
#define atomic_rcu_read(ptr) \
({
It looks like `typeof_strip_qual` doesn't work for pointer types.
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https://bugs.launchpad.net/bugs/1886155
Title:
error: argument 2 of ‘__atomic_load’ discards ‘const’ qualifier
Statu
On Wed, 2020-04-22 at 14:36 -0700, no-re...@patchew.org wrote:
> Patchew URL:
> https://patchew.org/QEMU/20200422171305.10923-1-jonathan.derr...@intel.com/
>
>
>
> Hi,
>
> This series failed the asan build test. Please find the testing commands and
> their output below. If you have Docker inst
On Wed, 2020-04-22 at 23:16 -0700, Christoph Hellwig wrote:
> On Wed, Apr 22, 2020 at 01:14:44PM -0400, Jon Derrick wrote:
> > The two patches (Linux & QEMU) add support for passthrough VMD devices
> > in QEMU/KVM. VMD device 28C0 already supports passthrough natively by
> > providing the Host Phys
P isn't
as widespread as it once was.
Jonathan
On Fri, May 1, 2020 at 2:54 PM Jose Martins wrote:
> Just resubmitted version 2. Sorry. Not really used to this. I actually
> wasn't using git send-email. I was copying the patch to my email
> client which was causing the weird wrapp
Public bug reported:
a qemu-hosted process segfaults when the program calls mremap to shrink
the size of a buffer to 4096 that was allocated with mmap. See below for
a C program to reproduce this issue. I was able to compile this program
for both i386 and 32-bit arm, and use qemu-i386 and qemu-ar
Thanks to @LemonBoy for finding this:
It looks like this issue my be caused by this chunk of code in linux-
user/mmap.c
if (prot == 0) {
host_addr = mremap(g2h(old_addr), old_size, new_size, flags);
if (host_addr != MAP_FAILED && reserved_va && old_size > new_size)
I've submitted a patch, this is my first qemu patch so sorry if I didn't
format it correctly: https://lists.gnu.org/archive/html/qemu-
trivial/2020-05/msg0.html
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https://bugs.launchpa
g
>
> Thanks,
> Laurent
>
> Le 02/05/2020 à 09:49, Jonathan Marler a écrit :
> > Signed-off-by: Jonathan Marler
> > ---
> > linux-user/mmap.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/linux-user/mmap.c b/linux-u
from the smaller new_size. Instead, it should be subtracting the
smaller new_size from the larger old_size. You can also see in the previous
line of the change that this mmap_reserve call only occurs when old_size >
new_size.
Signed-off-by: Jonathan Marler
---
linux-user/mmap.c | 2 +-
1 f
at 10:12 AM Jonathan Marler
wrote:
> Fixes: https://bugs.launchpad.net/bugs/1876373
>
> This code path in mmap occurs when a page size is decreased with mremap.
> When a section of pages is shrunk, qemu calls mmap_reserve on the pages
> that were released. However, it has the
FYI, first patch in the previous comment was wrong. This new patch is
the correct one: https://lists.gnu.org/archive/html/qemu-
devel/2020-05/msg00183.html
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perhaps silently succeeding.
Jonathan
On Wed, Sep 25, 2019 at 8:29 AM Guo Ren wrote:
> On Wed, Sep 25, 2019 at 1:19 PM Alistair Francis
> wrote:
> >
> > On Tue, Sep 24, 2019 at 9:48 PM wrote:
> > >
> > > From: Guo Ren
> > >
> > > Highe
bits, the spec says
nothing about what hardware should do, so both the old an the new
behavior are fine.
Jonathan
This patch enables a debugger to read and write the current privilege level via
a special "priv" register. When compiled with CONFIG_USER_ONLY the register is
still visible but is hardwired to zero.
Signed-off-by: Jonathan Behrens
---
gdb-xml/riscv-32bit-cpu.xml | 1 +
gdb-xml/r
want the guest version you access element
one. And if you want the version that the running code would see you index
by the virtualization mode. In any case, the choice indicates that you
thought though which was the right option to use in that instance.
Jonathan
On Tue, Jan 21, 2020 at 6:02 AM A
PM Palmer Dabbelt wrote:
> On Wed, 14 Aug 2019 20:19:39 PDT (-0700), jonat...@fintelia.io wrote:
> > Ping! What is the status of this patch?
>
> Sorry, I must have lost track of it. I've added it to my patch queue.
>
> >
> > On Wed, Jul 3, 2019 at 2:02 PM Jo
This series doesn't seem to touch mcounteren.TM which should be hardwired
to zero if no callback in provided, and writable otherwise. (I had a patch
to do the hardwiring unconditionally, but it seems to have been
accidentally dropped.) Other than that, I think the design is quite good.
Jon
Looks good to me. Though this is I think the third bug in privilege
checking in op_helper.c which is only like 150 lines long total. It would
be really good to fully double check that there aren't any more lurking
there...
Reviewed-by: Jonathan Behrens >
On Tue, Jan 21, 2020 at 12:45 AM
I don't think this was ever merged?
On Wed, Jul 3, 2019 at 10:37 PM wrote:
> Patchew URL:
> https://patchew.org/QEMU/20190703190715.5328-1-jonat...@fintelia.io/
>
>
>
> Hi,
>
> This series failed the asan build test. Please find the testing commands
> and
> their output below. If you have Docker
out having to understand anything. However, I'd attribute that more to
luck than elegance of a particular option.
Jonathan
On Tue, Jan 21, 2020 at 7:01 PM Alistair Francis
wrote:
> On Tue, Jan 21, 2020 at 10:56 PM Jonathan Behrens
> wrote:
> >
> > When I looked through
s S-mode to selectively permit WFI in U-mode."
Signed-off-by: Jonathan Behrens
Reviewed-by: Alistair Francis
---
target/riscv/op_helper.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 331cc36232..2e5a
new version with that changed.
Jonathan
On Thu, Jan 23, 2020 at 6:35 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 1/23/20 9:52 AM, Jonathan Behrens wrote:
> > +if (!(env->priv >= PRV_S) ||
>
> For integers, !(x >= y) is a poor way to write x < y.
>
>
> r~
>
>
d in Qemu etc.
https://wiki.qemu.org/Contribute/SubmitAPatch (follow like to kernel policy
that talks
more about this)
Comments below are mostly minor stylistic things. There is just
enough here that I want to take a look at v5 before giving a Reviewed-by tag.
Thanks,
Jonathan
> ---
&g
On Wed, 31 Mar 2021 12:36:58 -0400
Chris Browy wrote:
> From: hchkuo
Again, must have a description, plus a sign off from Chris if Chris is
the person sending the patch out.
>
> Signed-off-by: hchkuo
Please split this into 2 patches. Add the DOE + CDAT in first patch, and
compliance in the
standard-headers at least should come via scripts
(break that one out to a separate patch to make life easier)
Jonathan
> ---
> include/hw/pci/pci_ids.h | 2 ++
> include/hw/pci/pcie_regs.h| 3 +++
> include/standard-headers/linux/pci_regs.h | 3 ++-
ou have it implemented - right now it's just unwanted noise
in this patch.
Thanks,
Jonathan
> ---
> MAINTAINERS | 49 +--
> hw/pci/meson.build| 1 +
> hw/pci/pci.c | 13 +-
> hw/pci/pcie_doe.c
On Tue, 9 Mar 2021 16:04:36 -0500
Chris Browy wrote:
Hi Chris,
As for patch 1, description needed here. Let's move this series towards
the form needed for a final submission.
2 features, 2 patches... If nothing else makes each one small enough to be
suitable for review with morning coffee :)
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