On 2022/7/28 下午10:03, Igor Mammedov wrote:
On Tue, 12 Jul 2022 16:32:05 +0800
Xiaojuan Yang wrote:
Loongarch virt machine uses general hardware reduces acpi method, rather
than LS7A acpi device. Now only power management function is used in
acpi ged device, memory hotplug will be added later
Cc: Richard
Apply to 7.1?
On 2022/8/4 下午9:24, Qi Hu wrote:
The macros SET_FPU_* are used to set corresponding bits of fcsr.
Unfortunately it forgets to set the result and it causes fcsr's
"CAUSE" never being updated. This patch is to fix this bug.
Signed-off-by: Qi Hu
---
target/loongarch/c
Ping for 7.1
On 2022/7/24 上午11:27, Richard Henderson wrote:
On 7/21/22 09:30, Song Gao wrote:
Fix a compiler warning on openbsd:
../src/hw/loongarch/acpi-build.c:416:12: warning: variable 'aml_len'
set but not used [-Wunused-but-set-variable]
size_t aml_len = 0;
^
Reported-by:
On 2022/8/7 上午1:08, Richard Henderson wrote:
All of the fpu operations are defined with TCG_CALL_NO_WG, but they
all modify FCSR0. The most efficient way to fix this is to remove
cpu_fcsr0, and instead use explicit load and store operations for the
two instructions that manipulate that value.
CC: Huacai Chen
On 2022/8/11 下午9:24, Waldemar Brodkorb wrote:
Hi Qemu developers,
I am trying to bootup a loongarch64 Linux kernel in Qemu 7.1.0-rc2.
The problem is I get no output when using following command:
qemu-system-loongarch64 -M virt -nographic -kernel vmlinux
You can find my vmlinux
On 2022/8/12 下午5:19, Xiaojuan Yang wrote:
1. Add some information about how to boot the LoongArch virt
machine by uefi bios and linux kernel and how to access the
source code or binary file.
2. Move the explanation of LoongArch system emulation in the
target/loongarch/README to docs/system/loon
ping !
在 2023/7/14 下午4:45, Song Gao 写道:
Hi,
This series adds LoongArch LASX instructions.
About test:
We use RISU test the LoongArch LASX instructions.
QEMU:
https://github.com/loongson/qemu/tree/tcg-old-abi-support-lasx
RISU:
https://github.com/loongson/risu/tree/loongarch-suport-l
Cc: Jun Yi
在 2023/8/6 下午10:13, Jiajie Chen 写道:
This commit introduces new loongarch32-softmmu target. Compared to
loongarch64-softmmu, the new target is different at least in:
- GPRs and CSRs are 32-bits wide, but FPRs are still 64-bits wide
- LA32 lacks some 64-bit-only instructions
- CSR.DMW
在 2023/8/7 上午10:31, gaosong 写道:
Cc: Jun Yi
CC: shenjiny...@loongson.cn
在 2023/8/6 下午10:13, Jiajie Chen 写道:
This commit introduces new loongarch32-softmmu target. Compared to
loongarch64-softmmu, the new target is different at least in:
- GPRs and CSRs are 32-bits wide, but FPRs are still
Hi, Jiajie
在 2023/8/7 下午1:17, Jiajie Chen 写道:
On 2023/8/7 11:18, Jiajie Chen wrote:
The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
zero in LoongArch32.
Signed-off-by: Jiajie Chen
---
target/loongarch/cpu-csr.h | 9 +
target/loongarch/tlb_helper.c | 17 ++
si-map';
[1]:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/arch/loongarch/booting.rst?h=v6.7-rc4
[2]: https://github.com/gaosong-loongson/loongarch-binary/releases
Please review!
Thanks.
Song Gao
Song Gao (17):
hw/loongarch: Move boot fucntion
Hi,
Title 'target/loongarch: ' ...
Thanks.
Song Gao
在 2024/2/28 14:55, Xianglai Li 写道:
The lddir and ldpte instruction emulation has
a problem with the use of large page processing above level 2.
The page size is not correctly calculated,
resulting in the wrong page size of the table entry
在 2024/3/4 10:18, Bibo Mao 写道:
In structure CPUArchState some struct elements are only used in TCG
mode, and it is not used in KVM mode. Macro CONFIG_TCG is added to
make it simpiler in KVM mode, also there is the same modification
in c code when these struct elements are used.
When VM runs in
在 2024/2/27 10:30, Bibo Mao 写道:
The minimum memory size for LoongArch UEFI bios is 256M, also some
test cases such as migration and qos use 256M memory by default.
Here set minimum memory size for Loongarch VirtMachine with 256M rather
than 1G, so that test cases with 256M memory can pass to
在 2024/2/20 20:41, Bibo Mao 写道:
Since migration test case requires compat machine type support,
compat machine is added for qemu 9.0 here.
Signed-off-by: Bibo Mao
---
hw/loongarch/virt.c | 60 +++--
1 file changed, 47 insertions(+), 13 deletions(-)
在 2024/2/27 10:30, Bibo Mao 写道:
Since migration test case requires compat machine type support,
compat machine is added for qemu 9.0 here.
Signed-off-by: Bibo Mao
---
hw/loongarch/virt.c | 60 +++--
1 file changed, 47 insertions(+), 13 deletions(-)
6 16:56:20 +)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240307
for you to fetch changes up to 4dc2edfd6f8abfc38f0ba110502790aa5051b1b5:
hw/loongarch: Add cells missing from rtc node (2024-03-07 21:5
)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240307
for you to fetch changes up to 4dc2edfd6f8abfc38f0ba110502790aa5051b1b5:
hw/loongarch: Add cells missing from rtc node (2024-03-07 21:5
oot_rom' at [0 - 1M], the 'boot_rom' includes
slave_boot_code, cmdline_buf and systab_tables;
- R-b and rebase.
V2:
- FDT pcie node adds cells 'msi-map';
[1]:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/arch/loongarch/boot
在 2024/2/19 下午6:34, Xianglai Li 写道:
The UEFI loading mode in loongarch is very different
from that in other architectures:loongarch's UEFI code
is in rom, while other architectures' UEFI code is in flash.
loongarch UEFI can be loaded as follows:
-machine virt,pflash=pflash0-format
-bios ./QEMU_E
in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240221
for you to fetch changes up to be57fd1e526e70fd55f1e87b0b70fab3c6baf089:
loongarch: Change the UEFI loading mode to loongarch (2024-02-21 17:06
在 2024/2/23 上午11:03, Richard Henderson 写道:
The upstream linux kernel does not define __ARCH_FORCE_SHMLBA.
Cc: Song Gao
Signed-off-by: Richard Henderson
---
Did this definition come from the port before it was merged upstream?
Yes,
The patch [1] dropped it .
[1]
https://patchew.org/li
在 2024/2/1 上午5:16, Richard Henderson 写道:
On 1/31/24 17:27, Song Gao wrote:
It seems that tcg_reg_alloc_op() set const_args[i] wrong value
when instructions imm is 0. The LoongArch tcg_out_vec_op() cmp_vec
use the wrong const_args[2].
e.g
The wrong const_args[2] is 0.
IN: vslti.w v5, v4,
在 2024/2/2 上午7:34, Richard Henderson 写道:
Because there are more call clobbered registers than
call saved registers, we begin with all registers as
call clobbered and then reset those that are saved.
This was missed when we introduced the LSX support.
Cc: qemu-sta...@nongnu.org
Fixes: 16288ded94
在 2024/3/21 上午10:50, Richard Henderson 写道:
On 3/20/24 16:11, Song Gao wrote:
qemu-system-loongarch64 assert failed with the option '-d int',
the helper_idle() raise an exception EXCP_HLT, but the exception name
is undefined.
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 75 +
在 2024/3/22 上午1:13, Michael Tokarev 写道:
20.03.2024 05:40, Song Gao :
On gen_ll, if a->imm is zero, make_address_x return src1,
but the load to destination may clobber src1. We use a new
destination to fix this problem.
Fixes: c5af6628f4be (target/loongarch: Extract make_address_i() helper)
Revi
Cc: qemu-sta...@nongnu.org
在 2024/3/22 下午10:58, Michael Tokarev 写道:
22.03.2024 13:03, Song Gao :
qemu-system-loongarch64 assert failed with the option '-d int',
the helper_idle() raise an exception EXCP_HLT, but the exception name
is undefined.
Signed-off-by: Song Gao
Reviewed-by: Philippe
在 2024/3/8 16:36, Philippe Mathieu-Daudé 写道:
Hi Song,
On 7/3/24 17:48, Song Gao wrote:
Signed-off-by: Song Gao
Message-Id: <20240301093839.663947-8-gaos...@loongson.cn>
---
hw/loongarch/boot.c | 23 +--
include/hw/loongarch/boot.h | 9 +
2 files chan
在 2024/3/8 16:27, maobibo 写道:
On 2024/3/8 上午12:48, Song Gao wrote:
Signed-off-by: Song Gao
Message-Id: <20240301093839.663947-4-gaos...@loongson.cn>
---
hw/loongarch/boot.c | 70 -
1 file changed, 69 insertions(+), 1 deletion(-)
diff --git a/
在 2024/3/8 16:37, maobibo 写道:
On 2024/3/8 上午12:48, Song Gao wrote:
Signed-off-by: Song Gao
Message-Id: <20240301093839.663947-7-gaos...@loongson.cn>
---
hw/loongarch/boot.c | 39 +
hw/loongarch/virt.c | 11 ++-
include/hw/loon
在 2024/3/14 9:31, maobibo 写道:
On 2024/3/11 下午2:50, maobibo wrote:
On 2024/3/8 下午5:36, gaosong wrote:
在 2024/3/8 16:27, maobibo 写道:
On 2024/3/8 上午12:48, Song Gao wrote:
Signed-off-by: Song Gao
Message-Id: <20240301093839.663947-4-gaos...@loongson.cn>
---
hw/loongarch/boot.
在 2024/3/14 10:28, chen huacai 写道:
Song,
On Fri, Mar 8, 2024 at 12:51 AM Song Gao wrote:
Signed-off-by: Song Gao
Message-Id: <20240301093839.663947-4-gaos...@loongson.cn>
---
hw/loongarch/boot.c | 70 -
1 file changed, 69 insertions(+), 1 del
在 2024/3/13 下午5:39, Bibo Mao 写道:
Interrupt number in loop sentence should be base irq plus
loop index, it is missing on checking whether the irq
is pending.
Fixes: 428a6ef4396 ("Add vmstate post_load support")
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_extioi.c | 2 +-
1 file changed, 1 i
在 2024/4/28 上午9:15, maobibo 写道:
On 2024/4/26 下午5:15, Song Gao wrote:
Message text is missing here :(
Signed-off-by: Song Gao
Message-Id: <20240307164835.300412-4-gaos...@loongson.cn>
It is strange that there is "Message-Id:" string. Is it required here?
Message_ID helps to find the origi
在 2024/4/28 上午9:34, maobibo 写道:
On 2024/4/26 下午5:15, Song Gao wrote:
Message test is also missing there :(
Signed-off-by: Song Gao
Message-Id: <20240307164835.300412-7-gaos...@loongson.cn>
---
include/hw/loongarch/boot.h | 27 +
include/hw/loongarch/virt.h | 10 ++
在 2024/4/29 上午2:59, Richard Henderson 写道:
On 4/28/24 01:51, Song Gao wrote:
we load initrd ramdisk after kernel_high address
Signed-off-by: Song Gao
Reviewed-by: Bibo Mao
Message-Id: <20240426091551.2397867-3-gaos...@loongson.cn>
---
hw/loongarch/boot.c | 29 -
在 2024/4/28 上午11:16, Bibo Mao 写道:
On Loongarch, cpucfg is register for cpu feature, some other registers
depend on cpucfg feature such as perf CSR registers. Here put cpucfg
read/write operations before CSR register, so that KVM knows how many
perf CSR registers are valid from pre-set cpucfg feat
在 2024/3/19 上午10:26, Bibo Mao 写道:
With numa_test test case, there is subcase named test_def_cpu_split(),
there are 8 sockets and 2 numa nodes. Here is command line:
"-machine smp.cpus=8,smp.sockets=8 -numa node,memdev=ram -numa node"
The required result is:
node 0 cpus: 0 2 4 6
node 1 cpus
Hi,
在 2024/3/18 下午4:01, Bibo Mao 写道:
One LoongArch virt machine platform, there is limitation for memory
map information. The minimum memory size is 256M and minimum memory
size for numa node0 is 256M also. With qemu numa qtest, it is possible
that memory size of numa node0 is 128M.
Limitations
在 2024/5/3 下午8:50, Peter Maydell 写道:
On Fri, 16 Jun 2023 at 11:03, Song Gao wrote:
From: Tianrui Zhao
1. Implement some functions for LoongArch numa support;
2. Implement fdt_add_memory_node() for fdt;
3. build_srat() fills node_id and adds build numa memory.
Reviewed-by: Song Gao
Signed-of
Thanks for the comments !
在 2024/5/2 下午8:45, Fabiano Rosas 写道:
Peter Xu writes:
On Tue, Apr 30, 2024 at 11:00:24AM -0300, Fabiano Rosas wrote:
Philippe Mathieu-Daudé writes:
(Cc'ing migration maintainers)
On 30/4/24 03:23, Song Gao wrote:
vmstate does not save kvm_state_conter,
which
在 2024/5/7 下午5:52, Michael Tokarev 写道:
07.05.2024 05:22, Song Gao wrote:
for (i = 1; i < nb_numa_nodes; i++) {
MemoryRegion *nodemem = g_new(MemoryRegion, 1);
- ramName = g_strdup_printf("loongarch.node%d.ram", i);
+ g_autofree char *ramName =
g_strdup_printf("loo
在 2024/5/10 下午5:12, Richard Henderson 写道:
TCG register spill/fill uses tcg_out_ld/st with all types,
not necessarily going through INDEX_op_{ld,st}_vec.
Cc: qemu-sta...@nongnu.org
Fixes: 16288ded944 ("tcg/loongarch64: Lower basic tcg vec ops to LSX")
Resolves: https://gitlab.com/qemu-project/qem
在 2022/12/28 上午11:07, Bibo Mao 写道:
In theory gsi base can start from 0 on loongarch virt machine,
however gsi base is hard-coded in linux kernel loongarch system,
else system fails to boot.
This patch renames macro PCH_PIC_IRQ_OFFSET with VIRT_GSI_BASE,
keeps value unchanged. GSI base is commo
在 2023/3/28 上午1:44, Richard Henderson 写道:
On 3/27/23 04:23, Tianrui Zhao wrote:
The virt addr should mask TARGET_PHYS_ADDR_SPACE_BITS to
get the phys addr, and this is used by loading kernel elf.
Signed-off-by: Tianrui Zhao
---
hw/loongarch/virt.c | 2 +-
1 file changed, 1 insertion(+), 1
在 2023/3/29 上午3:56, Richard Henderson 写道:
@@ -33,7 +33,39 @@ const VMStateDescription vmstate_loongarch_cpu = {
VMSTATE_UINTTL_ARRAY(env.gpr, LoongArchCPU, 32),
VMSTATE_UINTTL(env.pc, LoongArchCPU),
- VMSTATE_UINT64_ARRAY(env.fpr, LoongArchCPU, 32),
+ VMSTATE_
在 2023/3/29 上午3:42, Richard Henderson 写道:
On 3/27/23 20:05, Song Gao wrote:
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -52,6 +52,7 @@ static const char * const excp_names[] = {
[EXCCODE_FPE] = "Floating Point Exception",
[EXCCODE_DBP] = "Debug breakpoint",
[
在 2023/3/29 上午4:17, Richard Henderson 写道:
On 3/27/23 20:05, Song Gao wrote:
+#define DO_ODD_EVEN_S(NAME, BIT, T, E1, E2, DO_OP) \
+void HELPER(NAME)(CPULoongArchState *env, \
+ uint32_t vd, uint32_t vj, uint32_t vk) \
+{
在 2023/3/29 上午3:59, Richard Henderson 写道:
On 3/27/23 20:05, Song Gao wrote:
+ func(mop, vd_ofs, vj_ofs, vk_ofs, 16, 16);
Oh, reading about ASXD and 256-bit vectors makes me wonder if it would
be better to plan ahead and have a function, or DisasContext member,
for the length of the vect
just too old?
Yes.
[gaosong@kvm-dev1 BIOS]$ loongarch64-unknown-linux-gnu-gcc --version
loongarch64-unknown-linux-gnu-gcc (GCC) 13.0.0 20220906 (experimental)
See:
https://github.com/tianocore/edk2-platforms/tree/master/Platform/Loongson/LoongArchQemuPkg#readme
or
docs/system/loongarch/virt.rst
在 2023/4/2 下午1:17, Richard Henderson 写道:
On 3/27/23 20:06, Song Gao wrote:
This patch includes:
- VFRSTP[I].{B/H}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 5 +++
target/loongarch/helper.h | 5 +++
target/loongarch/insn_trans/trans_lsx.
Hi, Richard
在 2023/4/1 下午1:03, Richard Henderson 写道:
On 3/27/23 20:06, Song Gao wrote:
+static void gen_vsat_s(unsigned vece, TCGv_vec t, TCGv_vec a,
int64_t imm)
+{
+ TCGv_vec t1;
+ int64_t max = (1l << imm) - 1;
This needed 1ull, but better to just use
max = MAKE_64BIT_MASK(0,
在 2023/4/4 上午4:13, Richard Henderson 写道:
On 4/3/23 05:55, gaosong wrote:
Hi, Richard
在 2023/4/1 下午1:03, Richard Henderson 写道:
On 3/27/23 20:06, Song Gao wrote:
+static void gen_vsat_s(unsigned vece, TCGv_vec t, TCGv_vec a,
int64_t imm)
+{
+ TCGv_vec t1;
+ int64_t max = (1l <&l
HI, Richard
在 2023/3/29 上午4:46, Richard Henderson 写道:
+static void do_vmuh_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
+ uint32_t vk_ofs, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen3 op[4] = {
+ {
+ .fno = gen_helper_vmuh_b,
+
在 2023/4/4 下午9:27, Alex Bennée 写道:
The calling function is already working with hwaddr and uint64_t so
lets avoid bringing target_ulong in if we don't need to.
Signed-off-by: Alex Bennée
---
hw/intc/loongarch_ipi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Song Ga
Ping~
在 2023/3/28 下午5:35, Song Gao 写道:
The parameter '--disable-werror' is not required
when building the 'loongarch64-linux-user' target.
Fixes: c32b3fec34 ("target/loongarch: Update README")
Reported-by: Philippe Mathieu-Daudé
Signed-off-by: Song Gao
---
target/loongarch/README | 2 +-
1
在 2023/4/2 上午11:34, Richard Henderson 写道:
On 3/27/23 20:06, Song Gao wrote:
+#define DO_CLO_B(N) (clz32((uint8_t)~N) - 24)
+#define DO_CLO_H(N) (clz32((uint16_t)~N) - 16)
I think this is wrong.
It is wried, the result is always right. :-\
and (clz32(~N) - 24) or (clz32((uint32_t)~N) -
在 2023/4/4 上午9:03, Richard Henderson 写道:
+void HELPER(vseteqz_v)(CPULoongArchState *env, uint32_t cd, uint32_t
vj)
+{
+ VReg *Vj = &(env->fpr[vj].vreg);
+ env->cf[cd & 0x7] = (Vj->Q(0) == 0);
+}
+
+void HELPER(vsetnez_v)(CPULoongArchState *env, uint32_t cd, uint32_t
vj)
+{
+ VReg *Vj
Ping !
在 2023/1/12 下午2:11, Song Gao 写道:
For loongarch virt machine, add powerdown notification callback
and send ACPI_POWER_DOWN_STATUS event by acpi ged. Also add
acpi dsdt table for ACPI_POWER_BUTTON_DEVICE device in this
patch.
Signed-off-by: Song Gao
---
hw/loongarch/acpi-build.c | 1
Hi Richard,
On 2021/11/12 下午3:39, Richard Henderson wrote:
On 11/12/21 7:53 AM, Song Gao wrote:
+const char * const fccregnames[8] = {
+ "$fcc0", "$fcc1", "$fcc2", "$fcc3", "$fcc4", "$fcc5", "$fcc6",
"$fcc7",
+};
static.
OK.
+static void output_fcsrdrj(DisasContext *ctx, arg_fmt_fcsrdrj
Hi Richard,
On 2021/11/12 下午10:05, Richard Henderson wrote:
On 11/12/21 7:53 AM, Song Gao wrote:
+#
+# Fields
+#
+%rd 0:5
+%rj 5:5
+%rk 10:5
+%sa2 15:2
+%si12 10:s12
+%ui12 10:12
+%si16 10:s16
+%si20 5:s20
You should only create separate field definitions like
Hi Philippe,
On 2021/11/16 下午4:33, Philippe Mathieu-Daudé wrote:
Hi,
On 11/12/21 07:54, Song Gao wrote:
This includes:
- sockbits.h
- target_errno_defs.h
- target_fcntl.h
- termbits.h
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
linux-user/loongarch64/sockbits.h | 1 +
Hi Richard,
On 2021/11/15 下午4:42, Richard Henderson wrote:
On 11/15/21 4:59 AM, gaosong wrote:
'The width of the immediate is a detail of the format' means:
&fmt_rdrjimm rd rj imm
@fmt_rdrjimm .. imm:12 rj:5 rd:5 &fmt_rdrjimm
@fmt_rdrjimm14
Hi Richard,
On 2021/11/17 下午4:28, Richard Henderson wrote:
On 11/17/21 8:57 AM, gaosong wrote:
I see that insns.decode format is not very consistent with other
architectures, such ARM/RISCV
No. I don't like how riscv has done it, though they have quite a few
split fields, so perhaps
Hi Richard,
On 2021/11/17 下午5:55, Richard Henderson wrote:
@fmt_rr_i12 and @fmt_rr_ui12 are two 'Formats', but they use the
same 'Argument sets'(rr_i).
What I meant is that there would be a single gen_rr_i function handing
the argument set rr_i; no need for two gen_rr_i* functions.
Got
Hi Richard,
On 2021/11/20 下午3:17, Richard Henderson wrote:
On 11/19/21 7:13 AM, Song Gao wrote:
+static bool gen_rrr(DisasContext *ctx, arg_rrr *a,
+ DisasExtend src1_ext, DisasExtend src2_ext,
+ DisasExtend dst_ext, void (*func)(TCGv, TCGv,
TCGv))
+{
+
Hi Richard,
On 2021/11/20 下午3:42, Richard Henderson wrote:
On 11/19/21 7:13 AM, Song Gao wrote:
+static bool gen_shift(DisasContext *ctx, arg_rr_i *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv dest = gpr_dst(ctx, a->rd, EXT_SIGN);
+ TCGv src1 = gpr_src(ctx, a->rj, EX
Hi Richard,
Sorry for the late reply.
On 2021/11/20 下午4:56, Richard Henderson wrote:
On 11/20/21 9:52 AM, gaosong wrote:
You're right, gen_set_gpr not need EXT_NONE at all, and we need not
condition around gen_set_gpr.
I think that if we know the dst_ext is EXT_NONE, we do't need
g
Hi Richard,
On 2021/11/20 下午6:33, Richard Henderson wrote:
Drop all of the the inline markers.
+{
+ int i;
+
+ __put_user(env->pc, &sc->sc_pc);
+
+ __put_user(0, &sc->sc_gpr[0]);
+ for (i = 1; i < 32; ++i) {
+ __put_user(env->gpr[i], &sc->sc_gpr[i]);
+ }
+
+ for (i =
Hi Richard,
On 2021/11/20 下午6:33, Richard Henderson wrote:
On 11/19/21 7:13 AM, Song Gao wrote:
+
+struct target_sigcontext {
+ uint64_t sc_pc;
+ uint64_t sc_gpr[32];
+ uint64_t sc_fpr[32];
+ uint64_t sc_fcc;
+ uint32_t sc_fcsr;
+ uint32_t sc_flags;
+};
Does not
Hi Richard,
On 2021/11/24 下午3:27, Richard Henderson wrote:
On 11/24/21 3:46 AM, gaosong wrote:
Hi Richard,
On 2021/11/20 下午6:33, Richard Henderson wrote:
On 11/19/21 7:13 AM, Song Gao wrote:
+
+struct target_sigcontext {
+ uint64_t sc_pc;
+ uint64_t sc_gpr[32];
+ uint64_t
Hi Richard,
On 2021/11/20 下午6:33, Richard Henderson wrote:
+{
+ int i;
+
+ __put_user(env->pc, &sc->sc_pc);
+
+ __put_user(0, &sc->sc_gpr[0]);
+ for (i = 1; i < 32; ++i) {
+ __put_user(env->gpr[i], &sc->sc_gpr[i]);
+ }
+
+ for (i = 0; i < 32; ++i) {
+ __put_user(en
Hi Richard,
On 2021/11/20 下午6:33, Richard Henderson wrote:
+/* this struct defines a stack used during syscall handling */
+typedef struct target_sigaltstack {
+ abi_long ss_sp;
+ abi_int ss_flags;
+ abi_ulong ss_size;
+} target_stack_t;
+
+/*
+ * sigaltstack controls
+ */
+
Hi,
On 2021/11/25 下午6:08, WANG Xuerui wrote:
+
+#define TARGET_MINSIGSTKSZ 2048
While all the architectures you de-duplicated here have
TARGET_MINSIGSTACKSZ as 2048, some others specify a different value
(mostly 4096, e.g. alpha), as can be seen in your next patch (which
should belong to thi
On 2022/6/24 上午9:20, Richard Henderson wrote:
On 6/23/22 17:45, maobibo wrote:
在 2022/6/24 07:34, Richard Henderson 写道:
On 6/23/22 01:55, Song Gao wrote:
+static void setup_sigcontext(CPULoongArchState *env,
+ struct target_sigcontext *sc,
+
Hi, Richard
On 2022/6/24 上午11:10, Song Gao wrote:
Hi All,
This series adds support linux-user emulation.
As the LoongArch kernel had merged into 5.19-rc1,
you can see the latest kernel at https://kernel.org
Need review patch:
0002-linux-user-Add-LoongArch-signal-support.patch
V20:
- Up
Hi, Richard
On 2022/7/3 下午4:59, Richard Henderson wrote:
Hi. This is Song Gao's v20 [1], with patch 2 extensively rewritten
so that it handles lock_user properly. It compiles, but I need
to update the docker image we produced last year so that I can
properly test this.
In the meantime, Song,
On 2022/7/4 下午1:18, Richard Henderson wrote:
On 7/1/22 15:04, Xiaojuan Yang wrote:
By the manual of LoongArch CSR, the VS field(18:16 bits) of
ECFG reg means that the number of instructions between each
exception entry is 2^VS.
Is it a typo in the manual that says "2VS", i.e. multiplication?
On 2022/7/4 下午1:37, Richard Henderson wrote:
On 7/1/22 15:04, Xiaojuan Yang wrote:
By the document of ipi mailsend device, byte is written only when the
mask bit
is 0. The original code discards mask bit and overwrite the data
always, this
patch fixes the issue.
Signed-off-by: Xiaojuan Yang
On 2022/7/4 下午1:28, Richard Henderson wrote:
On 7/1/22 15:04, Xiaojuan Yang wrote:
+static const MemoryRegionOps loongarch_ipi64_ops = {
+ .write = loongarch_ipi_writeq,
+ .impl.min_access_size = 8,
+ .impl.max_access_size = 8,
+ .valid.min_access_size = 4,
+ .valid.max_access_si
On 2022/7/5 下午4:28, Richard Henderson wrote:
Remove toy_val_to_time_mon and toy_val_to_time_year as unused,
and to avoid a build failure with clang. Remove all of the
other inline markers foo so that this does not creep back in.
Signed-off-by: Richard Henderson
---
Sorry for this problem,
On 2022/7/5 下午4:36, Richard Henderson wrote:
There is nothing in this environment variable that cannot
be done better with -d flags. There is nothing special
about TCI that warrants this hack.
Moreover, it does not compile -- remove it.
Reported-by: Song Gao
Signed-off-by: Richard Henderson
在 2023/4/12 下午2:53, Richard Henderson 写道:
+#define SETANYEQZ(NAME, BIT, E) \
+void HELPER(NAME)(CPULoongArchState *env, uint32_t cd, uint32_t vj) \
+{ \
+ int i; \
+ bool ret = false;
在 2023/4/13 下午6:06, Richard Henderson 写道:
On 4/13/23 04:53, gaosong wrote:
在 2023/4/12 下午2:53, Richard Henderson 写道:
+#define SETANYEQZ(NAME, BIT, E) \
+void HELPER(NAME)(CPULoongArchState *env, uint32_t cd, uint32_t
vj
在 2023/4/14 上午11:22, gaosong 写道:
在 2023/4/13 下午6:06, Richard Henderson 写道:
On 4/13/23 04:53, gaosong wrote:
在 2023/4/12 下午2:53, Richard Henderson 写道:
+#define SETANYEQZ(NAME, BIT, E) \
+void HELPER(NAME)(CPULoongArchState *env, uint32_t cd, uint32_t
vj
Hi, Richard
在 2022/12/25 上午5:12, Richard Henderson 写道:
On 12/24/22 00:16, Song Gao wrote:
+TRANS(vreplve_b, gen_vvr, gen_helper_vreplve_b)
+TRANS(vreplve_h, gen_vvr, gen_helper_vreplve_h)
+TRANS(vreplve_w, gen_vvr, gen_helper_vreplve_w)
+TRANS(vreplve_d, gen_vvr, gen_helper_vreplve_d)
+TRANS(vr
在 2023/3/21 下午11:55, Richard Henderson 写道:
On 3/21/23 04:31, gaosong wrote:
but for this case.
e.g
vreplve_b vd vj, rk
index = gpr[rk] % (128/8);
Vd->B(i) = Vj->B(index);
tcg_gen_gvec_dup_mem(MO_8, vreg_full_offset(a->vd),
offsetof(CPULoongArchState, fpr[a->vj].vreg.B(inde
Hi Xuerui,
On 2021/11/1 下午6:45, WANG Xuerui wrote:
While I can see this patch and the next one are clearly from me, my
author info is lost as I didn't spot any "From:" line in the mail body?
Also I don't remember seeing "Base-on" tags in QEMU either.
Sorry, I refer to the commit 35f171a2eb25f
Hi,
On 2021/11/2 下午4:38, Philippe Mathieu-Daudé wrote:
On 11/1/21 10:51, Song Gao wrote:
This patch adds target state header, target definitions
and initialization routines.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
target/loongarch/cpu-param.
Hi Richard.
On 2022/1/7 下午1:01, Richard Henderson wrote:
On 1/6/22 1:41 AM, Song Gao wrote:
Based-on:<20220106074740.1754661-1-gaos...@loongson.cn>
Hi all,
This series only support linux-user emulation.
More about LoongArch at:https://github.com/loongson/
The latest kernel:
*https://githu
Hi Philippe,
On 2022/1/4 下午9:20, Philippe Mathieu-Daudé wrote:
Generated on Loongson-3A5000 (CPU revision 0x0014c011).
Signed-off-by: Philippe Mathieu-Daudé
---
tests/tcg/loongson64/float_convs.ref | 748 ++
tests/tcg/loongson64/float_madds.ref | 768
Hi Laurent,
On 2022/1/6 下午6:46, Laurent Vivier wrote:
make the LTP testsuite (20200930) happy again (capset02, prctl01,
prctl02, prctl03)?
Do we have LTP test documents? or What test methods do we have for linux-user?
As for far, I konw 'make check ' ,'make check-tcg'. and some testcases
Hi,
On 2022/1/10 上午2:49, Richard Henderson wrote:
+static bool loongarch_cpu_has_work(CPUState *cs)
+{
+ return true;
Note: this is only applicable to CONFIG_USER_ONLY, and needs to be
changed in the following commits adding system emulation. To better
convey your intention it may be bett
Hi,
On 2022/1/9 下午5:25, WANG Xuerui wrote:
+
+const char * const fregnames[32] = {
+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
+ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
+ "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+ "f24", "f25", "f26", "f27", "f28",
Hi,
On 2022/1/9 下午5:25, WANG Xuerui wrote:
+ data = FIELD_DP32(data, CPUCFG16, L1_DPRE, 1);
+ data = FIELD_DP32(data, CPUCFG16, L2_IUPRE, 1);
+ data = FIELD_DP32(data, CPUCFG16, L2_IUUNIFY, 1);
+ data = FIELD_DP32(data, CPUCFG16, L2_IUPRIV, 1);
+ data = FIELD_DP32(data, CPUCFG16,
Hi,
On 2022/1/12 下午5:28, gaosong wrote:
+ data = FIELD_DP32(data, CPUCFG16, L3_IUUNIFY, 1);
+ data = FIELD_DP32(data, CPUCFG16, L3_IUINCL, 1);
+ env->cpucfg[16] = data;
+
+ data = 0;
+ data = FIELD_DP32(data, CPUCFG17, L1IU_WAYS, 0x8003);
This seems out-of-place, according
在 2022/8/17 上午10:36, chen huacai 写道:
Hi, Richard and Xuerui,
On Mon, Aug 15, 2022 at 4:54 AM Richard Henderson
wrote:
On 8/14/22 09:55, WANG Xuerui wrote:
From: WANG Xuerui
The only LoongArch CPU implemented is modeled after the Loongson 3A5000,
but it is not the real thing, ...
The 3A50
Hi, Richard
在 2022/12/25 上午1:48, Richard Henderson 写道:
On 12/24/22 00:16, Song Gao wrote:
+TRANS(vaddwev_h_b, gen_vvv, gen_helper_vaddwev_h_b)
+TRANS(vaddwev_w_h, gen_vvv, gen_helper_vaddwev_w_h)
+TRANS(vaddwev_d_w, gen_vvv, gen_helper_vaddwev_d_w)
+TRANS(vaddwev_q_d, gen_vvv, gen_helper_vaddwe
在 2022/11/8 下午6:41, Richard Henderson 写道:
On 11/5/22 14:28, Song Gao wrote:
From: Xiaojuan Yang
Load FDT table into dram memory space, and the addr is 2 MiB.
Since lowmem region starts from 0, FDT base address is located
at 2 MiB to avoid NULL pointer access.
Signed-off-by: Xiaojuan Yang
A
在 2022/9/23 上午11:29, Xiaojuan Yang 写道:
+#define VIRT_PCI_IO_OFFSET 0x4000
+static MemMapEntry virt_memmap[] = {
+[VIRT_LOWDDR] = {0x0,0x1000 },
+[VIRT_PCH] = { 0x1000,0x1000 },
+[VIRT_PM] = { 0x1008, 0x100 },
+
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