Hi Marc,
在 2022/11/10 18:28, Marc Zyngier 写道:
On Wed, 09 Nov 2022 06:21:18 +,
"chenxiang (M)" wrote:
Hi Marc,
在 2022/11/8 20:47, Marc Zyngier 写道:
On Tue, 08 Nov 2022 08:08:57 +,
chenxiang wrote:
From: Xiang Chen
Currently the numbers of MSI vectors come fro
在 2022/11/23 20:08, Marc Zyngier 写道:
On Wed, 23 Nov 2022 01:42:36 +,
chenxiang wrote:
From: Xiang Chen
Currently the number of MSI vectors comes from register PCI_MSI_FLAGS
which should be power-of-2 in qemu, in some scenaries it is not the same as
the number that driver requires in gue
Hi,
We boot the VM using following commands (with nvdimm on) (qemu version
6.1.50, kernel 6.0-r4):
qemu-system-aarch64 -machine
virt,kernel_irqchip=on,gic-version=3,nvdimm=on -kernel
/home/kernel/Image -initrd /home/mini-rootfs/rootfs.cpio.gz -bios
/root/QEMU_EFI.FD -cpu host -enable-kvm
Hi Marc,
在 2022/11/30 15:53, Marc Zyngier 写道:
On Wed, 30 Nov 2022 02:52:35 +,
"chenxiang (M)" wrote:
Hi,
We boot the VM using following commands (with nvdimm on) (qemu
version 6.1.50, kernel 6.0-r4):
How relevant is the presence of the nvdimm? Do you observe the failure
wi
Hi Ard,
在 2022/11/30 16:18, Ard Biesheuvel 写道:
On Wed, 30 Nov 2022 at 08:53, Marc Zyngier wrote:
On Wed, 30 Nov 2022 02:52:35 +,
"chenxiang (M)" wrote:
Hi,
We boot the VM using following commands (with nvdimm on) (qemu
version 6.1.50, kernel 6.0-r4):
How relevant is the p
在 2022/12/1 19:07, Ard Biesheuvel 写道:
On Thu, 1 Dec 2022 at 09:07, Ard Biesheuvel wrote:
On Thu, 1 Dec 2022 at 08:15, chenxiang (M) wrote:
Hi Ard,
在 2022/11/30 16:18, Ard Biesheuvel 写道:
On Wed, 30 Nov 2022 at 08:53, Marc Zyngier wrote:
On Wed, 30 Nov 2022 02:52:35 +,
"chen
Hi Ard,
在 2022/12/1 19:07, Ard Biesheuvel 写道:
On Thu, 1 Dec 2022 at 09:07, Ard Biesheuvel wrote:
On Thu, 1 Dec 2022 at 08:15, chenxiang (M) wrote:
Hi Ard,
在 2022/11/30 16:18, Ard Biesheuvel 写道:
On Wed, 30 Nov 2022 at 08:53, Marc Zyngier wrote:
On Wed, 30 Nov 2022 02:52:35 +
Hi Andrew,
在 2022/1/25 18:26, Andrew Jones 写道:
On Tue, Jan 25, 2022 at 05:15:34PM +0800, chenxiang via wrote:
From: Xiang Chen
Since the patchset ("Build ACPI Heterogeneous Memory Attribute Table (HMAT)"),
HMAT is supported, but only x86 is enabled. Enable HMAT on arm virt machine.
Hi Xiang
在 2022/1/25 20:46, Andrew Jones 写道:
On Tue, Jan 25, 2022 at 07:46:43PM +0800, chenxiang (M) wrote:
Hi Andrew,
在 2022/1/25 18:26, Andrew Jones 写道:
On Tue, Jan 25, 2022 at 05:15:34PM +0800, chenxiang via wrote:
From: Xiang Chen
Since the patchset ("Build ACPI Heterogeneous M
在 2022/1/6 19:00, Eric Auger 写道:
Hi CHenxiangn
On 12/29/21 8:13 AM, chenxiang (M) via wrote:
Hi Eric,
在 2021/10/5 16:53, Eric Auger 写道:
Add a 'preserve_config' field in struct GPEXConfig and
if set generate the DSM #5 for preserving PCI boot configurations.
The DSM presence is
Hi Marc,
在 2022/11/8 20:47, Marc Zyngier 写道:
On Tue, 08 Nov 2022 08:08:57 +,
chenxiang wrote:
From: Xiang Chen
Currently the numbers of MSI vectors come from register PCI_MSI_FLAGS
which should be power-of-2, but in some scenaries it is not the same as
the number that driver requires in
Hi all,
I encounter a issue with kernel 5.19-rc1 on a ARM64 board: it takes
about 150s between beginning to run qemu command and beginng to boot
Linux kernel ("EFI stub: Booting Linux Kernel...").
But in kernel 5.18-rc4, it only takes about 5s. I git bisect the kernel
code and it finds c244
在 2022/6/13 21:22, Paul E. McKenney 写道:
On Mon, Jun 13, 2022 at 08:26:34PM +0800, chenxiang (M) wrote:
Hi all,
I encounter a issue with kernel 5.19-rc1 on a ARM64 board: it takes about
150s between beginning to run qemu command and beginng to boot Linux kernel
("EFI stub: Booting
Hi,
I encounter a issue related to GICv4 enable on ARM64 platform (kernel
5.19-rc4, qemu 6.2.0):
We have a accelaration module whose VF has 3 MSI interrupts, and we
passthrough it to virtual machine with following steps:
echo :79:00.1 > /sys/bus/pci/drivers/hisi_hpre/unbind
echo vfio-pci >
Hi Marc,
Thank you for your reply.
在 2022/7/12 23:25, Marc Zyngier 写道:
Hi Xiang,
On Tue, 12 Jul 2022 13:55:16 +0100,
"chenxiang (M)" wrote:
Hi,
I encounter a issue related to GICv4 enable on ARM64 platform (kernel
5.19-rc4, qemu 6.2.0):
We have a accelaration module whose VF
Hi Damien,
在 2022/4/6 23:22, Damien Hedde 写道:
On 4/6/22 10:14, chenxiang via wrote:
From: Xiang Chen
Right now the trace of vfio_region_sparse_mmap_entry is as follows:
vfio_region_sparse_mmap_entry sparse entry 0 [0x1000 - 0x9000]
Actually the range it wants to show is [0x1000 - 0x8fff]，s
Hi Eric,
在 2022/4/15 0:02, Eric Auger 写道:
Hi Chenxiang,
On 4/7/22 9:57 AM, chenxiang via wrote:
From: Xiang Chen
In function memory_region_iommu_replay(), it decides to notify() or not
according to the perm of returned IOMMUTLBEntry. But for smmuv3, the
returned perm is always IOMMU_NONE ev
Hi Eric,
在 2021/10/5 16:53, Eric Auger 写道:
Add a 'preserve_config' field in struct GPEXConfig and
if set generate the DSM #5 for preserving PCI boot configurations.
The DSM presence is needed to expose RMRs.
At the moment the DSM generation is not yet enabled.
Signed-off-by: Eric Auger
---
Hi Eric,
在 2021/8/5 0:26, Eric Auger 写道:
Hi Chenxiang,
On 8/4/21 10:49 AM, chenxiang wrote:
From: Xiang Chen
It splits invalidations into ^2 range invalidations in the patch
6d9cd115b(" hw/arm/smmuv3: Enforce invalidation on a power of two range").
So for some scenarios such as the size of
Hi Eric,
在 2021/8/5 16:10, Eric Auger 写道:
Hi Chenxiang,
On 8/5/21 9:48 AM, chenxiang (M) wrote:
Hi Eric,
在 2021/8/5 0:26, Eric Auger 写道:
Hi Chenxiang,
On 8/4/21 10:49 AM, chenxiang wrote:
From: Xiang Chen
It splits invalidations into ^2 range invalidations in the patch
6d9cd115b(&quo
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