Re: [Qemu-devel] [sw-dev] The problem of write misa on QEMU and BBL

2018-04-20 8:11 GMT+08:00 Andrew Waterman : > > > On Thu, Apr 19, 2018 at 5:05 PM, Michael Clark wrote: >> >> >> >> On Thu, Apr 19, 2018 at 9:28 PM, Zong Li wrote: >>> >>> 2018-04-19 12:43 GMT+08:00 Michael Clark : >>> >

Re: [Qemu-devel] [sw-dev] The problem of write misa on QEMU and BBL

2018-04-20 8:05 GMT+08:00 Michael Clark : > > > On Thu, Apr 19, 2018 at 9:28 PM, Zong Li wrote: >> >> 2018-04-19 12:43 GMT+08:00 Michael Clark : >> > Hi Zong, >> > >> >> On 19/04/2018, at 2:40 PM, Zong Li wrote: >> >> >&g

Re: [Qemu-devel] [sw-dev] The problem of write misa on QEMU and BBL

2018-04-19 12:43 GMT+08:00 Michael Clark : > Hi Zong, > >> On 19/04/2018, at 2:40 PM, Zong Li wrote: >> >> Hi all, >> >> For BBL part, in fp_init at machine/minit.c, >> it will clear the D and F bits of misa register, and assertion that >> the bits

[PATCH 2/2] target/riscv/pmp.c: Fix the index offset on RV64

2, but we expect that it should be started from 8. Separate the implementation for RV32 and RV64 respectively. Signed-off-by: Zong Li --- target/riscv/pmp.c | 9 + 1 file changed, 9 insertions(+) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 2a2b9f5363..adcdd411e6 100644 --

[PATCH 0/2] Fix some PMP implementation

This patch set contains the fixes for wrong index of pmpcfg CSR on rv64, and the pmp range in CSR function table. Zong Li (2): target/riscv: Fix the range of pmpcfg of CSR funcion table target/riscv/pmp.c: Fix the index offset on RV64 target/riscv/csr.c | 2 +- target/riscv/pmp.c | 9

[PATCH 1/2] target/riscv: Fix the range of pmpcfg of CSR funcion table

The range of Physical Memory Protection should be from CSR_PMPCFG0 to CSR_PMPCFG3, not to CSR_PMPADDR9. Signed-off-by: Zong Li --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ac01c835e1..6a96a01b1c 100644

Re: [PATCH 2/2] target/riscv/pmp.c: Fix the index offset on RV64

On Tue, Jul 21, 2020 at 10:41 AM Bin Meng wrote: > > Hi Zong, > > On Mon, Jul 20, 2020 at 5:46 PM Zong Li wrote: > > > > On RV64, the reg_index is 2 (pmpcfg2 CSR) after the seventh pmp > > entry, it is not 1 (pmpcfg1 CSR) like RV32. In the original > > imp

[PATCH v2 0/2] Fix some PMP implementation

This patch set contains the fixes for wrong index of pmpcfg CSR on rv64, and the pmp range in CSR function table. Changed in v2: - Move out the shifting operation from loop. Suggested by Bin Meng. Zong Li (2): target/riscv: Fix the range of pmpcfg of CSR funcion table target/riscv/pmp.c

[PATCH v2 2/2] target/riscv/pmp.c: Fix the index offset on RV64

2, but we expect that it should be started from 8. Separate the implementation for RV32 and RV64 respectively. Changed in v2: - Move out the shifting operation from loop. Suggested by Bin Meng Signed-off-by: Zong Li --- target/riscv/pmp.c | 19 --- 1 file changed, 16 insert

[PATCH v2 1/2] target/riscv: Fix the range of pmpcfg of CSR funcion table

The range of Physical Memory Protection should be from CSR_PMPCFG0 to CSR_PMPCFG3, not to CSR_PMPADDR9. Signed-off-by: Zong Li Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b

[PATCH v3 0/3] Fix some PMP implementation

checking Changed in v2: - Move out the shifting operation from loop. Suggested by Bin Meng. Zong Li (3): target/riscv: Fix the range of pmpcfg of CSR funcion table target/riscv/pmp.c: Fix the index offset on RV64 target/riscv: Fix the translation of physical address target/riscv/cpu_helper.c

[PATCH v3 1/3] target/riscv: Fix the range of pmpcfg of CSR funcion table

The range of Physical Memory Protection should be from CSR_PMPCFG0 to CSR_PMPCFG3, not to CSR_PMPADDR9. Signed-off-by: Zong Li Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b

[PATCH v3 2/3] target/riscv/pmp.c: Fix the index offset on RV64

2, but we expect that it should be started from 8. Separate the implementation for RV32 and RV64 respectively. Signed-off-by: Zong Li Changed in v3: - Refine the implementation. Suggested by Bin Meng. Changed in v2: - Move out the shifting operation from loop. Suggested by Bin Meng. --- target/r

[PATCH v3 3/3] target/riscv: Fix the translation of physical address

which in the same page. Signed-off-by: Zong Li --- target/riscv/cpu_helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 75d2ae3434..08b069f0c9 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv

Re: [PATCH v3 2/3] target/riscv/pmp.c: Fix the index offset on RV64

On Wed, Jul 22, 2020 at 12:58 PM Bin Meng wrote: > > Hi Zong, > > On Tue, Jul 21, 2020 at 8:41 PM Zong Li wrote: > > > > On RV64, the reg_index is 2 (pmpcfg2 CSR) after the seventh pmp > > entry, it is not 1 (pmpcfg1 CSR) like RV32. In the original > > imp

Re: [PATCH v3 3/3] target/riscv: Fix the translation of physical address

On Wed, Jul 22, 2020 at 5:08 PM Alexander Richardson wrote: > > On Tue, 21 Jul 2020 at 13:43, Zong Li wrote: > > > > The real physical address should add the 12 bits page offset. It also > > causes the PMP wrong checking due to the minimum granularity of PMP is > >

[PATCH v4 0/4] Fix some PMP implementations

. Suggested by Bin Meng. - Add fix for PMP checking was ignored. Changed in v3: - Refine the implementation. Suggested by Bin Meng. - Add fix for wrong pphysical address translation. Changed in v2: - Move out the shifting operation from loop. Suggested by Bin Meng. Zong Li (4): target/riscv

[PATCH v4 2/4] target/riscv/pmp.c: Fix the index offset on RV64

2, but we expect that it should be started from 8. Separate the implementation for RV32 and RV64 respectively. Signed-off-by: Zong Li --- target/riscv/pmp.c | 8 1 file changed, 8 insertions(+) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 2a2b9f5363..e0161d6aab 100644 --- a/ta

[PATCH v4 4/4] target/riscv: Change the TLB page size depends on PMP entries.

page size. Signed-off-by: Zong Li --- target/riscv/cpu_helper.c | 10 ++-- target/riscv/pmp.c| 52 +++ target/riscv/pmp.h| 2 ++ 3 files changed, 62 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_hel

[PATCH v4 3/4] target/riscv: Fix the translation of physical address

which in the same page. Signed-off-by: Zong Li --- target/riscv/cpu_helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 75d2ae3434..08b069f0c9 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv

[PATCH v4 1/4] target/riscv: Fix the range of pmpcfg of CSR funcion table

The range of Physical Memory Protection should be from CSR_PMPCFG0 to CSR_PMPCFG3, not to CSR_PMPADDR9. Signed-off-by: Zong Li Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b

[PATCH v5 0/4] Fix some PMP implementations

operation from loop. Suggested by Bin Meng. Zong Li (4): target/riscv: Fix the range of pmpcfg of CSR funcion table target/riscv/pmp.c: Fix the index offset on RV64 target/riscv: Fix the translation of physical address target/riscv: Change the TLB page size depends on PMP entries. target

[PATCH v5 2/4] target/riscv/pmp.c: Fix the index offset on RV64

2, but we expect that it should be started from 8. Separate the implementation for RV32 and RV64 respectively. Signed-off-by: Zong Li --- target/riscv/pmp.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 2a2b9f5363..

[PATCH v5 1/4] target/riscv: Fix the range of pmpcfg of CSR funcion table

The range of Physical Memory Protection should be from CSR_PMPCFG0 to CSR_PMPCFG3, not to CSR_PMPADDR9. Signed-off-by: Zong Li Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b

[PATCH v5 3/4] target/riscv: Fix the translation of physical address

which in the same page. Signed-off-by: Zong Li --- target/riscv/cpu_helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 75d2ae3434..08b069f0c9 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv

Re: [PATCH v4 2/4] target/riscv/pmp.c: Fix the index offset on RV64

On Fri, Jul 24, 2020 at 5:22 PM Bin Meng wrote: > > Hi Zong, > > On Fri, Jul 24, 2020 at 5:08 PM Zong Li wrote: > > > > On RV64, the reg_index is 2 (pmpcfg2 CSR) after the seventh pmp > > entry, it is not 1 (pmpcfg1 CSR) like RV32. In the original > > imp

[PATCH v5 4/4] target/riscv: Change the TLB page size depends on PMP entries.

page size. Signed-off-by: Zong Li --- target/riscv/cpu_helper.c | 10 ++-- target/riscv/pmp.c| 52 +++ target/riscv/pmp.h| 2 ++ 3 files changed, 62 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_hel

Re: [PATCH v5 3/4] target/riscv: Fix the translation of physical address

On Tue, Jul 28, 2020 at 6:49 AM Alistair Francis wrote: > > On Sat, Jul 25, 2020 at 8:05 AM Zong Li wrote: > > > > The real physical address should add the 12 bits page offset. It also > > causes the PMP wrong checking due to the minimum granularity of PMP is > >

[PATCH v6 1/4] target/riscv: Fix the range of pmpcfg of CSR funcion table

The range of Physical Memory Protection should be from CSR_PMPCFG0 to CSR_PMPCFG3, not to CSR_PMPADDR9. Signed-off-by: Zong Li Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b

[PATCH v6 3/4] target/riscv: Fix the translation of physical address

which in the same page. Signed-off-by: Zong Li --- target/riscv/cpu_helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 75d2ae3434..2f337e418c 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv

[PATCH v6 0/4] Fix some PMP implementations

implementation. Suggested by Bin Meng. - Add fix for wrong physical address translation. Changed in v2: - Move out the shifting operation from loop. Suggested by Bin Meng. Zong Li (4): target/riscv: Fix the range of pmpcfg of CSR funcion table target/riscv/pmp.c: Fix the index offset on RV64 target

[PATCH v6 2/4] target/riscv/pmp.c: Fix the index offset on RV64

2, but we expect that it should be started from 8. Separate the implementation for RV32 and RV64 respectively. Signed-off-by: Zong Li Reviewed-by: Bin Meng Reviewed-by: Alistair Francis --- target/riscv/pmp.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/target/ris

[PATCH v6 4/4] target/riscv: Change the TLB page size depends on PMP entries.

page size. Signed-off-by: Zong Li --- target/riscv/cpu_helper.c | 10 ++-- target/riscv/pmp.c| 52 +++ target/riscv/pmp.h| 2 ++ 3 files changed, 62 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_hel

Re: [PATCH v6 4/4] target/riscv: Change the TLB page size depends on PMP entries.

On Tue, Jul 28, 2020 at 4:26 PM Zong Li wrote: > > The minimum granularity of PMP is 4 bytes, it is small than 4KB page > size, therefore, the pmp checking would be ignored if its range doesn't > start from the alignment of one page. This patch detects the pmp entries > and

Re: [PATCH v6 4/4] target/riscv: Change the TLB page size depends on PMP entries.

On Wed, Aug 12, 2020 at 11:21 PM Alistair Francis wrote: > > On Tue, Jul 28, 2020 at 1:29 AM Zong Li wrote: > > > > The minimum granularity of PMP is 4 bytes, it is small than 4KB page > > size, therefore, the pmp checking would be ignored if its range doesn't > &