[PATCH v4 08/17] intel_iommu: Set accessed and dirty bits during first stage translation

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 3 +++ hw/i386/intel_iommu.c | 25 - 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/hw/i386

[PATCH v4 10/17] intel_iommu: Process PASID-based iotlb invalidation

PASID-based iotlb (piotlb) is used during walking Intel VT-d stage-1 page table. This emulates the stage-1 page table iotlb invalidation requested by a PASID-based IOTLB Invalidate Descriptor (P_IOTLB). Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Clément Mathieu--Drif

[PATCH v4 12/17] intel_iommu: Add support for PASID-based device IOTLB invalidation

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 11 hw/i386/intel_iommu.c | 50 ++ 2 files changed, 61 insertions(+) diff --git a/hw/i386

[PATCH v4 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation

what in iotlb cache are only first-stage and second-stage mappings. Add a tag pgtt in VTDIOTLBEntry to mark PGTT type of the mapping and invalidate entries based on PGTT type. Signed-off-by: Zhenzhong Duan Reviewed-by: Clément Mathieu--Drif Acked-by: Jason Wang --- include/hw/i386/intel_iommu.h

[PATCH] intel_iommu: Remove Transient Mapping (TM) field from second-level page-tables

VT-d spec removed Transient Mapping (TM) field from second-level page-tables and treat the field as Reserved(0) since revision 3.2. Update code to match spec. This doesn't impact function of vIOMMU as there was no logic to emulate Transient Mapping. Suggested-by: Yi Liu Signed-off-by: Zhen

[PATCH v4 15/17] intel_iommu: Introduce a property x-fls for scalable modern mode

o known as scalable modern mode is supported. When enabled in legacy mode, throw out error. With scalable modern mode exposed to user, also accurate the pasid entry check in vtd_pe_type_check(). Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_

[PATCH v4 07/17] intel_iommu: Check if the input address is canonical

From: Clément Mathieu--Drif First stage translation must fail if the address to translate is not canonical. Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan Acked-by: Jason Wang --- hw/i386/intel_iommu_internal.h | 2 ++ hw/i386/intel_iommu.c | 23

[PATCH v4 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation

, remove old IOTLB related definitions which were unused. Signed-off-by: Zhenzhong Duan Reviewed-by: Clément Mathieu--Drif Acked-by: Jason Wang --- hw/i386/intel_iommu_internal.h | 14 -- hw/i386/intel_iommu.c | 88 +- 2 files changed, 96 insertions(+), 6

[RESEND PATCH v4 17/17] tests/qtest: Add intel-iommu test

Add the framework to test the intel-iommu device. Currently only tested cap/ecap bits correctness in scalable modern mode. Also tested cap/ecap bits consistency before and after system reset. Signed-off-by: Zhenzhong Duan Acked-by: Thomas Huth Reviewed-by: Clément Mathieu--Drif Acked-by: Jason

[PATCH v2] intel_iommu: Introduce property "x-stale-tm" to control Transient Mapping (TM) field

ansient Mapping. Suggested-by: Yi Liu Suggested-by: Jason Wang Signed-off-by: Zhenzhong Duan --- v2: Introcude "x-stale-tm" to handle migration compatibility (Jason) hw/i386/intel_iommu_internal.h | 12 ++-- include/hw/i386/intel_iommu.h | 3 +++ hw/i386/intel_iommu.c

[PATCH v4] intel_iommu: Introduce property "stale-tm" to control Transient Mapping (TM) field

ansient Mapping. Suggested-by: Yi Liu Suggested-by: Jason Wang Signed-off-by: Zhenzhong Duan --- v4: s/x-stale-tm/stale-tm (Jason) v3: still need to check x86_iommu->dt_supported v2: introcude "x-stale-tm" to handle migration compatibility (Jason) hw/i386/intel_iommu_internal.h | 12 +

[PATCH 2/3] intel_iommu: Add missed sanity check for 256-bit invalidation queue

ue as error_report_once() here is mainly used to help debug guest error, but it only dumps once in qemu life cycle and doesn't help much, we need error_report() instead. Fixes: c0c1d351849b ("intel_iommu: add 256 bits qi_desc support") Suggested-by: Yi Liu Signed-off-by: Zhenzhon

[PATCH 0/3] intel_iommu: Add missed sanity check for invalidae descriptor

Hi, This adds missed sanity check when IQ size is 256-bit per Yi's suggestion, see patch for details. I don't add check for VTD_INV_DESC_PC and VTD_INV_DESC_PIOTLB, will do it in "intel_iommu: Enable stage-1 translation for emulated device" series. Thanks Zhenzhon

[PATCH 3/3] intel_iommu: Add missed reserved bit check for IEC descriptor

ned-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 3 +++ hw/i386/intel_iommu.c | 8 2 files changed, 11 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 75ccd501b0..4323fc5d6d 100644 --- a/hw/i386/intel_iommu_internal.h +++

[PATCH 1/3] intel_iommu: Send IQE event when setting reserved bit in IQT_TAIL

; Current code missed to send IQE event to guest, fix it. Fixes: c0c1d351849b ("intel_iommu: add 256 bits qi_desc support") Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386

[PATCH v5] intel_iommu: Introduce property "stale-tm" to control Transient Mapping (TM) field

ansient Mapping. Suggested-by: Yi Liu Suggested-by: Jason Wang Signed-off-by: Zhenzhong Duan Acked-by: Jason Wang Reviewed-by: Yi Liu --- v5: fix typo, s/hw_compat_9_1/pc_compat_9_1 (Liuyi) v4: s/x-stale-tm/stale-tm (Jason) v3: still need to check x86_iommu->dt_supported v2: introcude "x-stale-

[PATCH v5 01/20] intel_iommu: Use the latest fault reasons defined by spec

are supported. Instead cap/ecap bits should be checked. Signed-off-by: Yu Zhang Signed-off-by: Zhenzhong Duan Reviewed-by: Clément Mathieu--Drif Reviewed-by: Yi Liu Acked-by: Jason Wang --- hw/i386/intel_iommu_internal.h | 9 - hw/i386/intel_iommu.c | 25

[PATCH v5 03/20] intel_iommu: Add a placeholder variable for scalable modern mode

igned-off-by: Yi Liu Signed-off-by: Zhenzhong Duan Acked-by: Jason Wang Reviewed-by: Clément Mathieu--Drif Reviewed-by: Yi Liu --- include/hw/i386/intel_iommu.h | 1 + hw/i386/intel_iommu.c | 23 ++- 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/in

[PATCH v5 11/20] intel_iommu: Process PASID-based iotlb invalidation

PASID-based iotlb (piotlb) is used during walking Intel VT-d stage-1 page table. This emulates the stage-1 page table iotlb invalidation requested by a PASID-based IOTLB Invalidate Descriptor (P_IOTLB). Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Clément Mathieu--Drif

[PATCH v5 00/20] intel_iommu: Enable stage-1 translation for emulated device

: Set accessed and dirty bits during stage-1 translation intel_iommu: Add an internal API to find an address space with PASID intel_iommu: Add support for PASID-based device IOTLB invalidation Yi Liu (2): intel_iommu: Rename slpte to pte intel_iommu: Implement stage-1 translation Yu Zhang (1

[PATCH v5 14/20] intel_iommu: piotlb invalidation should notify unmap

invalidation. For device that does not implement ATS capability or disable it but still caches the translation result, it is better to implement ATS cap or enable it if there is need to cache the translation result. Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan Acked-by: Jason Wang

[PATCH v5 12/20] intel_iommu: Add an internal API to find an address space with PASID

From: Clément Mathieu--Drif This will be used to implement the device IOTLB invalidation Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan Acked-by: Jason Wang Reviewed-by: Yi Liu --- hw/i386/intel_iommu.c | 38 +++--- 1 file changed, 23

[PATCH v5 15/20] tests/acpi: q35: allow DMAR acpi table changes

Signed-off-by: Zhenzhong Duan --- tests/qtest/bios-tables-test-allowed-diff.h | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8b..46f80be9ca 100644 --- a/tests/qtest/bios-tables-test

[PATCH v5 02/20] intel_iommu: Make pasid entry type check accurate

Signed-off-by: Zhenzhong Duan Reviewed-by: Clément Mathieu--Drif Reviewed-by: Yi Liu Acked-by: Jason Wang --- hw/i386/intel_iommu.c | 12 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 67dc99cfdf..10b8425a6c 10064

[PATCH v5 05/20] intel_iommu: Rename slpte to pte

: Clément Mathieu--Drif Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan Acked-by: Jason Wang Reviewed-by: Yi Liu --- hw/i386/intel_iommu_internal.h | 24 +++--- include/hw/i386/intel_iommu.h | 2 +- hw/i386/intel_iommu.c | 129 + 3 files changed

[PATCH v5 18/20] intel_iommu: Introduce a property x-flts for scalable modern mode

also known as scalable modern mode is supported. When enabled in legacy mode, throw out error. With scalable modern mode exposed to user, also accurate the pasid entry check in vtd_pe_type_check(). Suggested-by: Jason Wang Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Dua

[PATCH v5 07/20] intel_iommu: Check if the input address is canonical

From: Clément Mathieu--Drif First stage translation must fail if the address to translate is not canonical. Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan Acked-by: Jason Wang Reviewed-by: Yi Liu --- hw/i386/intel_iommu_internal.h | 1 + hw/i386/intel_iommu.c

[PATCH v5 08/20] intel_iommu: Check stage-1 translation result with interrupt range

slpte() to vtd_do_iommu_translate() so stage-1 page table could also be checked. By this chance, update the comment with correct section number. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 48 ++- 1 file changed, 25 insertions(+), 23

[PATCH v5 13/20] intel_iommu: Add support for PASID-based device IOTLB invalidation

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 11 hw/i386/intel_iommu.c | 50 ++ 2 files changed, 61 insertions(+) diff --git a/hw/i386

[PATCH v5 10/20] intel_iommu: Flush stage-1 cache in iotlb invalidation

what in iotlb cache are only first-stage and second-stage mappings. Add a tag pgtt in VTDIOTLBEntry to mark PGTT type of the mapping and invalidate entries based on PGTT type. Signed-off-by: Zhenzhong Duan Reviewed-by: Clément Mathieu--Drif Acked-by: Jason Wang Reviewed-by: Yi Liu --- inclu

[PATCH v5 06/20] intel_iommu: Implement stage-1 translation

From: Yi Liu This adds stage-1 page table walking to support stage-1 only translation in scalable modern mode. Signed-off-by: Yi Liu Co-developed-by: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan Acked-by: Jason Wang --- hw

[PATCH v5 04/20] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation

n to flush either stage-1 or stage-2 entries. By this chance, remove old IOTLB related definitions which were unused. Signed-off-by: Zhenzhong Duan Reviewed-by: Clément Mathieu--Drif Acked-by: Jason Wang --- hw/i386/intel_iommu_internal.h | 14 -- hw/i386/intel_iommu.c

[PATCH v5 09/20] intel_iommu: Set accessed and dirty bits during stage-1 translation

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan Reviewed-by: Yi Liu Acked-by: Jason Wang --- hw/i386/intel_iommu_internal.h | 3 +++ hw/i386/intel_iommu.c | 25 - 2 files changed, 27 insertions(+), 1 deletion

[PATCH v5 17/20] tests/acpi: q35: Update host address width in DMAR

Reserved : [044h 0068 1] Enumeration ID : 00 [045h 0069 1] PCI Bus Number : FF Signed-off-by: Zhenzhong Duan --- tests/qtest/bios-tables-test-allowed-diff.h | 1 - tests/data/acpi/x86/q35/DMAR.dmar | Bin 120 -> 120 bytes 2 files changed, 1

[PATCH v5 20/20] tests/qtest: Add intel-iommu test

Add the framework to test the intel-iommu device. Currently only tested cap/ecap bits correctness in scalable modern mode. Also tested cap/ecap bits consistency before and after system reset. Signed-off-by: Zhenzhong Duan Acked-by: Thomas Huth Reviewed-by: Clément Mathieu--Drif Acked-by: Jason

[PATCH v5 19/20] intel_iommu: Introduce a property to control FS1GP cap bit setting

n scalable modern mode. Signed-off-by: Zhenzhong Duan Reviewed-by: Clément Mathieu--Drif Reviewed-by: Yi Liu Acked-by: Jason Wang --- include/hw/i386/intel_iommu.h | 1 + hw/i386/intel_iommu.c | 5 - 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/include/hw/i386/intel

[PATCH v5 16/20] intel_iommu: Set default aw_bits to 48 starting from QEMU 9.2

is the default choice for modern OS when both 48 and 39 are supported. So it makes sense to set default to 48 for these two modes too starting from QEMU 9.2. Use pc_compat_9_1 to handle the compatibility for machines before 9.2. Suggested-by: Jason Wang Signed-off-by: Zhenzhong Duan Reviewed-by

[PATCH v6 04/20] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation

n to flush either stage-1 or stage-2 entries. By this chance, remove old IOTLB related definitions which were unused. Signed-off-by: Zhenzhong Duan Reviewed-by: Clément Mathieu--Drif Acked-by: Jason Wang --- hw/i386/intel_iommu_internal.h | 14 -- hw/i386/intel_iommu.c

[PATCH v6 01/20] intel_iommu: Use the latest fault reasons defined by spec

are supported. Instead cap/ecap bits should be checked. Signed-off-by: Yu Zhang Signed-off-by: Zhenzhong Duan Reviewed-by: Clément Mathieu--Drif Reviewed-by: Yi Liu Acked-by: Jason Wang --- hw/i386/intel_iommu_internal.h | 9 - hw/i386/intel_iommu.c | 25

[PATCH v6 11/20] intel_iommu: Process PASID-based iotlb invalidation

PASID-based iotlb (piotlb) is used during walking Intel VT-d stage-1 page table. This emulates the stage-1 page table iotlb invalidation requested by a PASID-based IOTLB Invalidate Descriptor (P_IOTLB). Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Clément Mathieu--Drif

[PATCH v6 03/20] intel_iommu: Add a placeholder variable for scalable mode stage-1 translation

sting is supported. Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan Acked-by: Jason Wang Reviewed-by: Clément Mathieu--Drif Reviewed-by: Yi Liu --- include/hw/i386/intel_iommu.h | 1 + hw/i386/intel_iommu.c | 23 ++- 2 files changed, 19 insertions(+), 5 dele

[PATCH v6 05/20] intel_iommu: Rename slpte to pte

: Clément Mathieu--Drif Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan Acked-by: Jason Wang Reviewed-by: Yi Liu --- hw/i386/intel_iommu_internal.h | 24 +++--- include/hw/i386/intel_iommu.h | 2 +- hw/i386/intel_iommu.c | 129 + 3 files changed

[PATCH v6 13/20] intel_iommu: Add support for PASID-based device IOTLB invalidation

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan Acked-by: Jason Wang --- hw/i386/intel_iommu_internal.h | 11 hw/i386/intel_iommu.c | 50 ++ 2 files changed, 61 insertions(+) diff --git a/hw

[PATCH v6 02/20] intel_iommu: Make pasid entry type check accurate

Signed-off-by: Zhenzhong Duan Reviewed-by: Clément Mathieu--Drif Reviewed-by: Yi Liu Acked-by: Jason Wang --- hw/i386/intel_iommu.c | 12 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 67dc99cfdf..10b8425a6c 10064

[PATCH v6 16/20] intel_iommu: Set default aw_bits to 48 starting from QEMU 9.2

modes, 48 is the default choice for modern OS when both 48 and 39 are supported. So it makes sense to set default to 48 for these two modes too starting from QEMU 9.2. Use pc_compat_9_1 to handle the compatibility for machines before 9.2. Suggested-by: Jason Wang Signed-off-by: Zhenzhong Duan

[PATCH v6 08/20] intel_iommu: Check stage-1 translation result with interrupt range

slpte() to vtd_do_iommu_translate() so stage-1 page table could also be checked. By this chance, update the comment with correct section number. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Clément Mathieu--Drif Acked-by: Jason Wang --- hw/i386/intel_io

[PATCH v6 00/20] intel_iommu: Enable stage-1 translation for emulated device

intel_iommu: Implement stage-1 translation Yu Zhang (1): intel_iommu: Use the latest fault reasons defined by spec Zhenzhong Duan (13): intel_iommu: Make pasid entry type check accurate intel_iommu: Add a placeholder variable for scalable mode stage-1 translation intel_iommu: Flush

[PATCH v6 14/20] intel_iommu: piotlb invalidation should notify unmap

invalidation. For device that does not implement ATS capability or disable it but still caches the translation result, it is better to implement ATS cap or enable it if there is need to cache the translation result. Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan Acked-by: Jason Wang

[PATCH v6 20/20] tests/qtest: Add intel-iommu test

Add the framework to test the intel-iommu device. Currently only tested cap/ecap bits correctness when x-flts=on in scalable mode. Also tested cap/ecap bits consistency before and after system reset. Signed-off-by: Zhenzhong Duan Acked-by: Thomas Huth Reviewed-by: Clément Mathieu--Drif Acked

[PATCH v6 10/20] intel_iommu: Flush stage-1 cache in iotlb invalidation

what in iotlb cache are only first-stage and second-stage mappings. Add a tag pgtt in VTDIOTLBEntry to mark PGTT type of the mapping and invalidate entries based on PGTT type. Signed-off-by: Zhenzhong Duan Reviewed-by: Clément Mathieu--Drif Acked-by: Jason Wang Reviewed-by: Yi Liu --- inclu

[PATCH v6 15/20] tests/acpi: q35: allow DMAR acpi table changes

Signed-off-by: Zhenzhong Duan Acked-by: Jason Wang --- tests/qtest/bios-tables-test-allowed-diff.h | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8b..46f80be9ca 100644 --- a/tests/qtest

[PATCH v6 09/20] intel_iommu: Set accessed and dirty bits during stage-1 translation

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan Reviewed-by: Yi Liu Acked-by: Jason Wang --- hw/i386/intel_iommu_internal.h | 3 +++ hw/i386/intel_iommu.c | 25 - 2 files changed, 27 insertions(+), 1 deletion

[PATCH v6 18/20] intel_iommu: Introduce a property x-flts for stage-1 translation

supported. When turned on in legacy mode, throw out error. With stage-1 translation support exposed to user, also accurate the pasid entry check in vtd_pe_type_check(). Suggested-by: Jason Wang Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan Reviewed-by: Clément Mat

[PATCH v6 19/20] intel_iommu: Introduce a property to control FS1GP cap bit setting

mode or x-flts=off in scalable modme. Signed-off-by: Zhenzhong Duan Reviewed-by: Clément Mathieu--Drif Reviewed-by: Yi Liu Acked-by: Jason Wang --- include/hw/i386/intel_iommu.h | 1 + hw/i386/intel_iommu.c | 5 - 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/inclu

[PATCH v6 12/20] intel_iommu: Add an internal API to find an address space with PASID

From: Clément Mathieu--Drif This will be used to implement the device IOTLB invalidation Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan Acked-by: Jason Wang Reviewed-by: Yi Liu --- hw/i386/intel_iommu.c | 38 +++--- 1 file changed, 23

[PATCH v6 17/20] tests/acpi: q35: Update host address width in DMAR

Reserved : [044h 0068 1] Enumeration ID : 00 [045h 0069 1] PCI Bus Number : FF Signed-off-by: Zhenzhong Duan Acked-by: Clément Mathieu--Drif --- tests/qtest/bios-tables-test-allowed-diff.h | 1 - tests/data/acpi/x86/q35/DMAR.dmar | Bin 120 -

[PATCH v6 06/20] intel_iommu: Implement stage-1 translation

From: Yi Liu This adds stage-1 page table walking to support stage-1 only translation in scalable mode. Signed-off-by: Yi Liu Co-developed-by: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan Acked-by: Jason Wang --- hw/i386

[PATCH v6 07/20] intel_iommu: Check if the input address is canonical

From: Clément Mathieu--Drif Stage-1 translation must fail if the address to translate is not canonical. Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan Acked-by: Jason Wang Reviewed-by: Yi Liu --- hw/i386/intel_iommu_internal.h | 1 + hw/i386/intel_iommu.c | 23

[PATCH] vfio/iommufd: Fix SIGSEV in iommufd_cdev_attach()

ement the iommufd backend") Signed-off-by: Zhenzhong Duan --- hw/vfio/iommufd.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index 3490a8f1eb..df61edffc0 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -515,8 +515,8

[PATCH 5/5] vfio/iommufd: Drop HostIOMMUDeviceCaps from HostIOMMUDevice

: Zhenzhong Duan --- include/system/host_iommu_device.h | 14 -- hw/vfio/iommufd.c | 15 --- 2 files changed, 29 deletions(-) diff --git a/include/system/host_iommu_device.h b/include/system/host_iommu_device.h index 809cced4ba..6f10bea25f 100644 --- a

[PATCH 3/5] vfio/iommufd: Implement .get_cap() in TYPE_HOST_IOMMU_DEVICE_IOMMUFD_VFIO sub-class

specific capability, e.g., for vtd, checking code will be in hiod_iommufd_get_vtd_cap(). This also fixes an issue that calling vfio_device_get_aw_bits() in TYPE_HOST_IOMMU_DEVICE_IOMMUFD parent class .get_cap(). Signed-off-by: Zhenzhong Duan --- include/system/iommufd.h | 4 backends

[PATCH 1/5] vfio/iommufd: Save host iommu capabilities in VFIODevice.caps

ze() after .attach_device(). Suggested-by: Cédric Le Goater Suggested-by: Eric Auger Suggested-by: Nicolin Chen Signed-off-by: Zhenzhong Duan --- include/hw/vfio/vfio-device.h | 1 + include/system/iommufd.h | 22 ++ hw/vfio/iommufd.c | 10 +- 3 fil

[PATCH 0/5] cleanup interfaces

4/msg01211.html [2] https://lists.gnu.org/archive/html/qemu-devel/2025-04/msg00898.html [3] https://lists.gnu.org/archive/html/qemu-devel/2025-03/msg01552.html Test: net card passthrough and ping test hotplug/unplug Based on vfio-next(b9d42a878b). Thanks Zhenzhong Zhenzhong Duan (5): vfio/iom

[PATCH 2/5] vfio: Move realize() after attach_device()

vfio_device_attach(). Drop vfio_device_hiod_realize() which looks redundant now. Suggested-by: Cédric Le Goater Suggested-by: Donald Dutile Signed-off-by: Zhenzhong Duan --- include/hw/vfio/vfio-device.h | 1 - hw/vfio/container.c | 4 hw/vfio/device.c | 28

[PATCH 4/5] backends/iommufd: Drop hiod_iommufd_get_cap()

Because sub-class TYPE_HOST_IOMMU_DEVICE_IOMMUFD_VFIO has it's own implementation of .get_cap(), hiod_iommufd_get_cap() isn't used any more, drop it. Signed-off-by: Zhenzhong Duan --- backends/iommufd.c | 23 --- 1 file changed, 23 deletions(-) diff --git

[PATCH v2 4/5] vfio: Cleanup host IOMMU device creation

realize() is now moved after attachment, do the same for hiod creation. Introduce a new function vfio_device_hiod_create_and_realize() to do them all in one go. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- include/hw/vfio/vfio-device.h | 3 ++- hw/vfio/container.c

[PATCH v2 0/5] vfio: Move realize after attach_dev

unction to create and realize hiod - remove hiod_typename property Zhenzhong Duan (5): vfio/iommufd: Make a separate call to get IOMMU capabilities vfio/iommufd: Move realize() after attachment vfio/container: Move realize() after attachment vfio: Cleanup host IOMMU device creation vf

[PATCH v2 3/5] vfio/container: Move realize() after attachment

To match the change for IOMMUFD backend, move realize() after attachment for legacy backend too. Suggested-by: Cédric Le Goater Suggested-by: Donald Dutile Signed-off-by: Zhenzhong Duan --- hw/vfio/container.c | 20 1 file changed, 12 insertions(+), 8 deletions(-) diff

[PATCH v2 5/5] vfio: Remove hiod_typename property

Because we handle host IOMMU device creation in each container backend, we know which type name to use, so hiod_typename property is useless now, just remove it. Signed-off-by: Zhenzhong Duan --- include/hw/vfio/vfio-container-base.h | 3 --- hw/vfio/container.c | 2 -- hw

[PATCH v2 2/5] vfio/iommufd: Move realize() after attachment

after attachment succeed. Suggested-by: Cédric Le Goater Suggested-by: Donald Dutile Signed-off-by: Zhenzhong Duan --- hw/vfio/iommufd.c | 17 ++--- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index 2253778b3a..f273dc8712

[PATCH v2 1/5] vfio/iommufd: Make a separate call to get IOMMU capabilities

oater Signed-off-by: Zhenzhong Duan --- hw/vfio/iommufd.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index 48db105422..2253778b3a 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -287,7 +287,8 @@ static

[PATCH] vfio: Register/unregister container for CPR only once for each container

: d9fa4223b30a ("vfio: register container for cpr") Signed-off-by: Zhenzhong Duan --- btw: untested as I have no env with two migration capable devices, appreciate if someone have env to help test, thanks hw/vfio/iommufd.c | 14 ++ 1 file changed, 6 insertions(+), 8 deletion

[PATCH rfcv2 11/20] intel_iommu: Check for compatibility with IOMMUFD backed device when x-flts=on

pport iommufd. Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan --- include/system/host_iommu_device.h | 13 hw/i386/intel_iommu.c | 34 ++ 2 files changed, 47 insertions(+) diff --git a/include/system/host_iommu_device.h b/include/s

[PATCH rfcv2 15/20] intel_iommu: ERRATA_772415 workaround

0) | | (iommufd0) | .---. .---. .. .. Changed to pass VTDHostIOMMUDevice pointer to vtd_check_hdev() so errata could be saved. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 1 + include/hw/i386/intel_iommu.h

[PATCH rfcv2 14/20] intel_iommu: Bind/unbind guest page table to host

ce | | (iommufd0)| | (iommufd0)| | (non-CC) | | | | | | (iommufd0) | .---. .---. .. Co-Authored-by: Yi Liu Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h

[PATCH rfcv2 00/20] intel_iommu: Enable stage-1 translation for passthrough device

u_pasid() helper to translate between vtd_as and iommu pasid, this is important for dropping VTDPASIDAddressSpace Yi Liu (3): intel_iommu: Replay pasid binds after context cache invalidation intel_iommu: Propagate PASID-based iotlb invalidation to host intel_iommu: Refresh pasid bind when

[PATCH rfcv2 16/20] intel_iommu: Replay pasid binds after context cache invalidation

Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 1 + hw/i386/intel_iommu.c | 51 -- hw/i386/trace-events | 1 + 3 files changed, 51 insertions(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386

[PATCH rfcv2 07/20] iommufd: Implement query of HOST_IOMMU_DEVICE_CAP_[NESTING|FS1GP]

Implement query of HOST_IOMMU_DEVICE_CAP_[NESTING|FS1GP] for IOMMUFD backed host IOMMU device. Query on these two capabilities is not supported for legacy backend because there is no plan to support nesting with leacy backend backed host device. Signed-off-by: Zhenzhong Duan --- hw/i386

[PATCH rfcv2 08/20] iommufd: Implement query of HOST_IOMMU_DEVICE_CAP_ERRATA

Implement query of HOST_IOMMU_DEVICE_CAP_ERRATA for IOMMUFD backed host IOMMU device. Query on this capability is not supported for legacy backend because there is no plan to support nesting with leacy backend backed host device. Signed-off-by: Zhenzhong Duan --- include/system

[PATCH rfcv2 18/20] intel_iommu: Refresh pasid bind when either SRTP or TE bit is changed

From: Yi Liu When either 'Set Root Table Pointer' or 'Translation Enable' bit is changed, the pasid bindings on host side become stale and need to be updated. Introduce a helper function vtd_refresh_pasid_bind() for that purpose. Signed-off-by: Yi Liu Signed-off-by: Zhe

[PATCH rfcv2 13/20] intel_iommu: Add PASID cache management infrastructure

*) a present pasid entry to be a present entry *) a non-present pasid entry moved to present vIOMMU emulator could figure out the reason by fetching latest guest pasid entry and compare it with the PASID cache. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan

[PATCH rfcv2 06/20] host_iommu_device: Define two new capabilities HOST_IOMMU_DEVICE_CAP_[NESTING|FS1GP]

Signed-off-by: Zhenzhong Duan --- include/system/host_iommu_device.h | 8 1 file changed, 8 insertions(+) diff --git a/include/system/host_iommu_device.h b/include/system/host_iommu_device.h index df782598f2..18f8b5e5cf 100644 --- a/include/system/host_iommu_device.h +++ b/include

[PATCH rfcv2 10/20] intel_iommu: Optimize context entry cache utilization

it. So introduce a helper function vtd_as_to_context_entry() to fetch from cache before trying with vtd_dev_to_context_entry(). Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 36 +++- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a

[PATCH rfcv2 05/20] vfio/iommufd: Implement [at|de]tach_hwpt handlers

Implement [at|de]tach_hwpt handlers in VFIO subsystem. vIOMMU utilizes them to attach to or detach from hwpt on host side. Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/vfio/iommufd.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/hw/vfio/iommufd.c b

[PATCH rfcv2 19/20] intel_iommu: Bypass replay in stage-1 page table mode

VFIO utilizes replay to setup initial shadow iommu mappings. But when stage-1 page table is configured, it is passed to host to construct nested page table, there is no replay needed. Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 8 1 file changed, 8 insertions(+) diff

[PATCH rfcv2 17/20] intel_iommu: Propagate PASID-based iotlb invalidation to host

U will cache first level page table related mappings during DMA address translation. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 6 ++ hw/i386/intel_iommu.c | 116 - 2 files change

[PATCH rfcv2 02/20] vfio/iommufd: Add properties and handlers to TYPE_HOST_IOMMU_DEVICE_IOMMUFD

]tach_hwpt to wrap the two handlers. This is a prerequisite patch for following ones. Signed-off-by: Zhenzhong Duan --- include/system/iommufd.h | 50 backends/iommufd.c | 22 ++ 2 files changed, 72 insertions(+) diff --git a/include/system

[PATCH rfcv2 04/20] vfio/iommufd: Implement HostIOMMUDeviceClass::realize_late() handler

There are three iommufd related elements iommufd handle, devid and hwpt_id. hwpt_id is ready only after VFIO device attachment. Device id and iommufd handle are ready before attachment, but they are all iommufd related stuff, initialize them together with hwpt_id. Signed-off-by: Zhenzhong Duan

[PATCH rfcv2 20/20] intel_iommu: Enable host device when x-flts=on in scalable mode

Now that all infrastructures of supporting passthrough device running with stage-1 translation are there, enable it now. Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c

[PATCH rfcv2 01/20] backends/iommufd: Add helpers for invalidating user-managed HWPT

Signed-off-by: Nicolin Chen Signed-off-by: Zhenzhong Duan --- include/system/iommufd.h | 3 +++ backends/iommufd.c | 30 ++ backends/trace-events| 1 + 3 files changed, 34 insertions(+) diff --git a/include/system/iommufd.h b/include/system/iommufd.h

[PATCH rfcv2 12/20] intel_iommu: Introduce a new structure VTDHostIOMMUDevice

Introduce a new structure VTDHostIOMMUDevice which replaces HostIOMMUDevice to be stored in hash table. It includes a reference to HostIOMMUDevice and IntelIOMMUState, also includes BDF information which will be used in future patches. Signed-off-by: Zhenzhong Duan --- hw/i386

[PATCH rfcv2 03/20] HostIOMMUDevice: Introduce realize_late callback

nothing needs to be initialized after attachment. Signed-off-by: Zhenzhong Duan --- include/system/host_iommu_device.h | 17 + hw/vfio/common.c | 17 ++--- 2 files changed, 31 insertions(+), 3 deletions(-) diff --git a/include/system

[PATCH rfcv2 09/20] intel_iommu: Rename vtd_ce_get_rid2pasid_entry to vtd_ce_get_pasid_entry

In early days vtd_ce_get_rid2pasid_entry() is used to get pasid entry of rid2pasid, then extend to any pasid. So a new name vtd_ce_get_pasid_entry is better to match its functions. No functional change intended. Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 14 +++--- 1

[PATCH] vfio/iommufd: Add comment emphasizing no movement of hiod->realize() call

The nested IOMMU support needs device and hwpt id which are generated only after attachment. Hiod encapsulates these information in realize() and passes to vIOMMU. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- hw/vfio/iommufd.c | 4 1 file changed, 4 insertions(+) diff

[PATCH v1 3/6] vfio/iommufd: Initialize iommufd specific members in HostIOMMUDeviceIOMMUFD

There are three iommufd specific members in HostIOMMUDeviceIOMMUFD that need to be initialized after attachment, they will all be used by vIOMMU. Signed-off-by: Zhenzhong Duan --- hw/vfio/iommufd.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c

[PATCH v1 4/6] vfio/iommufd: Implement [at|de]tach_hwpt handlers

Implement [at|de]tach_hwpt handlers in VFIO subsystem. vIOMMU utilizes them to attach to or detach from hwpt on host side. Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/vfio/iommufd.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/hw/vfio/iommufd.c b

[PATCH v1 5/6] vfio/iommufd: Save vendor specific device info

supported in linux, so declare those capability related structures with CONFIG_LINUX. Suggested-by: Eric Auger Suggested-by: Nicolin Chen Signed-off-by: Zhenzhong Duan --- include/system/host_iommu_device.h | 11 +++ hw/vfio/iommufd.c | 8 +++- 2 files changed, 14

[PATCH v1 6/6] iommufd: Implement query of host VTD IOMMU's capability

Implement query of HOST_IOMMU_DEVICE_CAP_[NESTING|FS1GP|ERRATA] for IOMMUFD backed host VTD IOMMU device. Query on these capabilities is not supported for legacy backend because there is no plan to support nesting with legacy backend backed host device. Signed-off-by: Zhenzhong Duan --- hw

[PATCH v1 1/6] backends/iommufd: Add a helper to invalidate user-managed HWPT

This helper passes cache invalidation request from guest to invalidate stage-1 page table cache in host hardware. Signed-off-by: Nicolin Chen Signed-off-by: Zhenzhong Duan --- include/system/iommufd.h | 4 backends/iommufd.c | 33 + backends/trace

[PATCH v1 2/6] vfio/iommufd: Add properties and handlers to TYPE_HOST_IOMMU_DEVICE_IOMMUFD

instead of HostIOMMUDeviceIOMMUFD, e.g., in HostIOMMUDeviceIOMMUFDVFIO. Add two wrappers host_iommu_device_iommufd_[at|de]tach_hwpt to wrap the two functions. Signed-off-by: Zhenzhong Duan --- include/system/iommufd.h | 50 backends/iommufd.c | 22

<    3   4   5   6   7   8   9   10   >