I can confirm the same bug. I am not building from source, but rather
using the unofficial Windows binaries linked to by Qemu.
http://wiki.qemu.org/Links
I'm running as Administrator on Win8.1 x86_64
qemu-system-i386.exe -L . -hda \\.\PhysicalDrive3
qemu-system-i386.exe: -hda \\.\PhysicalDrive
I found some newer Windows binaries at http://qemu.weilnetz.de/ and can
confirm I do not see the issue any more.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1223467
Title:
Unable to use USB as hd
es to access the emulated hardware it will hang
for a very long period of time and play no audio through spice. It
doesn't seem to matter what guest (x86_64 or x86) I run (the above is
just one example) and it also doesn't matter what sound hardware I
choose to emulate or which command line
lated hardware it will hang
for a very long period of time and play no audio through spice. It
doesn't seem to matter what guest (x86_64 or x86) I run (the above is
just one example) and it also doesn't matter what sound hardware I
choose to emulate or which command line method I use to
lated hardware it will hang
for a very long period of time and play no audio through spice. It
doesn't seem to matter what guest (x86_64 or x86) I run (the above is
just one example) and it also doesn't matter what sound hardware I
choose to emulate or which command line method I us
l -spice port=5999,addr=0.0.0.0,disable-ticketing
-enable-kvm -device virtio-serial-pci -device
virtserialport,chardev=spicechannel0,name=com.redhat.spice.0 -chardev
spicevmc,id=spicechannel0,name=vdagent
Any time the guest tries to access the emulated hardware it will hang
for a very long
roject.port.0\
/path/to/vm1.img
*
I also noticed that libvirt is able to create socke
/var/lib/libvirt/qemu/vm1.monitor every time. I can't win even I change the unix
socket path to "/var/lib/libvirt/qemu/foo"
Any information will be appreciated!
hread refinements by stacking on additional
filters (at the cost of additional evaluation time).
hth!
will
Marcelo, Hi,
I have been watching for this patch in the upstream but have not seen it yet.
What version of QEMU should it be in?
Thanks,
Will
> -Original Message-
> From: Marcelo Tosatti [mailto:mtosa...@redhat.com]
> Sent: Friday, November 30, 2012 12:40 PM
> To: Aul
>From 9d5201975d2c9da4da8a945fcd9531c9fb2073c0 Mon Sep 17 00:00:00 2001
From: Will Auld
Date: Wed, 12 Sep 2012 18:31:41 -0700
Subject: [PATCH] Enabling IA32_TSC_ADJUST for Qemu KVM guest VMs
CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
Basic design is to emulate the MSR
suitable for VFIO PCI assignment?).
I'm playing with PCI device assignment with kvmtool, so I could do some
basic testing if you like. Can you put the patches on a git tree somewhere
please?
Will
On Mon, Aug 11, 2014 at 03:28:40PM +0100, Eric Auger wrote:
> On 08/11/2014 03:50 PM, Will Deacon wrote:
> > I'm playing with PCI device assignment with kvmtool, so I could do some
> > basic testing if you like. Can you put the patches on a git tree somewhere
> > please?
he virtio family for the
>>>> sake of simplicity (and covering 90% of the options).
>>>>
>>>> This is my basic overview of how I'm planning on implementing the
>>>> initial POC:
>>>>
>>>> 1. First I'll focus on the si
The regs parameter is not used anywhere, so remove it.
Signed-off-by: Will Newton
---
linux-user/elfload.c | 3 +--
linux-user/flatload.c | 3 +--
linux-user/linuxload.c | 4 ++--
linux-user/qemu.h | 6 ++
4 files changed, 6 insertions(+), 10 deletions(-)
diff --git a/linux-user
Add support for the AArch32 floating-point VRINTZ instruction.
Signed-off-by: Will Newton
---
target-arm/translate.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 73e0e8d..153d0e6 100644
--- a/target-arm
Add support for AArch32 ARMv8 FP VRINTA, VRINTN, VRINTP and VRINTM
instructions.
Signed-off-by: Will Newton
---
target-arm/translate.c | 49 +
1 file changed, 49 insertions(+)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index
This helper sets the rounding mode in the standard_fp_status word to
allow NEON instructions to modify the rounding mode whilst using the
standard FPSCR values for everything else.
Signed-off-by: Will Newton
---
target-arm/helper.c | 17 +
target-arm/helper.h | 1 +
2 files
Add support for the AArch32 Advanced SIMD VRINTA, VRINTN, VRINTP
and VRINTM instructions.
Signed-off-by: Will Newton
---
target-arm/translate.c | 29 -
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index
Add support for the AArch32 Advanced SIMD VRINTZ instruction.
Signed-off-by: Will Newton
---
target-arm/translate.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index b6d11db..16242d3 100644
--- a/target
Add support for the AArch32 floating-point VRINTX instruction.
Signed-off-by: Will Newton
---
target-arm/translate.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 153d0e6..5108f6b 100644
--- a/target-arm/translate.c
+++ b
Add support for the AArch32 floating-point VRINTR instruction.
Signed-off-by: Will Newton
---
target-arm/translate.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index f688f6d..73e0e8d 100644
--- a/target-arm/translate.c
+++ b
Add support for the AArch32 Advanced SIMD VRINTX instruction.
Signed-off-by: Will Newton
---
target-arm/translate.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 5108f6b..b6d11db 100644
--- a/target-arm
This function will be needed for AArch32 ARMv8 support, so move it to
helper.c where it can be used by both targets. Also moves the code out
of line, but as it is quite a large function I don't believe this
should be a significant performance impact.
Signed-off-by: Will Newton
---
targe
This series adds support for the floating-point and Advanced SIMD
versions of the VRINT family of instructions.
Will Newton (9):
target-arm: Move arm_rmode_to_sf to a shared location.
target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM
target-arm: Add support for AArch32 FP VRINTR
Signed-off-by: Will Newton
---
include/qemu/crc32c.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/qemu/crc32c.h b/include/qemu/crc32c.h
index 56d1c3b..dafb6a1 100644
--- a/include/qemu/crc32c.h
+++ b/include/qemu/crc32c.h
@@ -25,8 +25,8 @@
*
*/
-#ifndef
Add support for AArch32 CRC32 and CRC32C instructions added in ARMv8.
Signed-off-by: Will Newton
---
target-arm/helper.c| 37 +
target-arm/helper.h| 3 +++
target-arm/translate.c | 48
3 files changed
This series adds support for the AArch32 CRC32 instructions added in
ARMv8. The CRC-32 algorithm is added alongside the existing CRC-32C
implementation which requires a small fix to the crc32c.h header file.
Will Newton (3):
include/qemu/crc32c.h: Rename include guards to match filename
util
Add a table-driven CRC-32 implementation similar in style to the
existing CRC-32C implementation.
Signed-off-by: Will Newton
---
include/qemu/crc32.h | 15
util/Makefile.objs | 1 +
util/crc32.c | 98
3 files changed, 114
Signed-off-by: Will Newton
Reviewed-by: Peter Maydell
---
include/qemu/crc32c.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/qemu/crc32c.h b/include/qemu/crc32c.h
index 56d1c3b..dafb6a1 100644
--- a/include/qemu/crc32c.h
+++ b/include/qemu/crc32c.h
@@ -25,8
This series adds support for the AArch32 CRC32 instructions added in
ARMv8.
Will Newton (2):
include/qemu/crc32c.h: Rename include guards to match filename
target-arm: Add support for AArch32 ARMv8 CRC32 instructions
configure | 2 +-
include/qemu/crc32c.h | 4 ++--
target
Add support for AArch32 CRC32 and CRC32C instructions added in ARMv8.
The CRC32-C implementation used is the built-in qemu implementation
and The CRC-32 implementation is from zlib. This requires adding zlib
to LIBS to ensure it is linked for the linux-user binary.
Signed-off-by: Will Newton
Signed-off-by: Will Newton
Reviewed-by: Peter Maydell
---
include/qemu/crc32c.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Changes in v3:
- None
diff --git a/include/qemu/crc32c.h b/include/qemu/crc32c.h
index 56d1c3b..dafb6a1 100644
--- a/include/qemu/crc32c.h
+++ b/include
This series adds support for the AArch32 CRC32 instructions added in
ARMv8.
Will Newton (2):
include/qemu/crc32c.h: Rename include guards to match filename
target-arm: Add support for AArch32 ARMv8 CRC32 instructions
configure | 2 +-
include/qemu/crc32c.h | 4 ++--
target
Add support for AArch32 CRC32 and CRC32C instructions added in ARMv8.
The CRC32-C implementation used is the built-in qemu implementation
and The CRC-32 implementation is from zlib. This requires adding zlib
to LIBS to ensure it is linked for the linux-user binary.
Signed-off-by: Will Newton
for the linux-user binary.
Signed-off-by: Will Newton
---
configure | 2 +-
target-arm/cpu.c | 1 +
target-arm/cpu.h | 1 +
target-arm/helper.c| 39 +++
target-arm/helper.h| 3 +++
target-arm/translate.c | 56
Signed-off-by: Will Newton
Reviewed-by: Peter Maydell
---
include/qemu/crc32c.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Changes in v4:
- None
diff --git a/include/qemu/crc32c.h b/include/qemu/crc32c.h
index 56d1c3b..dafb6a1 100644
--- a/include/qemu/crc32c.h
+++ b/include
This series adds support for the AArch32 CRC32 instructions added in
ARMv8.
Will Newton (2):
include/qemu/crc32c.h: Rename include guards to match filename
target-arm: Add support for AArch32 ARMv8 CRC32 instructions
configure | 2 +-
include/qemu/crc32c.h | 4 ++--
target
Add support for AArch32 ARMv8 FP VRINTA, VRINTN, VRINTP and VRINTM
instructions.
Signed-off-by: Will Newton
---
target-arm/translate.c | 54 ++
1 file changed, 54 insertions(+)
Changes in v2:
- Add comment to fp_decode_rm lookup table
diff
This function will be needed for AArch32 ARMv8 support, so move it to
helper.c where it can be used by both targets. Also moves the code out
of line, but as it is quite a large function I don't believe this
should be a significant performance impact.
Signed-off-by: Will Newton
Reviewed-by:
Add support for the AArch32 floating-point VRINTR instruction.
Signed-off-by: Will Newton
---
target-arm/translate.c | 11 +++
1 file changed, 11 insertions(+)
Changes in v2:
- Move code outside the arms of the if
diff --git a/target-arm/translate.c b/target-arm/translate.c
index
Add support for the AArch32 floating-point VCVTA, VCVTN, VCVTP
and VCVTM instructions.
Signed-off-by: Will Newton
---
target-arm/translate.c | 61 ++
1 file changed, 61 insertions(+)
diff --git a/target-arm/translate.c b/target-arm/translate.c
Add support for the AArch32 floating-point VRINTZ instruction.
Signed-off-by: Will Newton
---
target-arm/translate.c | 16
1 file changed, 16 insertions(+)
Changes in v2:
- Move code outside the arms of the if
diff --git a/target-arm/translate.c b/target-arm/translate.c
Add support for the AArch32 Advanced SIMD VRINTA, VRINTN, VRINTP
VRINTM and VRINTZ instructions.
Signed-off-by: Will Newton
---
target-arm/translate.c | 40 +++-
1 file changed, 39 insertions(+), 1 deletion(-)
Changes in v2:
- Merge VRINTZ handling into the
Add support for the AArch32 floating-point VRINTX instruction.
Signed-off-by: Will Newton
---
target-arm/translate.c | 11 +++
1 file changed, 11 insertions(+)
Changes in v2:
- Move code outside the arms of the if
diff --git a/target-arm/translate.c b/target-arm/translate.c
index
Add support for the AArch32 Advanced SIMD VCVTA, VCVTN, VCVTP
and VCVTM instructions.
Signed-off-by: Will Newton
---
target-arm/translate.c | 53 +-
1 file changed, 52 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate.c b/target-arm
This helper sets the rounding mode in the standard_fp_status word to
allow NEON instructions to modify the rounding mode whilst using the
standard FPSCR values for everything else.
Signed-off-by: Will Newton
Reviewed-by: Peter Maydell
---
target-arm/helper.c | 17 +
target-arm
Add support for the AArch32 floating-point half-precision to double-
precision conversion VCVTB and VCVTT instructions.
Signed-off-by: Will Newton
---
target-arm/translate.c | 62 ++
1 file changed, 48 insertions(+), 14 deletions(-)
diff --git a
Add support for the AArch32 Advanced SIMD VRINTX instruction.
Signed-off-by: Will Newton
Reviewed-by: Peter Maydell
---
target-arm/translate.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 9eb5b92..c179817
Add support for the AArch32 floating-point half-precision to double-
precision conversion VCVTB and VCVTT instructions.
Signed-off-by: Will Newton
---
target-arm/translate.c | 74 ++
1 file changed, 56 insertions(+), 18 deletions(-)
Changes in v3
On 29 November 2013 15:26, Peter Maydell wrote:
> On 28 November 2013 17:07, Will Newton wrote:
>>
>> Floating point is an extension to the instruction set rather than
>> a coprocessor, so call it directly from the ARM and Thumb decode
>> functions.
>
> Hi;
This series adds support for three new instructions added in ARMv8 -
VSEL, VMINNM and VMAXNM.
Will Newton (6):
target-arm: Move call to disas_vfp_insn out of disas_coproc_insn.
target-arm: Implement ARMv8 VSEL instruction.
softfloat: Remove unused argument from MINMAX macro.
softfloat
Floating point is an extension to the instruction set rather than
a coprocessor, so call it directly from the ARM and Thumb decode
functions.
---
target-arm/translate.c | 32 +++-
1 file changed, 27 insertions(+), 5 deletions(-)
Changes in v7:
- Fix comment style
- F
This adds support for the ARMv8 floating point VMAXNM and VMINNM
instructions.
---
target-arm/helper.c| 25 +
target-arm/helper.h| 5 +
target-arm/translate.c | 50 ++
3 files changed, 80 insertions(+)
Changes in
The nan_exp argument is not used, so remove it.
---
fpu/softfloat.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Changes in v7:
- New patch
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 7ba51b6..97bf627 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -6706,7 +6706,7
This adds support for the VSEL floating point selection instruction
which was added in ARMv8.
---
target-arm/translate.c | 135 -
1 file changed, 134 insertions(+), 1 deletion(-)
Changes in v7:
- Break out VSEL handling into a function
- Properly
This adds support for the ARMv8 Advanced SIMD VMAXNM and VMINNM
instructions.
Signed-off-by: Will Newton
---
target-arm/helper.h | 3 +++
target-arm/neon_helper.c | 16
target-arm/translate.c | 31 ++-
3 files changed, 41 insertions(+), 9
Add floatnn_minnum() and floatnn_maxnum() functions which are equivalent
to the minNum() and maxNum() functions from IEEE 754-2008. They are
similar to min() and max() but differ in the handling of QNaN arguments.
---
fpu/softfloat.c | 54 +
Floating point is an extension to the instruction set rather than
a coprocessor, so call it directly from the ARM and Thumb decode
functions.
Signed-off-by: Will Newton
Reviewed-by: Peter Maydell
---
target-arm/translate.c | 32 +++-
1 file changed, 27 insertions
This adds support for the VSEL floating point selection instruction
which was added in ARMv8.
Signed-off-by: Will Newton
Reviewed-by: Peter Maydell
---
target-arm/translate.c | 135 -
1 file changed, 134 insertions(+), 1 deletion(-)
diff --git a
This adds support for the ARMv8 Advanced SIMD VMAXNM and VMINNM
instructions.
Signed-off-by: Will Newton
---
target-arm/translate.c | 31 ++-
1 file changed, 22 insertions(+), 9 deletions(-)
Changes in v8:
- Use VFP helper instead of adding a NEON specific one
This series adds support for three new instructions added in ARMv8 -
VSEL, VMINNM and VMAXNM.
Will Newton (6):
target-arm: Move call to disas_vfp_insn out of disas_coproc_insn.
target-arm: Implement ARMv8 VSEL instruction.
softfloat: Remove unused argument from MINMAX macro.
softfloat
This adds support for the ARMv8 floating point VMAXNM and VMINNM
instructions.
Signed-off-by: Will Newton
Reviewed-by: Peter Maydell
---
target-arm/helper.c| 25 +
target-arm/helper.h| 5 +
target-arm/translate.c | 50
The nan_exp argument is not used, so remove it.
Signed-off-by: Will Newton
Reviewed-by: Peter Maydell
---
fpu/softfloat.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 7ba51b6..97bf627 100644
--- a/fpu/softfloat.c
+++ b/fpu
Add floatnn_minnum() and floatnn_maxnum() functions which are equivalent
to the minNum() and maxNum() functions from IEEE 754-2008. They are
similar to min() and max() but differ in the handling of QNaN arguments.
Signed-off-by: Will Newton
---
fpu/softfloat.c | 32
On Thu, Dec 5, 2013 at 7:15 AM, Stefan Hajnoczi wrote:
> On Wed, Dec 04, 2013 at 11:21:12AM -0200, Eduardo Otubo wrote:
>> On 12/04/2013 07:39 AM, Stefan Hajnoczi wrote:
>> >On Fri, Nov 22, 2013 at 11:00:24AM -0500, Paul Moore wrote:
>> >>>Developers will only b
On Fri, Dec 6, 2013 at 3:13 AM, Stefan Hajnoczi wrote:
> On Thu, Dec 05, 2013 at 10:12:00AM -0600, Will Drewry wrote:
>> On Thu, Dec 5, 2013 at 7:15 AM, Stefan Hajnoczi wrote:
>> > On Wed, Dec 04, 2013 at 11:21:12AM -0200, Eduardo Otubo wrote:
>> >> On 12/04/2013 0
t;
> So, if you can point me to any arm model which can do usb passthrough
> I would be very happy. Thanks.
Just a word of warning - the Raspberry Pi uses a non-standard (i.e.
non-EHCI) USB host controller so it may prove very difficult to get
USB working.
--
Will Newton
Toolchain Working Group, Linaro
On 15 October 2013 16:09, Will Newton wrote:
>
> Floating point is an extension to the instruction set rather than
> a coprocessor, so call it directly from the ARM and Thumb decode
> functions.
>
> Signed-off-by: Will Newton
> ---
> tar
This adds support for the ARMv8 floating point VMAXNM and VMINNM
instructions.
Signed-off-by: Will Newton
---
target-arm/helper.c| 41 +
target-arm/helper.h| 5 +
target-arm/translate.c | 43 +++
3
Floating point is an extension to the instruction set rather than
a coprocessor, so call it directly from the ARM and Thumb decode
functions.
Signed-off-by: Will Newton
---
target-arm/translate.c | 30 +-
1 file changed, 25 insertions(+), 5 deletions(-)
Changes in
This adds support for the VSEL floating point selection instruction
which was added in ARMv8.
Signed-off-by: Will Newton
---
target-arm/translate.c | 130 -
1 file changed, 129 insertions(+), 1 deletion(-)
Changes in v6:
- None
diff --git a
This adds support for the ARMv8 Advanced SIMD VMAXNM and VMINNM
instructions.
Signed-off-by: Will Newton
---
target-arm/helper.h | 3 +++
target-arm/neon_helper.c | 24
target-arm/translate.c | 23 +--
3 files changed, 44 insertions(+), 6
: Will Newton
---
target-arm/translate.c | 121 +
1 file changed, 121 insertions(+)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 998bde2..7bfd606 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -2617,6
-by: Will Newton
---
target-arm/translate.c | 105 +
1 file changed, 105 insertions(+)
Changes in v2:
- Integrate vsel decoding into disas_vfp_insn
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 998bde2..5e49334 100644
--- a
On 3 October 2013 13:59, Peter Maydell wrote:
> On 3 October 2013 21:51, Will Newton wrote:
>>
>> This adds support for the VSEL floating point selection instruction
>> which was added in ARMv8. It is based on the previous patch[1] from
>> Mans Rullgard, but attem
This adds support for the VSEL floating point selection instruction
which was added in ARMv8.
Signed-off-by: Will Newton
---
target-arm/translate.c | 115 ++---
1 file changed, 110 insertions(+), 5 deletions(-)
Changes in v3:
- Move calls to
On 3 October 2013 15:34, Richard Henderson wrote:
> On 10/03/2013 05:51 AM, Will Newton wrote:
>> +case 0: /* eq: Z */
>> +tcg_gen_movcond_i64(TCG_COND_EQ, ftmp3, cpu_ZF,
>> zero,
>> +
Floating point is an extension to the instruction set rather than
a coprocessor, so call it directly from the ARM and Thumb decode
functions.
Signed-off-by: Will Newton
---
target-arm/translate.c | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/target
This adds support for the VSEL floating point selection instruction
which was added in ARMv8.
Signed-off-by: Will Newton
---
target-arm/translate.c | 113 +
1 file changed, 113 insertions(+)
Changes in v4:
- Fix leak of temporaries
- Extend
Floating point is an extension to the instruction set rather than
a coprocessor, so call it directly from the ARM and Thumb decode
functions.
Signed-off-by: Will Newton
---
target-arm/translate.c | 29 -
1 file changed, 24 insertions(+), 5 deletions(-)
Changes in
This adds support for the VSEL floating point selection instruction
which was added in ARMv8.
Signed-off-by: Will Newton
---
target-arm/translate.c | 130 -
1 file changed, 129 insertions(+), 1 deletion(-)
Changes in v5:
- Break out VSEL decode
ion is not
> implemented in the core.
>
> Signed-off-by: Lorenzo Pieralisi
> Reported-by: Guenter Roeck
> Cc: Will Deacon
> Cc: Peter Maydell
> Cc: Mark Rutland
> ---
> Based on arm64 for-next/perf branch.
>
> Tested on QEMU and Juno, I checked that the repor
*mb() explicitly does _NOT_
> > > cover the smp_*mb() part.
> > >
> > > Again, look at the ARM definitions, the smp_*mb() primitives use the
> > > inner coherence stuff, while the dma_*mb() primitives use the outer
> > > coherent stuff.
> >
> &g
CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
Basic design is to emulate the MSR by allowing reads and writes to the
hypervisor vcpu specific locations to store the value of the emulated MSRs.
In this way the IA32_TSC_ADJUST value will be included in all reads to
the TSC MSR
CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
Basic design is to emulate the MSR by allowing reads and writes to the
hypervisor vcpu specific locations to store the value of the emulated MSRs.
In this way the IA32_TSC_ADJUST value will be included in all reads to
the TSC MSR
Resending these as the mail seems to have not fully worked last Wed.
Marcelo,
I have addressed your comments for this patch set (V3), the following patch for
QEMU-KVM and for adding a test
case for tsc_adjust also to follow today.
Thanks,
Will
Will Auld (2):
Add code to track call
individual parameters.
The initial use for this capability is for updating the IA32_TSC_ADJUST
msr while setting the tsc value. It is anticipated that this capability
is useful other tasks.
Signed-off-by: Will Auld
---
arch/x86/include/asm/kvm_host.h | 12 +---
arch/x86/kvm/svm.c
CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
Basic design is to emulate the MSR by allowing reads and writes to a guest
vcpu specific location to store the value of the emulated MSR while adding
the value to the vmcs tsc_offset. In this way the IA32_TSC_ADJUST value will
be
CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
Basic design is to emulate the MSR by allowing reads and writes to the
hypervisor vcpu specific locations to store the value of the emulated MSRs.
In this way the IA32_TSC_ADJUST value will be included in all reads to
the TSC MSR
remained the same
- Also I would prefer adding host_initiated parameter to kvm_set_msr() instead
of introducing msr_data structure.
>From Marcelo:
- false, this is guest instruction emulation
I will address these points. However Gleb, your second item above,
host_initiated parameter was impl
This reversion, V4, addresses a couple of issues I missed from Gleb and Marcelo.
Thanks, Will
Will Auld (2):
Add code to track call origin for msr assignment.
Enabling IA32_TSC_ADJUST for KVM guest VM support
arch/x86/include/asm/cpufeature.h | 1 +
arch/x86/include/asm/kvm_host.h | 15
individual parameters.
The initial use for this capability is for updating the IA32_TSC_ADJUST
msr while setting the tsc value. It is anticipated that this capability
is useful other tasks.
Signed-off-by: Will Auld
---
arch/x86/include/asm/kvm_host.h | 12 +---
arch/x86/kvm/svm.c
CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
Basic design is to emulate the MSR by allowing reads and writes to a guest
vcpu specific location to store the value of the emulated MSR while adding
the value to the vmcs tsc_offset. In this way the IA32_TSC_ADJUST value will
be
CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
Basic design is to emulate the MSR by allowing reads and writes to the
hypervisor vcpu specific locations to store the value of the emulated MSRs.
In this way the IA32_TSC_ADJUST value will be included in all reads to
the TSC MSR
Andreas,
Thanks. I just sent the update patch (V3) to address your comments.
Will
> -Original Message-
> From: kvm-ow...@vger.kernel.org [mailto:kvm-ow...@vger.kernel.org] On
> Behalf Of Andreas Färber
> Sent: Monday, November 26, 2012 11:05 AM
> To: Auld, Will
> C
Sorry, let me figure this out and resend.
Thanks,
Will
> -Original Message-
> From: kvm-ow...@vger.kernel.org [mailto:kvm-ow...@vger.kernel.org] On
> Behalf Of Andreas Färber
> Sent: Monday, November 26, 2012 5:51 PM
> To: Auld, Will
> Cc: Will Auld; qemu-
CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
Basic design is to emulate the MSR by allowing reads and writes to the
hypervisor vcpu specific locations to store the value of the emulated MSRs.
In this way the IA32_TSC_ADJUST value will be included in all reads to
the TSC MSR
CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
Basic design is to emulate the MSR by allowing reads and writes to the
hypervisor vcpu specific locations to store the value of the emulated MSRs.
In this way the IA32_TSC_ADJUST value will be included in all reads to
the TSC MSR
Gleb,
This last change to emulator_set_msr() was wrong as you point out. I will
change it back to what it was in V3 with the exception of fixing the bool that
Marcelo pointed out.
However, the change of:
struct kvm_x86_ops {...
int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data
With this version (V5) I have gone back the the V3 implementation of
emulator_set_msr() but changing the
bool to false.
Will Auld (2):
Add code to track call origin for msr assignment.
Enabling IA32_TSC_ADJUST for KVM guest VM support
arch/x86/include/asm/cpufeature.h | 1 +
arch/x86
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