Re: [RFC PATCH] target/ppc: Remove xscmpnedp instruction

On 10/01/2022 12:02, Cédric Le Goater wrote: On 1/6/22 12:23, Víctor Colombo wrote: xscmpnedp was added in ISA v3.0 but removed in v3.0B. This patch removes this instruction as it was not in the final version of v3.0. Could please resend on top of the VSX combo patchset ? Absolutely! I wil

[PATCH 1/4] target/ppc: Fix xs{max,min}[cj]dp to use VSX registers

changing these instructions to use GEN_VSX_HELPER_X3. Signed-off-by: Victor Colombo --- target/ppc/fpu_helper.c | 4 ++-- target/ppc/helper.h | 8 target/ppc/translate/vsx-impl.c.inc | 8 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a

[PATCH 2/4] target/ppc: Move xs{max,min}[cj]dp to decodetree

Signed-off-by: Victor Colombo --- target/ppc/insn32.decode| 17 +--- target/ppc/translate/vsx-impl.c.inc | 30 + target/ppc/translate/vsx-ops.c.inc | 4 3 files changed, 40 insertions(+), 11 deletions(-) diff --git a/target/ppc/insn32

[PATCH 4/4] target/ppc: move xscvqpdp to decodetree

From: Matheus Ferst Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 10 +++--- target/ppc/helper.h | 2 +- target/ppc/insn32.decode| 4 target/ppc/translate/vsx-impl.c.inc | 24 +--- target/ppc/translate/vsx-ops.c

[PATCH 3/4] target/ppc: fix xscvqpdp register access

From: Matheus Ferst This instruction has VRT and VRB fields instead of T/TX and B/BX. Signed-off-by: Matheus Ferst --- target/ppc/translate/vsx-impl.c.inc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-im

[PATCH 0/4] target/ppc: Fix VSX instructions register access

Ferst (2): target/ppc: fix xscvqpdp register access target/ppc: move xscvqpdp to decodetree Victor Colombo (2): target/ppc: Fix xs{max,min}[cj]dp to use VSX registers target/ppc: Move xs{max,min}[cj]dp to decodetree target/ppc/fpu_helper.c | 14 +++- target/ppc/helper.h

[PATCH v2 0/4] target/ppc: Fix VSX instructions register access

: - Change ISA310 flag to ISA300 in xscvqpdp Matheus Ferst (2): target/ppc: fix xscvqpdp register access target/ppc: move xscvqpdp to decodetree Victor Colombo (2): target/ppc: Fix xs{max,min}[cj]dp to use VSX registers target/ppc: Move xs{max,min}[cj]dp to decodetree target/ppc/fpu_helper.c

[PATCH v2 2/4] target/ppc: Move xs{max,min}[cj]dp to decodetree

Reviewed-by: Richard Henderson Signed-off-by: Victor Colombo --- target/ppc/insn32.decode| 17 +--- target/ppc/translate/vsx-impl.c.inc | 30 + target/ppc/translate/vsx-ops.c.inc | 4 3 files changed, 40 insertions(+), 11 deletions

[PATCH v2 3/4] target/ppc: fix xscvqpdp register access

From: Matheus Ferst This instruction has VRT and VRB fields instead of T/TX and B/BX. Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/translate/vsx-impl.c.inc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/ppc/translate/vsx-impl.c.in

[PATCH v2 1/4] target/ppc: Fix xs{max, min}[cj]dp to use VSX registers

changing these instructions to use GEN_VSX_HELPER_X3. Reviewed-by: Richard Henderson Signed-off-by: Victor Colombo --- target/ppc/fpu_helper.c | 4 ++-- target/ppc/helper.h | 8 target/ppc/translate/vsx-impl.c.inc | 8 3 files changed, 10 insertions

[PATCH v2 4/4] target/ppc: move xscvqpdp to decodetree

From: Matheus Ferst Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/fpu_helper.c | 10 +++--- target/ppc/helper.h | 2 +- target/ppc/insn32.decode| 4 target/ppc/translate/vsx-impl.c.inc | 24 +---