Implementation for instructions hashst, hashchk, and its privileged
versions.
It was decided to implement the hash algorithm from ground up in this
patch exactly as described in Power ISA.
Signed-off-by: Víctor Colombo
---
RFC because I need some feedback on if the approach of implementing
make then fit in 80 columns
Signed-off-by: Víctor Colombo
---
target/ppc/cpu.h | 72
1 file changed, 36 insertions(+), 36 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 6d78078f37..c78f64cced 100644
--- a/target/ppc/cpu.h
++
On 27/06/2022 06:40, Rahul Pathak wrote:
mhartid csr is not available in user-mode code path and
user-mode build fails because of its reference in
riscv_cpu_realize function
Signed-off-by: Rahul Pathak
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/ri
subsws, xpnd04_2, 0, 30, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM_207(vaddcuq, 0, 5),
-GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
GEN_VXFORM_DUAL(vsubuqm, bcdtrunc, 0, 20, PPC2_ALTIVEC_207, PPC2_ISA300),
GEN_VXFORM_DUAL(vsubcuq, bcdutrunc, 0, 21, PPC2_ALTIVEC_20
M_300(bcdtrunc, 0, 20),
GEN_VXFORM_DUAL(vsubcuq, bcdutrunc, 0, 21, PPC2_ALTIVEC_207, PPC2_ISA300),
-GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
GEN_VXFORM(vsl, 2, 7),
GEN_VXFORM(vsr, 2, 11),
GEN_VXFORM(vpkuhum, 7, 0),
--
2.25.1
Reviewed-by: Víctor Colombo
--
Víctor Cora Colombo
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
0, 20, PPC2_ALTIVEC_207, PPC2_ISA300),
GEN_VXFORM_DUAL(vsubcuq, bcdutrunc, 0, 21, PPC2_ALTIVEC_207, PPC2_ISA300),
GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
--
2.25.1
Reviewed-by: Víctor Colombo
--
Víctor Cora Colombo
Instituto de Pesquisas ELD
no need to access
the elements in any particular order, and move the instruction to
decodetree.
Signed-off-by: Matheus Ferst
Reviewed-by: Víctor Colombo
--
Víctor Cora Colombo
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
C_207, PPC2_ISA300),
--
2.25.1
Reviewed-by: Víctor Colombo
--
Víctor Cora Colombo
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
EN_VXFORM_300(bcdtrunc, 0, 20),
GEN_VXFORM_DUAL(vsubcuq, bcdutrunc, 0, 21, PPC2_ALTIVEC_207, PPC2_ISA300),
GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
GEN_VXFORM(vsl, 2, 7),
--
2.25.1
Reviewed-by: Víctor Colombo
--
Víctor Cora Colombo
Instituto de P
RM_300(bcdtrunc, 0, 20),
-GEN_VXFORM_DUAL(vsubcuq, bcdutrunc, 0, 21, PPC2_ALTIVEC_207, PPC2_ISA300),
+GEN_VXFORM_300(bcdutrunc, 0, 21),
GEN_VXFORM(vsl, 2, 7),
GEN_VXFORM(vsr, 2, 11),
GEN_VXFORM(vpkuhum, 7, 0),
--
2.25.1
Reviewed-by: Víctor Colombo
--
Víctor Cora Colombo
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
: Add flag for ISA v2.06 BCDA instructions
target/ppc: implement addg6s
target/ppc: implement cbcdtd
target/ppc: implement cdtbcd
Víctor Colombo (7):
target/ppc: Fix insn32.decode style issues
target/ppc: Move mffscrn[i] to decodetree
target/ppc: Move mffsce to decodetree
target/ppc: Move
Some lines in insn32.decode have inconsistent alignment when compared
to others.
Fix this by changing the alignment of some lines, making it more
consistent throughout the file.
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
---
target/ppc/insn32.decode | 24
Signed-off-by: Víctor Colombo
Reviewed-by: Matheus Ferst
---
target/ppc/insn32.decode | 4 +++
target/ppc/translate/fp-impl.c.inc | 46 +++---
target/ppc/translate/fp-ops.c.inc | 2 --
3 files changed, 20 insertions(+), 32 deletions(-)
diff --git a/target
Signed-off-by: Víctor Colombo
Reviewed-by: Matheus Ferst
---
target/ppc/insn32.decode | 4
target/ppc/translate/fp-impl.c.inc | 35 +++---
target/ppc/translate/fp-ops.c.inc | 1 -
3 files changed, 21 insertions(+), 19 deletions(-)
diff --git a/target
Signed-off-by: Víctor Colombo
Reviewed-by: Matheus Ferst
---
target/ppc/insn32.decode | 8 +++
target/ppc/internal.h | 3 --
target/ppc/translate/fp-impl.c.inc | 83 +++---
target/ppc/translate/fp-ops.c.inc | 4 --
4 files changed, 50
Signed-off-by: Víctor Colombo
Reviewed-by: Matheus Ferst
---
target/ppc/insn32.decode | 5
target/ppc/translate/fp-impl.c.inc | 41 ++
2 files changed, 46 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 736a7c6f3f
avior is undefined, we try to match the result observed in
a POWER9 DD2.3.
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Signed-off-by: Víctor Colombo
---
target/ppc/dfp_helper.c| 39 ++
target/ppc/helper.h| 1 +
t
Signed-off-by: Víctor Colombo
Reviewed-by: Matheus Ferst
---
target/ppc/insn32.decode | 1 +
target/ppc/translate/fp-impl.c.inc | 38 +-
target/ppc/translate/fp-ops.c.inc | 2 --
3 files changed, 17 insertions(+), 24 deletions(-)
diff --git a/target/ppc
/EREF_RM.pdf
[2] https://www.nxp.com/docs/en/reference-manual/E6500RM.pdf
Signed-off-by: Matheus Ferst
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
---
target/ppc/cpu.h | 5 -
target/ppc/cpu_init.c | 10 ++
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git
Add mffsce test to check both the return value and the new fpscr
stored in the cpu.
Signed-off-by: Víctor Colombo
Reviewed-by: Matheus Ferst
---
tests/tcg/ppc64/Makefile.target | 1 +
tests/tcg/ppc64le/Makefile.target | 1 +
tests/tcg/ppc64le/mffsce.c| 37
iewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Signed-off-by: Víctor Colombo
---
target/ppc/dfp_helper.c| 26 ++
target/ppc/helper.h| 1 +
target/ppc/insn32.decode | 1 +
target/ppc/translate/fixed
From: Matheus Ferst
Implements the following Power ISA v2.06 instruction:
addg6s: Add and Generate Sixes
Signed-off-by: Matheus Ferst
Signed-off-by: Víctor Colombo
Reviewed-by: Víctor Colombo
---
target/ppc/insn32.decode | 4 +++
target/ppc/translate/fixedpoint-impl.c.inc
chine());
+if (mc) {
+ return object_class_by_name(mc->default_cpu_type);
+}
+}
+#endif
+
cpu_model = g_ascii_strdown(name, -1);
p = ppc_cpu_lookup_alias(cpu_model);
if (p) {
--
2.36.1
Reviewed-by: Víctor Colombo
Best regards,
--
Víctor Cora Colombo
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
On 02/07/2022 08:33, Alberto Faria wrote:
Alberto, hello. I was testing this patch as follows:
./static-analyzer.py build target/ppc/mmu-hash64.c
@@ -627,9 +744,31 @@ def is_coroutine_fn(node: Cursor) -> bool:
else:
break
-return node.kind == CursorKind.FUNCTION_
On 04/07/2022 13:57, Alberto Faria wrote:
Hi Víctor,
On Mon, Jul 4, 2022 at 3:18 PM Víctor Colombo
wrote:
And I receive an exception on the line above saying that node is of type
NoneType. Seems that `node = node.referenced` is setting `node` to None
in this case.
I was unable to understand
On 04/07/2022 15:04, Alberto Faria wrote:
On Mon, Jul 4, 2022 at 6:46 PM Víctor Colombo
wrote:
Yes, this line is present at the beginning of the output
Is this caused by problems with the code being analyzed or is it because
libclang is getting confused with something that is outside of our
On 22/02/2022 21:20, Richard Henderson wrote:> On 2/22/22 04:36,
matheus.fe...@eldorado.org.br wrote:
From: Víctor Colombo
Refactor VSX_SCALAR_CMP_DP, changing its name to VSX_SCALAR_CMP and
prepare the helper to be used for quadword comparisons.
Signed-off-by: Víctor Colombo
Signed-off
On 28/01/2022 10:12, Cédric Le Goater wrote:
The 602 was derived from the PowerPC 603, for the gaming market it
seems. It was hardly used and no firmware supporting the CPU could be
found. Drop support.
Signed-off-by: Cédric Le Goater
Hello Cédric! I am having problems building QEMU with this
igned-off-by: Víctor Colombo
---
This patch is a proposal on a previous RFC I sent on this topic [1].
I preferred this approach because it makes QEMU behavior closer to the
real hardware.
The affected instructions have the following note in the ISA:
"""
Previous versions of the
e inexact flags.
- Add patch 3, moving the renaming of sfprf to sfifprf to it
(previously on patch 1)
Víctor Colombo (3):
target/ppc: Fix FPSCR.FI bit being cleared when it shouldn't
target/ppc: Fix FPSCR.FI changing in float_overflow_excp()
target/ppc: Rename sfprf to sfifprf where i
D -> SET
xvnmsubmsp(0xf3c0c1fc8f3230, 0xbeaab9c5) = FI: CLEARED -> SET
(all tests assume FI is cleared beforehand)
Fix this by making float_overflow_excp() return float_flag_inexact
if it should update the inexact flags.
Signed-off-by: Víctor Colombo
---
v2:
- remove the setting of FI fr
The bit FI fix used the sfprf flag as a flag for the set_fi parameter
in do_float_check_status where applicable. Now, this patch rename this
flag to sfifprf to state this dual usage.
Signed-off-by: Víctor Colombo
---
v2: Add this patch
---
target/ppc/fpu_helper.c | 112
ap with the sfprf flag. So, reuse this flag for this purpose when
applicable.
Signed-off-by: Víctor Colombo
---
v2:
- move the FI change from float_inexact_excp to do_float_check_status
- sfprf will be renamed to sfifprf in another patch, as suggested by
Richard
---
target/ppc/cpu.h| 2
Hello!
Thanks everyone for your kind reviews
On 11/05/2022 07:12, Rashmica Gupta wrote:
Hello,
cc'ing Paul and Nick for clarification on the behaviour of xsrsp (see below)
On Tue, 2022-05-10 at 17:46 -0300, Víctor Colombo wrote:
The FI bit in FPSCR is said to be a non-sticky bit on
Make necessary changes for Multiply-Add instructions to use the
proposed reworked exceptions handling in do_float_check_status.
This should allow for cleaner code, not requiring the helper to check
multiple exceptions in its body.
Signed-off-by: Víctor Colombo
---
target/ppc/fpu_helper.c | 5
c/2022-05/msg00176.html
[2] <20220510204610.100867-1-victor.colo...@eldorado.org.br>
https://lists.nongnu.org/archive/html/qemu-ppc/2022-05/msg00246.html
https://patchew.org/QEMU/20220510204610.100867-1-victor.colo...@eldorado.org.br/
Víctor Colombo (2):
target/ppc: Add invalid
a gradual transition
for the instructions helpers. The 'defer' comes from the idea that the
exception raising is defered to be called somewhere else, as oposed of
what is being done in the original, 'non-defered' functions, which
immediatly call raise_exception_err_ra().
if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
+cpu->cfg.ext_a && cpu->cfg.ext_f &&
cpu->cfg.ext_d)) {
warn_report("Setting G will also se
will also set IMAFD");
cpu->cfg.ext_i = true;
--
2.34.1
Sorry, looks like I mistakenly reviewed v1 earlier
Reviewed-by: Víctor Colombo
--
Víctor Cora Colombo
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
On 14/05/2022 23:56, Tsukasa OI wrote:
Because "G" virtual extension expands to "IMAFD", we cannot separately
disable extensions like "F" or "D" without disabling "G". Because all
"IMAFD" are enabled by default, it's harmless to disable "G" by default.
Signed-off-by: Tsukasa OI
---
target/ri
D -> SET
xvnmsubmsp(0xf3c0c1fc8f3230, 0xbeaab9c5) = FI: CLEARED -> SET
(all tests assume FI is cleared beforehand)
Fix this by making float_overflow_excp() return float_flag_inexact
if it should update the inexact flags.
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
Re
) the only responsible for it.
- make float_overflow_excp() return float_flag_inexact if it should
update the inexact flags.
- Add patch 3, moving the renaming of sfprf to sfifprf to it
(previously on patch 1)
v3:
- rewrite patch 1 commit message
- fix missing comment change in patch 3
- add all R
plicable.
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
---
v3: Rewrite commit message to make it more clear
---
target/ppc/cpu.h| 2 +
target/ppc/fpu_helper.c | 122 +---
2 files changed, 66 insertions(+), 58 deletions(-)
diff --git
The bit FI fix used the sfprf flag as a flag for the set_fi parameter
in do_float_check_status where applicable. Now, this patch rename this
flag to sfifprf to state this dual usage.
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
Reviewed-by: Rashmica Gupta
---
v3: Fix missing
target/ppc: implement cbcdtd
target/ppc: implement cdtbcd
Víctor Colombo (6):
target/ppc: Fix insn32.decode style issues
target/ppc: Move mffs[.] to decodetree
target/ppc: Move mffsl to decodetree
target/ppc: Move mffsce to decodetree
target/ppc: Move mffscrn[i] to decodetree
target/ppc
Signed-off-by: Víctor Colombo
---
target/ppc/insn32.decode | 7 +++
target/ppc/translate/fp-impl.c.inc | 25 +
target/ppc/translate/fp-ops.c.inc | 1 -
3 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/target/ppc/insn32.decode b/target/ppc
Some lines in insn32.decode have inconsistent alignment when compared
to others.
Fix this by changing the alignment of some lines, making it more
consistent throughout the file.
Signed-off-by: Víctor Colombo
---
target/ppc/insn32.decode | 24
1 file changed, 12
Signed-off-by: Víctor Colombo
---
target/ppc/insn32.decode | 5 ++
target/ppc/internal.h | 3 --
target/ppc/translate/fp-impl.c.inc | 80 ++
target/ppc/translate/fp-ops.c.inc | 4 --
4 files changed, 20 insertions(+), 72 deletions(-)
diff
Signed-off-by: Víctor Colombo
---
target/ppc/insn32.decode | 4
target/ppc/translate/fp-impl.c.inc | 27 ---
target/ppc/translate/fp-ops.c.inc | 2 --
3 files changed, 12 insertions(+), 21 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc
Signed-off-by: Víctor Colombo
---
target/ppc/insn32.decode | 1 +
target/ppc/translate/fp-impl.c.inc | 45 +++---
target/ppc/translate/fp-ops.c.inc | 2 --
3 files changed, 18 insertions(+), 30 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc
/EREF_RM.pdf
[2] https://www.nxp.com/docs/en/reference-manual/E6500RM.pdf
Signed-off-by: Matheus Ferst
Signed-off-by: Víctor Colombo
---
target/ppc/cpu.h | 4 +++-
target/ppc/cpu_init.c | 9 +
2 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc
From: Matheus Ferst
Implements the following Power ISA v2.06 instruction:
addg6s: Add and Generate Sixes
Signed-off-by: Matheus Ferst
Signed-off-by: Víctor Colombo
---
target/ppc/insn32.decode | 4 +++
target/ppc/translate/fixedpoint-impl.c.inc | 35
Signed-off-by: Víctor Colombo
---
target/ppc/insn32.decode | 5 +
target/ppc/translate/fp-impl.c.inc | 35 ++
2 files changed, 40 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 682990b7f0..a3e87a0867 100644
--- a
igned-off-by: Matheus Ferst
Signed-off-by: Víctor Colombo
---
target/ppc/dfp_helper.c| 26 ++
target/ppc/helper.h| 1 +
target/ppc/insn32.decode | 1 +
target/ppc/translate/fixedpoint-impl.c.inc | 7 ++
4
avior is undefined, we try to match the result observed in
a POWER9 DD2.3.
Signed-off-by: Matheus Ferst
Signed-off-by: Víctor Colombo
---
target/ppc/dfp_helper.c| 39 ++
target/ppc/helper.h| 1 +
target/ppc/insn32.d
xscmpnedp was added in ISA v3.0 but removed in v3.0B. This patch
removes this instruction as it was not in the final version of v3.0.
RFC to know if you think this is the correct approach.
Signed-off-by: Víctor Colombo
---
target/ppc/fpu_helper.c | 1 -
target/ppc/helper.h
Hello everyone! Thanks Zoltan and Richard for your kind reviews!
On 26/04/2022 18:29, Richard Henderson wrote:
On 4/22/22 11:54, Víctor Colombo wrote:
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
---
hw/ppc/pegasos2.c | 2 +-
hw/ppc/spapr.c | 2
On 28/04/2022 03:46, Cédric Le Goater wrote:
On 4/27/22 19:00, Víctor Colombo wrote:
Hello everyone! Thanks Zoltan and Richard for your kind reviews!
On 26/04/2022 18:29, Richard Henderson wrote:
On 4/22/22 11:54, Víctor Colombo wrote:
Suggested-by: Richard Henderson
Signed-off-by: Víctor
1-11/msg00280.html
Patches requiring review: Patch 3 and after
Hello everyone, thanks for your kind reviews in v1,
What do you think of this new approach I did for v2?
v2:
- Abandon the ideia to add an M_MSR_* macro
- Instead, use registerfields API as suggested by Richard
- Add patch 21 to inver
fpscr_* defined macros are hiding the usage of *env behind them.
Substitute the usage of these macros with `env->fpscr & FP_*` to make
the code cleaner.
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Víctor Colombo
---
target/ppc/cpu.c| 2 +-
tar
Some msr_* macros are not used anywhere. Remove them as part of
the work to remove all hidden usage of *env.
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Víctor Colombo
---
target/ppc/cpu.h | 21 -
1 file changed, 21 deletions(-)
diff
msr_ds macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
---
v2: Remove M_MSR_DS and use FIELD_EX64 instead
Signed-off-by: Víctor C
msr_pr macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
---
v2: Remove M_MSR_PR and use FIELD_EX64 instead
Signed-off-by: Víctor C
Add FIELDs macros for msr bits that had an unused msr_* before.
Signed-off-by: Víctor Colombo
---
v2: Remove M_MSR_* and use FIELD macro now.
Signed-off-by: Víctor Colombo
---
target/ppc/cpu.h | 26 ++
1 file changed, 26 insertions(+)
diff --git a/target/ppc/cpu.h b
msr_ce macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
---
v2: Remove M_MSR_CE and use FIELD_EX64 instead
Signed-off-by: Víctor C
msr_ee macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
---
v2: Remove M_MSR_EE and use FIELD_EX64 instead
Signed-off-by: Víctor C
msr_le macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
---
v2: Remove M_MSR_LE and use FIELD_EX64 instead
Signed-off-by: Víctor C
msr_pow macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
---
v2: Remove M_MSR_POW and use FIELD_EX64 instead
Signed-off-by: Víctor C
msr_ile macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
---
v2: Remove M_MSR_ILE and use FIELD_EX64 instead
Signed-off-by: Víctor C
msr_fp macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
---
v2: Remove M_MSR_FP and use FIELD_EX64 instead
Signed-off-by: Víctor C
msr_me macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
---
v2: Remove M_MSR_ME and use FIELD_EX64 instead
Signed-off-by: Víctor C
msr_me macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
---
v2: Remove M_MSR_CM and use FIELD_EX64 instead
Signed-off-by: Víctor C
msr_gs macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
---
v2: Remove M_MSR_GS and use FIELD_EX64 instead
Signed-off-by: Víctor C
msr_dr macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
---
v2: Remove M_MSR_DR and use FIELD_EX64 instead
Signed-off-by: Víctor C
msr_ir macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
---
v2: Remove M_MSR_IR and use FIELD_EX64 instead
Signed-off-by: Víctor C
= msr_ep. The setup
to use FIELD_EX64 (calling FIELD macro in cpu.h) also adds a
R_MSR_EP_MASK which is equivalent to (1ull << MSR_EP). So, use
this mask to simplify the code.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
---
v2: Remove M_MSR_EP and use FIELD_EX64 inste
msr_fe0 and msr_fe1 macros hide the usage of env->msr, which is a bad
behavior. Substitute it with FIELD_EX64 calls that explicitly use
env->msr as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
---
v2: Remove M_MSR_FE* and use FIELD_EX64 instead. As t
msr_ts macro hides the usage of env->msr, which is a bad
behavior. Substitute it with FIELD_EX64 calls that explicitly use
env->msr as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
---
v2: Remove M_MSR_TS* and use FIELD_EX64 instead.
Signed-off-by: Víctor C
msr_hv macro hides the usage of env->msr, which is a bad
behavior. Substitute it with FIELD_EX64 calls that explicitly use
env->msr as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
---
v2: Remove M_MSR_HV and use FIELD_EX64 instead.
In this patch I'm
dy defined
PPC_BIT macro, which would turn MSR_* in masks instead of the numbers
itself.
Signed-off-by: Víctor Colombo
---
It'll also allow other places in cpu.h to be changed, like FSCR_*,
TEXASR_*, and FPSCR_*.
Signed-off-by: Víctor Colombo
---
target
msr_ile macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
---
target/ppc/cpu.h | 4 ++--
1 file chan
msr_fp macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
---
target/ppc/cpu.h | 2 +-
targ
sterfields API as suggested by Richard
- Add patch 21 to invert MSR_* values to match ISA ordering
v3:
- Add macro to extract both FE0 and FE1. Use it to simplify the
conditionals in patch 17
- Fix the checks that should be a xor
- Fix incorrect parameter in FIELD_EX64 (was env->msr should be va
Some msr_* macros are not used anywhere. Remove them as part of
the work to remove all hidden usage of *env.
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Víctor Colombo
---
target/ppc/cpu.h | 21 -
1 file changed, 21 deletions(-)
diff
msr_pr macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
---
hw/ppc/pegasos2.c| 2 +-
hw/ppc/s
msr_ee macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
---
target/ppc/cpu.h | 2 +-
targ
fpscr_* defined macros are hiding the usage of *env behind them.
Substitute the usage of these macros with `env->fpscr & FP_*` to make
the code cleaner.
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: Víctor Colombo
---
target/ppc/cpu.c| 2 +-
tar
msr_le macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
---
target/ppc/cpu.h| 2 +-
targ
msr_ds macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
---
target/ppc/cpu.h| 2 +-
targ
msr_ep macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
---
v3: Fix the difference check to use a xor
fix incorrect "FIELD_EX
msr_pow macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
---
target/ppc/cpu.h | 2 +-
targ
msr_ce macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
---
target/ppc/cpu.h | 2 +-
targ
msr_ts macro hides the usage of env->msr, which is a bad
behavior. Substitute it with FIELD_EX64 calls that explicitly use
env->msr as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
---
target/ppc/cpu.h | 2 +-
target/ppc
msr_gs macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
---
v3: Fix
!(value & env->msr & R_MSR_GS_MASK) -&g
msr_me macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
---
target/ppc/cpu.h | 2 +-
targ
msr_cm macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
---
v3: fix this patch's name (msr_ce
msr_hv macro hides the usage of env->msr, which is a bad
behavior. Substitute it with FIELD_EX64 calls that explicitly use
env->msr as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
---
target/ppc/cpu.h
msr_ir macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
---
v3: Fix the difference check to use a xor
Signed-off-by: Víctor C
Add FIELDs macros for msr bits that had an unused msr_* before.
Signed-off-by: Víctor Colombo
Acked-by: Richard Henderson
---
target/ppc/cpu.h | 26 ++
1 file changed, 26 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index f16a56fc55..1c40c7f0c6 100644
msr_dr macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson
Signed-off-by: Víctor Colombo
---
v3: Fix the difference check to use a xor
Signed-off-by: Víctor C
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