Hi Alex,
> -Original Message-
> From: Alex Bennée
> Sent: Saturday, March 11, 2023 2:03 AM
> To: qemu-devel@nongnu.org
> Cc: Alex Bennée ; Steven Lee
> ; Troy Lee ;
> Howard Chiu ; Jamin Lin
>
> Subject: [PATCH v2 03/10] contrib/gitdm: Add ASPEED Technology
Hi Joel,
On Tue, Feb 8, 2022 at 6:46 PM Joel Stanley wrote:
>
> Hello Troy,
>
> On Wed, 12 Jan 2022 at 08:10, Troy Lee wrote:
> >
> > Accumulative mode will supply a initial state and append padding bit at
> > the end of hash stream. However, the crypto libr
On Thu, Jan 6, 2022 at 11:27 PM Peter Maydell wrote:
>
> On Tue, 28 Dec 2021 at 03:34, Troy Lee wrote:
> >
> > Hi Klaus,
> >
> > On Thu, Dec 23, 2021 at 11:57 PM Klaus Heinrich Kiwi
> > wrote:
> > >
> > > Em qui., 23 de de
register fields macro
- Rebase to mainline QEMU
Troy Lee (2):
hw/misc: Implementating dummy AST2600 I3C model
hw/arm/aspeed_ast2600: create i3c instance
hw/arm/aspeed_ast2600.c | 19 +-
hw/misc/aspeed_i3c.c | 410 +++
hw/misc/meson.build | 1
This patch includes i3c instance in ast2600 soc.
v2: Rebase to mainline QEMU
Signed-off-by: Troy Lee
---
hw/arm/aspeed_ast2600.c | 19 ++-
include/hw/arm/aspeed_soc.h | 3 +++
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm
. If the device address
table register doesn't set correctly, it will cause guest machine kernel
panic due to reference to invalid address.
v2:
- Split i3c model into i3c and i3c_device
- Create 6x i3c devices
- Using register fields macro
Signed-off-by: Troy Lee
---
hw/misc/aspeed_
Hi Cedric,
On Mon, Jan 10, 2022 at 10:25 PM Cédric Le Goater wrote:
>
> Hello Troy,
>
> On 1/10/22 08:21, Troy Lee wrote:
> > Introduce a dummy AST2600 I3C model.
> >
> > Aspeed 2600 SDK enables I3C support by default. The I3C driver will try
> > to reset the
On Mon, Jan 10, 2022 at 10:31 PM Cédric Le Goater wrote:
>
> On 1/10/22 08:21, Troy Lee wrote:
> > This patch includes i3c instance in ast2600 soc.
> >
> > v2: Rebase to mainline QEMU
> >
> > Signed-off-by: Troy Lee
> > ---
> > hw/arm/aspeed_ast2
- Remove unrelated changes to SPI2 address
- Remove i3c controller irq line
v2:
- Split i3c model into i3c and i3c_device
- Create 6x i3c devices
- Using register fields macro
- Rebase to mainline QEMU
Troy Lee (2):
Introduce a dummy AST2600 I3C model.
This patch includes i3c instance in ast2600
ff-by: Troy Lee
---
hw/misc/aspeed_i3c.c | 381 +++
hw/misc/meson.build | 1 +
hw/misc/trace-events | 6 +
include/hw/misc/aspeed_i3c.h | 48 +
4 files changed, 436 insertions(+)
create mode 100644 hw/misc/aspeed_i3c.c
create mode 1
v3:
- Remove unrelated changes to SPI2 address
- Remove controller irq line
v2: Rebase to mainline QEMU
Signed-off-by: Troy Lee
---
hw/arm/aspeed_ast2600.c | 16
include/hw/arm/aspeed_soc.h | 3 +++
2 files changed, 19 insertions(+)
diff --git a/hw/arm/aspeed_ast2600.c b
[ Adding Klaus ]
On Wed, Jan 12, 2022 at 4:09 PM Troy Lee wrote:
>
> This add two addition test cases for accumulative mode under sg enabled.
>
> The input vector was manually craft with "abc" + bit 1 + padding zeros + L.
> The padding length depends on algorit
[ Adding Klaus ]
Sorry I forgot to add Klaus to the CC list.
On Wed, Jan 12, 2022 at 4:10 PM Troy Lee wrote:
>
> Accumulative mode will supply a initial state and append padding bit at
> the end of hash stream. However, the crypto library will padding those
> bit automatically,
/sha256sum utilities
without padding, i.e. only "abc" ascii text.
Signed-off-by: Troy Lee
---
tests/qtest/aspeed_hace-test.c | 145 +
1 file changed, 145 insertions(+)
diff --git a/tests/qtest/aspeed_hace-test.c b/tests/qtest/aspeed_hace-test.c
index 09
This patch series implements ast2600 hace engine with accumulative mode
and unit test against to it.
Changes in v2:
- Coding style
- Add accumulative mode description in comment
- Add unit test cases
Troy Lee (2):
hw/misc: Supporting AST2600 HACE accumulative mode
tests/qtest: Add test for
e the crypto library (gcrypt/glib) already pad the
padding message internally.
* This patch is to remove the padding message which fed byguest
machine driver.
Changes in v2:
- Coding style
- Add accumulative mode description in comment
Signed-off-by: Troy Lee
---
hw
On Wed, Jan 12, 2022 at 6:57 PM Graeme Gregory
wrote:
>
> On Tue, Jan 11, 2022 at 04:45:44PM +0800, Troy Lee wrote:
> > This series of patch introduce a dummy implemenation of aspeed i3c
> > model, and it provide just enough information for guest machine.
> > However, the
; Beraldo Leal
> ; open list:ASPEED BMCs ;
> open list:All patches CC here
> Cc: Steven Lee ; Troy Lee
>
> Subject: Re: [PATCH v5 7/9] aspeed/soc : Add AST1030 support
>
> ping
>
> On 29/12/22 12:16, Philippe Mathieu-Daudé wrote:
> > Hi,
> >
> > O
so.
>
> > Is there a way to have QEMU insert a barrier synchronization at some point
> in the bootloader? I think getting both cores past the =SCU_SMP_READY reset
> would get rid of this race, but I’m not aware of a way to do that kind of
> thing
> in QEMU-TCG.
> >
> > Thanks for any insights!
>
> Could we change the default value to registers 0x180 ... 0x18C in
> hw/misc/aspeed_scu.c to make sure the SMP regs are immune to the race ?
>
> Thanks,
>
> C.
Thanks,
Troy Lee
t;
> There is also this issue we discussed privately on SPI write
> transactions failing on the AST27000. It looked related to
> aspeed_smc_do_snoop() but we don't have a good fix yet.
>
> When time permits, could you please open a gitlab issue with
> your findings and logs, so that we don't forget.
>
>
> Thanks,
>
> C.
>
>
Thanks,
Troy Lee
Hi Cedric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Wednesday, June 1, 2022 3:10 PM
> To: Peter Delevoryas
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; zhdan...@fb.com; Troy
> Lee ; Jamin Lin ;
> Steven Lee ; k.jen...@samsung.com; Joe
> Komlodi
AST2600/1030 provides a new register mode which is controlled by
I2CG0C[2]. If the I2CG0C[2] = 1, then I2C will switch to a new set of
register.
This commit supports new register mode with packet operation and DMA
enabled. Byte/buffer mode is not implemented.
Signed-off-by: Troy Lee
Signed-off
Instanitate the I2C buses in AST1030 model and create two slave device
for ast1030-evb.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Signed-off-by: Steven Lee
---
hw/arm/aspeed_ast1030.c | 17 +
hw/arm/aspeed_minibmc.c | 13 +
2 files changed, 30 insertions
AST2600 Display Port MCU introduces 0x1800~0x1803 as it's memory
and io address. If guest machine try to access DPMCU memory, it will
cause a fatal error.
Signed-off-by: Troy Lee
---
hw/arm/aspeed_ast2600.c | 8
include/hw/arm/aspeed_soc.h | 2 ++
2 files change
AST2600 Display Port MCU introduces 0x1800~0x1803 as it's memory
and io address. If guest machine try to access DPMCU memory, it will
cause a fatal error.
Signed-off-by: Troy Lee
---
hw/arm/aspeed_ast2600.c | 8
include/hw/arm/aspeed_soc.h | 2 ++
2 files change
On Fri, Dec 10, 2021 at 10:05 PM Cédric Le Goater wrote:
>
> On 12/10/21 09:30, Troy Lee wrote:
> > AST2600 Display Port MCU introduces 0x1800~0x1803 as it's memory
> > and io address. If guest machine try to access DPMCU memory, it will
> > cause a fatal er
On Fri, Dec 10, 2021 at 11:13 PM Cédric Le Goater wrote:
>
> On 12/10/21 15:33, Troy Lee wrote:
> > On Fri, Dec 10, 2021 at 10:05 PM Cédric Le Goater wrote:
> >>
> >> On 12/10/21 09:30, Troy Lee wrote:
> >>> AST2600 Display Port MCU introduces 0x18000
Accumulative mode will supply a initial state and append padding bit at
the end of hash stream. However, the crypto library will padding those
bit automatically, so ripped it off from iov array.
Signed-off-by: Troy Lee
---
hw/misc/aspeed_hace.c | 30
This series of patch introduce a dummy implemenation of aspeed i3c
model, and it provide just enough information for guest machine.
However, the driver probing is still failed, but it will not cause
kernel panic.
Troy Lee (2):
hw/misc: Implementating dummy AST2600 I3C model
hw/arm
This patch includes i3c instance in ast2600 soc.
Signed-off-by: Troy Lee
---
hw/arm/aspeed_ast2600.c | 12
include/hw/arm/aspeed_soc.h | 3 +++
2 files changed, 15 insertions(+)
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index f2fef9d706..219b025bc2 100644
. If the device address
table register doesn't set correctly, it will cause guest machine kernel
panic due to reference to invalid address.
Signed-off-by: Troy Lee
---
hw/misc/aspeed_i3c.c | 258 +++
hw/misc/meson.build | 1 +
include/hw
Typo found during developing.
Fixes: 70b3f1a34d3c ("hw/misc: Add basic Aspeed PWM model")
Signed-off-by: Troy Lee
---
hw/misc/aspeed_pwm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/misc/aspeed_pwm.c b/hw/misc/aspeed_pwm.c
index 8ebab5dcef..dbf9634da3 10064
Hi Klaus,
On Thu, Dec 23, 2021 at 11:57 PM Klaus Heinrich Kiwi
wrote:
>
> Em qui., 23 de dez. de 2021 às 09:54, Cédric Le Goater
> escreveu:
> >
> > [ Adding Klaus ]
>
> Thanks Cedric. It's been a while since I've looked at this but I'll do my
>
Hi,
On Thu, Dec 23, 2021 at 9:48 PM Cédric Le Goater wrote:
>
>
> Hello,
>
> On 12/22/21 10:23, Troy Lee wrote:
> > Introduce a dummy AST2600 I3C model.
> >
> > Aspeed 2600 SDK enables I3C support by default. The I3C driver will try
> > to reset the dev
On Thu, Dec 23, 2021 at 9:54 PM Cédric Le Goater wrote:
>
> On 12/22/21 10:23, Troy Lee wrote:
> > This patch includes i3c instance in ast2600 soc.
> >
> > Signed-off-by: Troy Lee
>
> Looks good but it is based on the QEMU aspeed branch for OpenBMC.
> You shou
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2636
> Signed-off-by: Joel Stanley
Reviewed-by: Troy Lee
Troy Lee
> ---
> hw/fsi/aspeed_apb2opb.c | 2 +-
> hw/gpio/aspeed_gpio.c| 4 ++--
> hw/intc/aspeed_vic.c | 2 +-
> hw/misc/aspeed_scu.c | 4 ++
> -Original Message-
> From: Cédric Le Goater
> Sent: Tuesday, March 18, 2025 8:39 PM
> To: Troy Lee ; Peter Maydell
> ; Steven Lee ; Troy
> Lee ; Jamin Lin ; Andrew
> Jeffery ; Joel Stanley ;
> open list:ASPEED BMCs ; open list:All patches CC
> here
>
, AST27x0A0 only has 2 EHCI controllers due to hw issue.
Signed-off-by: Troy Lee
---
hw/arm/aspeed_ast27x0.c | 28
include/hw/arm/aspeed_soc.h | 4 +++-
2 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
Commit 6de4aa8dc544 ("hw/arm/aspeed_ast27x0: Add SoC Support for AST2700
A1") extends ast2700a1 spis_num to 3, but ASPEED_SPIS_NUM defines the
maximum number of spi controller to 2, result in ehci[0] is being
overwritten in runtime.
Signed-off-by: Troy Lee
---
include/hw/arm/aspeed
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