Hi Yuquan an Jon,
I added responses inline below.
On 3/6/24 07:23, Jonathan Cameron wrote:
> On Wed, 6 Mar 2024 19:27:07 +0800
> Yuquan Wang wrote:
>
>> Hello, Jonathan
>>
>> Recently I met some problems on CXL RAS tests.
>>
>> I tried to use "cxl-inject-uncorrectable-errors" and
>> "cxl-inje
Hi Jon,
This appears to partially address the same problem myself and Robert are
working on. We
are working to add support for CXL port devices to include root ports, RCECs,
USPs,
and DSPs. This was covered with LPC presentation and discussion.
We did not originally include RCEC error handlin
HI Yuquan,
For your test, the first logging will come from the AER driver if
everything is working correctly.
You may want to check if the upstream pci bridge's AER UIE/CIE
masks are set. This could prevent the error from handled by the OS's
aer driver.
Regards,
Terry
On 3/6/24 11
