Add new file to target/hexagon/meson.build
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/mmvec/decode_ext_mmvec.h | 24
target/hexagon/decode.c | 24 +++-
target/hexagon/mmvec/decode_ext_mmvec.c | 236
Probe and commit vector stores (masked and scatter/gather)
Log vector register writes
Add the execution counters to the debug log
Histogram instructions
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/helper.h| 16 +++
target/hexagon/op_helper.c | 282
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 150 +++
1 file changed, 150 insertions(+)
diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h
index 435c7b5..2d1d778 100644
--- a/target
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/translate.h | 61
target/hexagon/genptr.c| 15 +++
target/hexagon/translate.c | 239 -
3 files changed, 311 insertions(+), 4 deletions(-)
diff --git a
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/vector_add_int.c | 61 ++
tests/tcg/hexagon/Makefile.target | 3 ++
2 files changed, 64 insertions(+)
create mode 100644 tests/tcg/hexagon/vector_add_int.c
diff --git a
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/decode.c | 4 +
target/hexagon/imported/allextenc.def| 20 +
target/hexagon/imported/encode.def | 1 +
target/hexagon/imported/mmvec/encode_ext.def | 794
Tests for
packet semantics
vector loads (aligned and unaligned)
vector stores (aligned and unaligned)
vector masked stores
vector new value store
maximum HVX temps in a packet
vector operations
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
tests/tcg
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/hvx_histogram_input.h | 717
tests/tcg/hexagon/hvx_histogram_row.h | 24 ++
tests/tcg/hexagon/hvx_histogram.c | 88
tests/tcg/hexagon/Makefile.target | 5
Plan-A should be to update the container with the new toolchain.
Plan-B would be to remove the vector registers from the inline asm.
Thanks!
Taylor
> -Original Message-
> From: Richard Henderson
> Sent: Monday, November 1, 2021 8:44 AM
> To: Philippe Mathieu-Daudé ; Ta
> -Original Message-
> From: Richard Henderson
> Sent: Monday, November 1, 2021 10:03 AM
> To: Philippe Mathieu-Daudé ; Taylor Simpson
> ; qemu-devel@nongnu.org; Alex Bennée
>
> Cc: peter.mayd...@linaro.org
> Subject: Re: [PULL 28/30] Hexagon HVX (tests/tc
> -Original Message-
> From: Alex Bennée
> Sent: Tuesday, November 2, 2021 11:42 AM
> To: Taylor Simpson
> Cc: Richard Henderson ; Philippe Mathieu-
> Daudé ; qemu-devel@nongnu.org;
> peter.mayd...@linaro.org
> Subject: Re: [PULL 28/30] Hexagon HVX (tests/tc
gt; Sent: Wednesday, November 3, 2021 12:21 PM
> To: peter.mayd...@linaro.org
> Cc: richard.hender...@linaro.org; qemu-devel@nongnu.org; Alex Bennée
> ; Taylor Simpson
> Subject: Re: [PULL for 6.2 00/21] testing, plugin and gdbstub updates
>
> WARNING: This email originated fro
HVX is a set of wide vector instructions. Machine state includes
vector registers (VRegs)
vector predicate registers (QRegs)
temporary registers for intermediate values
store buffer (masked stores and scatter/gather)
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 50
1 file changed, 50 insertions(+)
diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h
index 916230e..ac2143e 100644
--- a/target
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/hex_regs.h | 1 +
target/hexagon/cpu.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/hex_regs.h b/target/hexagon/hex_regs.h
index f291911..e1b3149 100644
--- a/target
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/README | 81 ++-
1 file changed, 80 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/README b/target/hexagon/README
index b0b2435..372e247 100644
--- a/target
akefile to avoid need for toolchain upgrade
--------
Taylor Simpson (30):
Hexagon HVX (target/hexagon) README
Hexagon HVX (target/hexagon) add Hexagon Vector eXtensions (HVX) to core
Hexagon HVX (target/hexagon) regi
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_dectree_import.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/target/hexagon/gen_dectree_import.c
b/target/hexagon/gen_dectree_import.c
index 5b7ecfc..ee35467 100644
--- a/target/hexagon
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 103 +++
1 file changed, 103 insertions(+)
diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h
index f53a7f2..32f8e20 100644
--- a/target
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 42 ++
1 file changed, 42 insertions(+)
diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h
index f548404..f53a7f2 100644
--- a/target
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 31 +++
1 file changed, 31 insertions(+)
diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h
index a560504..916230e 100644
--- a/target/hexagon
macros to interface with the generator
macros referenced in instruction semantics
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/macros.h | 22 +++
target/hexagon/mmvec/macros.h | 354 ++
2 files changed, 376
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 26 ++
1 file changed, 26 insertions(+)
diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h
index 32f8e20..435c7b5 100644
--- a/target/hexagon
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/attribs_def.h.inc | 22 ++
1 file changed, 22 insertions(+)
diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc
index e44a7ea..dc890a5 100644
--- a/target/hexagon
Probe and commit vector stores (masked and scatter/gather)
Log vector register writes
Add the execution counters to the debug log
Histogram instructions
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/helper.h| 16 +++
target/hexagon/op_helper.c | 282
Add HVX support to the semantics generator
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_semantics.c | 33 +
target/hexagon/hex_common.py | 13 +
2 files changed, 46 insertions(+)
diff --git a/target/hexagon
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/translate.h | 61
target/hexagon/genptr.c| 15 +++
target/hexagon/translate.c | 239 -
3 files changed, 311 insertions(+), 4 deletions(-)
diff --git a
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 122 +++
1 file changed, 122 insertions(+)
diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h
index ac2143e..e865410 100644
--- a/target
Functions to support scatter/gather
Add new file to target/hexagon/meson.build
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/mmvec/system_ext_mmvec.h | 25 ++
target/hexagon/mmvec/system_ext_mmvec.c | 47
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 150 +++
1 file changed, 150 insertions(+)
diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h
index 435c7b5..2d1d778 100644
--- a/target
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/vector_add_int.c | 61 ++
1 file changed, 61 insertions(+)
create mode 100644 tests/tcg/hexagon/vector_add_int.c
diff --git a/tests/tcg/hexagon/vector_add_int.c
b/tests/tcg
Tests for
packet semantics
vector loads (aligned and unaligned)
vector stores (aligned and unaligned)
vector masked stores
vector new value store
maximum HVX temps in a packet
vector operations
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
tests/tcg
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/hvx_histogram_input.h | 717
tests/tcg/hexagon/hvx_histogram_row.h | 24 ++
tests/tcg/hexagon/hvx_histogram.c | 88
tests/tcg/hexagon/hvx_histogram_row.S | 294
instruction attributes that are applied
to each instruction that reverences the macro.
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/imported/allext_macros.def | 25 +
target/hexagon/imported/macros.def| 88
target/hexagon/imported/mmvec/macros.def | 842
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 34 ++
1 file changed, 34 insertions(+)
diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h
index e865410..f548404 100644
--- a/target/hexagon
Build the infrastructure to create overrides for HVX instructions.
We create a new empty file (gen_tcg_hvx.h) that will be populated
in subsequent patches.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_helper_funcs.py | 112 ++--
target/hexagon/gen_helper_protos.py | 16 ++-
target/hexagon/gen_tcg_funcs.py | 254 ++--
3 files changed, 360 insertions(+), 22
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 106 +++
1 file changed, 106 insertions(+)
diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h
index b5c6cad..a560504 100644
--- a/target
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 218 +++
1 file changed, 218 insertions(+)
diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h
index 2d1d778..cdcc938 100644
--- a/target
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/scatter_gather.c | 1011
1 file changed, 1011 insertions(+)
create mode 100644 tests/tcg/hexagon/scatter_gather.c
diff --git a/tests/tcg/hexagon/scatter_gather.c
b/tests/tcg
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/decode.c | 4 +
target/hexagon/imported/allextenc.def| 20 +
target/hexagon/imported/encode.def | 1 +
target/hexagon/imported/mmvec/encode_ext.def | 794
Add new file to target/hexagon/meson.build
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/mmvec/decode_ext_mmvec.h | 24
target/hexagon/decode.c | 24 +++-
target/hexagon/mmvec/decode_ext_mmvec.c | 236
> -Original Message-
> From: Philippe Mathieu-Daudé On
> Behalf Of Philippe Mathieu-Daudé
> Sent: Thursday, November 4, 2021 5:02 AM
> To: Daniel P. Berrangé
> Cc: Taylor Simpson ; Richard Henderson
> ; qemu-devel@nongnu.org; Laurent Vivier
>
> Subject: Re:
nks,
Taylor
-Original Message-
From: scan-ad...@coverity.com
Sent: Thursday, November 4, 2021 4:08 PM
To: Taylor Simpson
Subject: New Defects reported by Coverity Scan for QEMU
WARNING: This email originated from outside of Qualcomm. Please be wary of any
links or attachments, and do not enab
> -Original Message-
> From: Peter Maydell
> Sent: Friday, November 5, 2021 10:31 AM
> To: Taylor Simpson
> Cc: qemu-devel@nongnu.org; Richard Henderson
> ; Philippe Mathieu-Daudé
>
> Subject: Re: FW: New Defects reported by Coverity Scan for QEMU
>
&g
> From: Anton Johansson
> Sent: Monday, October 18, 2021 6:23 AM
> To: Taylor Simpson ; Alessandro Di Federico
> ; qemu-devel@nongnu.org
> Cc: Brian Cain ; bab...@rev.ng; ni...@rev.ng;
> richard.hender...@linaro.org; Alessandro Di Federico
> Subject: Re: [PATCH v6
> From: Anton Johansson
> Sent: Monday, October 18, 2021 6:37 AM
> To: Taylor Simpson ; Alessandro Di Federico
> ; qemu-devel@nongnu.org
> Cc: Brian Cain ; bab...@rev.ng; ni...@rev.ng;
> richard.hender...@linaro.org; Alessandro Di Federico
> Subject: Re: [PATCH v6
> From: Anton Johansson
> Sent: Monday, October 18, 2021 6:42 AM
> To: Taylor Simpson ; Alessandro Di Federico
> ; qemu-devel@nongnu.org
> Cc: Brian Cain ; bab...@rev.ng; ni...@rev.ng;
> richard.hender...@linaro.org; Alessandro Di Federico
> Subject: Re: [PATCH v6
l*
Fix bug to delay writes to USR until packet commit
--------
Taylor Simpson (2):
Hexagon (target/hexagon) more tcg_constant_*
Hexagon (target/hexagon) put writes to USR into temp until commit
target/hexagon/gen_tcg.h
: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h| 9 +++--
target/hexagon/macros.h | 7 +++
target/hexagon/translate.c | 3 +--
target/hexagon/gen_tcg_funcs.py | 11
: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/macros.h | 2 +-
target/hexagon/attribs_def.h.inc | 1 +
target/hexagon/translate.c| 9 +++-
tests/tcg/hexagon/overflow.c | 107 ++
target/hexagon/hex_common.py
> -Original Message-
> From: Richard Henderson
> Sent: Thursday, December 23, 2021 9:56 PM
> To: qemu-devel@nongnu.org
> Cc: alex.ben...@linaro.org; Taylor Simpson
> Subject: [PATCH 1/2] tests/tcg/multiarch: Read fp flags before printf
>
> We need to read
> -Original Message-
> From: Richard Henderson
> Sent: Wednesday, February 9, 2022 4:48 PM
> To: Philippe Mathieu-Daudé ; qemu-devel@nongnu.org
> Cc: Paolo Bonzini ; Thomas Huth
> ; Taylor Simpson
> Subject: Re: [PATCH 11/15] target: Use ArchCPU as interface to ta
> -Original Message-
> From: Richard Henderson
> Sent: Thursday, February 10, 2022 7:22 PM
> To: Taylor Simpson ; Philippe Mathieu-Daudé
> ; qemu-devel@nongnu.org
> Cc: Paolo Bonzini ; Thomas Huth
>
> Subject: Re: [PATCH 11/15] target: Use ArchCPU as interface to
Suggested-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu.h | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 58a0d3870b..e3efbb2303 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon
> -Original Message-
> From: Richard Henderson
> Sent: Thursday, February 10, 2022 7:03 PM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: f4...@amsat.org; a...@rev.ng; Brian Cain ; Michael
> Lambert
> Subject: Re: [PATCH v2 06/12] Hexagon (tests/tcg/hexag
The arch_sf_recip_common function was calling float32_getexp which
adjusts for denorm, but the we actually need the raw exponent bits.
This function is called from 3 instructions
sfrecipa
sffixupn
sffixupd
Test cases added to tests/tcg/hexagon/fpstuff.c
Signed-off-by: Taylor Simpson
/qemu-project/qemu/-/issues/831
Message-Id: <20220124064339.56027-1-zongyuan...@smartx.com>
Reviewed-by: Thomas Huth
Reviewed-by: Taylor Simpson
Signed-off-by: Taylor Simpson
---
target/hexagon/mmvec/macros.h | 4
1 file changed, 4 deletions(-)
diff --git a/target/hexagon/mmvec/macr
On Hexagon, c4 is an alias for predicate registers P3:0. If we assign to
c4 inside a packet with reads from predicate registers, the predicate
reads should get the old values.
Test case added to tests/tcg/hexagon/preg_alias.c
Co-authored-by: Michael Lambert
Signed-off-by: Taylor Simpson
Instead of checking for nan arguments, use float??_unordered_quiet
test cases added in a subsequent patch to more extensively test USR bits
Signed-off-by: Taylor Simpson
Message-Id: <20220210021556.9217-4-tsimp...@quicinc.com>
Reviewed-by: Richard Henderson
---
target/hexagon/op_helper
From: Michael Lambert
Versions V3 and earlier should treat the "K_const" and "length" values
as unsigned.
Modified circ_test_v3() in tests/tcg/hexagon/circ.c to reproduce the bug
Signed-off-by: Michael Lambert
Signed-off-by: Taylor Simpson
Message-Id: <2022
Suggested-by: Richard Henderson
Signed-off-by: Taylor Simpson
Message-Id: <20220211033034.21107-1-tsimp...@quicinc.com>
Reviewed-by: Richard Henderson
---
target/hexagon/cpu.h | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/target/hexagon/cpu.h b/target/h
Tests to confirm floating point instructions are properly
setting exception bits in USR
Signed-off-by: Taylor Simpson
Message-Id: <20220210021556.9217-8-tsimp...@quicinc.com>
Acked-by: Richard Henderson
---
tests/tcg/hexagon/usr.c | 339
1 file c
Add a test that sets USR multiple times in a packet
Signed-off-by: Taylor Simpson
Message-Id: <20220210021556.9217-9-tsimp...@quicinc.com>
Acked-by: Richard Henderson
---
tests/tcg/hexagon/overflow.c | 61 +++-
1 file changed, 60 insertions(+), 1 de
Two tests added to tests/tcg/hexagon/hvx_misc.c
v21.uw = vadd(v11.uw, v10.uw):sat
v25:24.uw = vsub(v17:16.uw, v27:26.uw):sat
Signed-off-by: Taylor Simpson
Message-Id: <20220210021556.9217-3-tsimp...@quicinc.com>
Reviewed-by: Richard Henderson
---
target/hexagon/macros.h
Hexagon has ~200 instructions that set the saturate bit in USR, these
were broken into groups of similar instructions and one instruction
from each group is tested with at least one input that does not
saturate and at least one input that does saturate.
Signed-off-by: Taylor Simpson
Message-Id
Fix typo that checked for 32 bit nan instead of 64 bit
Test case added in tests/tcg/hexagon/usr.c
Signed-off-by: Taylor Simpson
Message-Id: <20220210021556.9217-11-tsimp...@quicinc.com>
Reviewed-by: Richard Henderson
---
target/hexagon/op_helper.c | 2 +-
tests/tcg/hexagon/usr.c
remove an unused variable
Michael Lambert (1):
Hexagon (target/hexagon) fix bug in circular addressing
Taylor Simpson (10):
Hexagon HVX (target/hexagon) fix bug in HVX saturate instructions
Hexagon (target/hexagon
Replace consecutive inline asm blocks with a single one with proper
outputs/inputs/clobbers rather than making assumptions about register
values being carried between separate blocks.
Signed-off-by: Taylor Simpson
Message-Id: <20220210021556.9217-10-tsimp...@quicinc.com>
Reviewed-by: R
Please disregard.
I pulled 2 patches that haven't been reviewed but realized they are needed for
the new test case to pass.
My apologies,
Taylor
From: Taylor Simpson
Sent: Friday, February 11, 2022 5:17:10 AM
To: qemu-devel@nongnu.org
Cc: Taylor Si
Signed-off-by: Taylor Simpson
---
target/hexagon/op_helper.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 057baf9a48..daf0b0d348 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon
/hexagon/hvx_misc.c
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/hvx_misc.c| 45 +
target/hexagon/gen_tcg_funcs.py | 9 +++
2 files changed, 49 insertions(+), 5 deletions(-)
diff --git a/tests/tcg/hexagon/hvx_misc.c b/tests/tcg/hexagon/hvx_misc.c
index
Remove encodings guarded by ifdef that is not defined
Signed-off-by: Taylor Simpson
---
target/hexagon/imported/encode_pp.def | 23 ---
1 file changed, 23 deletions(-)
diff --git a/target/hexagon/imported/encode_pp.def
b/target/hexagon/imported/encode_pp.def
index
The increment used in :brev tests was causing unaligned addresses
Change the increment and the relevant expected values
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/load_unpack.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/tests/tcg/hexagon
These instructions will not be generated by idef-parser, so we override
them manually.
Test cases added to tests/tcg/hexagon/usr.c
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 10 ++-
target/hexagon/genptr.c | 147 +++
tests/tcg/hexagon
he fSTORE instances to fSTORE
- Assign the new attributes to the new macros
- Add definitions for the new macros
- Use the attributes from the instructions during translation to
set ctx->store_width
- Remove setting of ctx->store_width from genptr.c
Signed-off-by: Taylor Simpson
---
target/h
The test is in tests/tcg/multiarch/float_convd.c
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/float_convd.ref | 988 ++
1 file changed, 988 insertions(+)
create mode 100644 tests/tcg/hexagon/float_convd.ref
diff --git a/tests/tcg/hexagon/float_convd.ref
b
Add pc field to Packet structure
For helpers that need PC, pass an extra argument
Remove slot arg from conditional jump helpers
On a trap0, copy pkt->pc into hex_gpr[HEX_REG_PC]
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h| 7 +++
target/hexagon/ins
need_pkt_has_multi_cof
Address feedback from Matheus Tavares Bernardino
Rearrange new-value-jump overrides
Simplify gen_write_new_pc_addr
Taylor Simpson (11):
Hexagon (target/hexagon) Add pkt and insn to DisasContext
Hexagon (target/hexagon) Fix predicated assignment to .tmp and .cur
These instructions will not be generated by idef-parser, so we override
them manually.
Test cases added to tests/tcg/hexagon/usr.c
Co-authored-by: Matheus Tavares Bernardino
Signed-off-by: Matheus Tavares Bernardino
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 10 ++-
target
Add overrides for
J2_call
J2_callt
J2_callf
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 8 ++
target/hexagon/genptr.c | 55
2 files changed, 63 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 177 +++
target/hexagon/genptr.c | 72
2 files changed, 249 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index fe0a5e9c13..8b311d16e0 100644
The imported files don't properly mark all CONDEXEC instructions, so
we add some logic to hex_common.py to add the attribute.
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu.h| 1 -
target/hexagon/gen_tcg.h| 6 ++
target/hexagon/macros.h
branch is taken
branch_dest
The destination of the branch
Signed-off-by: Taylor Simpson
---
target/hexagon/translate.h | 3 +++
target/hexagon/genptr.c| 13 -
target/hexagon/translate.c | 39 +-
3 files changed, 53 insertions(+), 2
PC.
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu.h | 17
target/hexagon/gen_tcg.h | 3 ++
target/hexagon/translate.h | 1 +
target/hexagon/genptr.c| 57 ++
target/hexagon/translate.c | 34 +++
5 files
This enables us to reduce the number of parameters to many functions
In particular, the generated functions previously took all 3 as arguments
Not only does this simplify the code, it improves the translation time
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h| 6
er to the Packet structure, and pass this
information to the needed functions.
When there is a generated helper function with cof, the generator will
pass this pkt_has_multi_cof as a runtime value.
Signed-off-by: Taylor Simpson
---
target/hexagon/insn.h | 1 +
target/hexagon/mac
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 189 +++
target/hexagon/genptr.c | 45 ++
2 files changed, 234 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 8b311d16e0..93afa01156 100644
--- a
: Matheus Tavares Bernardino
Signed-off-by: Matheus Tavares Bernardino
Signed-off-by: Taylor Simpson
---
target/hexagon/translate.h | 6 +++
tests/tcg/hexagon/hvx_misc.c| 72 +
target/hexagon/gen_tcg_funcs.py | 12 ++
3 files changed, 90 insertions(+)
diff
> -Original Message-
> From: Richard Henderson
> Sent: Friday, November 4, 2022 8:33 PM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: phi...@linaro.org; a...@rev.ng; a...@rev.ng; Brian Cain
> ; Matheus Bernardino (QUIC)
>
> Subject: Re: [PATCH v3 10/11]
> -Original Message-
> From: Richard Henderson
> Sent: Friday, November 4, 2022 8:44 PM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: phi...@linaro.org; a...@rev.ng; a...@rev.ng; Brian Cain
> ; Matheus Bernardino (QUIC)
>
> Subject: Re: [PATCH v3 11/11]
pdate test case to use both true and false predicates
Add fix for .cur
Simplify test in need_pkt_has_multi_cof
Address feedback from Matheus Tavares Bernardino
Rearrange new-value-jump overrides
Simplify gen_write_new_pc_addr
Taylor Simpson (11):
Hexagon (target/hexagon) Add pkt a
These instructions will not be generated by idef-parser, so we override
them manually.
Test cases added to tests/tcg/hexagon/usr.c
Co-authored-by: Matheus Tavares Bernardino
Signed-off-by: Matheus Tavares Bernardino
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 10
PC.
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu.h | 13 +++---
target/hexagon/gen_tcg.h | 3 ++
target/hexagon/translate.h | 1 +
target/hexagon/genptr.c| 84 ++
target/hexagon/translate.c | 34
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 203 +++
target/hexagon/genptr.c | 43 +
2 files changed, 246 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index
Acked-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 177 +++
target/hexagon/genptr.c | 90
2 files changed, 267 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index
branch_cond == TCG_COND_NEVER, there isn't a single
direct branch in this packet.
When branch_cond != TCG_COND_ALWAYS, the value is in
hex_branch_taken
branch_dest
The destination of the branch
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Si
Add overrides for
J2_call
J2_callt
J2_callf
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 8 ++
target/hexagon/genptr.c | 55
2 files changed, 63 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon
This enables us to reduce the number of parameters to many functions
In particular, the generated functions previously took all 3 as arguments
Not only does this simplify the code, it improves the translation time
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon
Add pc field to Packet structure
For helpers that need PC, pass an extra argument
Remove slot arg from conditional jump helpers
On a trap0, copy pkt->pc into hex_gpr[HEX_REG_PC]
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h
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