Per ast1030_v7.pdf, AST1030 HACE engine is identical to AST2600's HACE
engine.
Signed-off-by: Steven Lee
---
hw/misc/aspeed_hace.c | 20
include/hw/misc/aspeed_hace.h | 2 ++
2 files changed, 22 insertions(+)
diff --git a/hw/misc/aspeed_hace.c b/hw
Per ast1030_v7.pdf, AST1030 HACE engine is identical to AST2600's HACE
engine.
Please help to review.
Thanks,
Steven
Based-on: 20220426021120.28255-3-steven_...@aspeedtech.com
([v6,2/3] aspeed/hace: Support AST2600 HACE)
Steven Lee (1):
aspeed/hace: Support AST1030 HACE
hw
AST2600's HPLL register offset and bit definition are different from
AST2500. Add a hpll calculation function for ast2600 and modify apb frequency
calculation function based on SCU200 register description in ast2600v11.pdf.
Signed-off-by: Steven Lee
---
hw/misc/aspeed_scu.c
teven
Steven Lee (1):
hw: aspeed_scu: Add AST2600 hpll calculation function
hw/misc/aspeed_scu.c | 43
include/hw/misc/aspeed_scu.h | 17 ++
2 files changed, 56 insertions(+), 4 deletions(-)
--
2.17.1
The 03/14/2022 20:21, Cédric Le Goater wrote:
> Hello Steven,
>
> On 3/14/22 10:54, Steven Lee wrote:
> > AST2600's HPLL register offset and bit definition are different from
> > AST2500. Add a hpll calculation function for ast2600 and modify apb
> > frequency
&
AST2600's HPLL register offset and bit definition are different from
AST2500. Add a hpll calculation function and an apb frequency calculation
function based on SCU200 register description in ast2600v11.pdf.
Signed-off-by: Steven Lee
---
hw/misc/aspeed_scu.c
AST2600 clkin is always 25MHz, introduce clkin_25Mhz attribute
for aspeed_scu_get_clkin() to return the correct clkin for ast2600.
Signed-off-by: Steven Lee
---
hw/misc/aspeed_scu.c | 6 +-
include/hw/misc/aspeed_scu.h | 1 +
2 files changed, 6 insertions(+), 1 deletion(-)
diff
0 and ast2600 get_apb_freq class handlers.
- introduce clkin_25Mhz attribute.
Please help to review.
Thanks,
Steven
Steven Lee (2):
hw: aspeed_scu: Add AST2600 apb_freq and hpll calculation function
hw: aspeed_scu: Introduce clkin_25Mhz attribute
hw/misc/aspeed_scu.c
/sha256sum utilities
without padding, i.e. only "abc" ascii text.
Signed-off-by: Troy Lee
Signed-off-by: Steven Lee
---
tests/qtest/aspeed_hace-test.c | 145 +
1 file changed, 145 insertions(+)
diff --git a/tests/qtest/aspeed_hace-test.c b/tests/qtest/aspe
login.
- AST1030 with ASPEED zephyr SDK v1.04
- run `hash sha256` command in zephyr shell to verify aspeed hace.
Please help to review
Thanks,
Steven
Changes in v3:
- Refactor acc_mode message handling flow.
Steven Lee (2):
aspeed/hace: Support AST2600 HACE
tests/qtest: Add test for Aspeed HACE
ff-by: Troy Lee
Signed-off-by: Steven Lee
---
hw/misc/aspeed_hace.c | 113 +++---
include/hw/misc/aspeed_hace.h | 1 +
2 files changed, 105 insertions(+), 9 deletions(-)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index 10f00e65f4..a883625e92 1
.
>
Hi Joel,
Thanks for the review and sorry for late reply, I was taking Monday off.
I added some examples to describe the driver behavior below, hope it helps.
> On Fri, 25 Mar 2022 at 03:58, Steven Lee wrote:
> >
> > The aspeed ast2600 acculumative mode is described in
Support HACE28: Hash HMAC Key Buffer Base Address Register.
Signed-off-by: Troy Lee
Signed-off-by: Steven Lee
---
hw/misc/aspeed_hace.c | 7 +++
include/hw/misc/aspeed_hace.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index
ff-by: Troy Lee
Signed-off-by: Steven Lee
---
hw/misc/aspeed_hace.c | 140 --
1 file changed, 136 insertions(+), 4 deletions(-)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index 59fe5bfca2..5a7a144602 100644
--- a/hw/misc/aspeed_hace.c
+++
login.
- AST1030 with ASPEED zephyr SDK v1.04
- run `hash sha256` command in zephyr shell to verify aspeed hace.
Please help to review.
Thanks,
Steven
Changes in v4:
- Separate HACE28 support to another patch.
- Refactor acc_mode message handling flow.
Steven Lee (3):
aspeed/hace: Support HMAC
/sha256sum utilities
without padding, i.e. only "abc" ascii text.
Signed-off-by: Troy Lee
Signed-off-by: Steven Lee
---
tests/qtest/aspeed_hace-test.c | 145 +
1 file changed, 145 insertions(+)
diff --git a/tests/qtest/aspeed_hace-test.c b/tests/qtest/aspe
The 04/20/2022 20:53, Cédric Le Goater wrote:
> On 3/31/22 09:48, Steven Lee wrote:
> > The aspeed ast2600 accumulative mode is described in datasheet
> > ast2600v10.pdf section 25.6.4:
> > 1. Allocating and initiating accumulative hash digest write buffer
> &
/sha256sum utilities
without padding, i.e. only "abc" ascii text.
Signed-off-by: Troy Lee
Signed-off-by: Steven Lee
Acked-by: Thomas Huth
Reviewed-by: Joel Stanley
---
tests/qtest/aspeed_hace-test.c | 145 +
1 file changed, 145 insertions(+)
diff
ff-by: Troy Lee
Signed-off-by: Steven Lee
---
hw/misc/aspeed_hace.c | 132 --
include/hw/misc/aspeed_hace.h | 4 ++
2 files changed, 131 insertions(+), 5 deletions(-)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index 59fe5bfca2..3164f6 1
Support HACE28: Hash HMAC Key Buffer Base Address Register.
Signed-off-by: Troy Lee
Signed-off-by: Steven Lee
Reviewed-by: Cédric Le Goater
---
hw/misc/aspeed_hace.c | 7 +++
include/hw/misc/aspeed_hace.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/hw/misc/aspeed_hace.c
AspeedHACEState.
Steven Lee (3):
aspeed/hace: Support HMAC Key Buffer register.
aspeed/hace: Support AST2600 HACE
tests/qtest: Add test for Aspeed HACE accumulative mode
hw/misc/aspeed_hace.c | 139 +--
include/hw/misc/aspeed_hace.h | 5 ++
tests/qtest
The 04/25/2022 21:46, Cédric Le Goater wrote:
> On 4/22/22 07:19, Steven Lee wrote:
> > +/**
> > + * Check whether the request contains padding message.
> > + *
> > + * @param s aspeed hace state object
> > + * @param iov iov of curre
/sha256sum utilities
without padding, i.e. only "abc" ascii text.
Signed-off-by: Troy Lee
Signed-off-by: Steven Lee
Acked-by: Thomas Huth
Reviewed-by: Joel Stanley
---
tests/qtest/aspeed_hace-test.c | 145 +
1 file changed, 145 insertions(+)
diff
login.
- AST1030 with ASPEED zephyr SDK v1.04
- run `hash sha256` command in zephyr shell to verify aspeed hace.
Please help to review.
Thanks,
Steven
Changes in v6:
- Bug fixes in reconstruct_iov().
Steven Lee (3):
aspeed/hace: Support HMAC Key Buffer register.
aspeed/hace: Support AST2600
ff-by: Troy Lee
Signed-off-by: Steven Lee
---
hw/misc/aspeed_hace.c | 132 --
include/hw/misc/aspeed_hace.h | 4 ++
2 files changed, 131 insertions(+), 5 deletions(-)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index 59fe5bfca2..0f4059e6df 1
Support HACE28: Hash HMAC Key Buffer Base Address Register.
Signed-off-by: Troy Lee
Signed-off-by: Steven Lee
Reviewed-by: Cédric Le Goater
---
hw/misc/aspeed_hace.c | 7 +++
include/hw/misc/aspeed_hace.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/hw/misc/aspeed_hace.c
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Tuesday, January 7, 2025 11:51 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
&
Hi Philippe,
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Wednesday, December 25, 2024 7:28 PM
> To: Steven Lee ; Cédric Le Goater
> ; Peter Maydell ; Troy Lee
> ; Jamin Lin ; Andrew
> Jeffery ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All
Hi Philippe,
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Wednesday, December 25, 2024 7:30 PM
> To: Steven Lee ; Cédric Le Goater
> ; Peter Maydell ; Troy Lee
> ; Jamin Lin ; Andrew
> Jeffery ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Friday, December 27, 2024 3:57 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
&
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Friday, December 27, 2024 5:53 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
&
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Friday, January 3, 2025 5:44 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
&
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Thursday, January 2, 2025 4:29 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
&
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Thursday, January 2, 2025 4:42 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
&
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Thursday, January 2, 2025 4:44 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
&
> -Original Message-
> From: Cédric Le Goater
> Sent: Friday, March 7, 2025 3:44 PM
> To: Jamin Lin ; Peter Maydell
> ; Steven Lee ; Troy
> Lee ; Andrew Jeffery ;
> Joel Stanley ; open list:All patches CC here
> ; open list:ASPEED BMCs
>
> Cc: Troy Lee
Hi Cédric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Thursday, March 20, 2025 11:29 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
This initial module adds support for the AST27x0 SoC, which features
four Cortex-A35 cores and two Cortex-M4 cores. The patch enables emulation
of the Cortex-M4 cores, laying the groundwork for co-processor support.
Signed-off-by: Steven Lee
---
hw/arm/aspeed_ast27x0-cm4.c | 397
serial2)
$ tio /dev/pts/51
$ tio /dev/pts/52
$ tio /dev/pts/53
$ (qemu) c
Steven Lee (5):
aspeed: Make sdhci_attach_drive and write_boot_rom public
aspeed: ast27x0: Map unimplemented devices in SoC memory
aspeed: Introduce AST27x0 SoC with Cortex-M4 support
aspeed: Introduce ast2700-fc
This commit adds a section describing the ast2700-fc multi-SoC machine.
Signed-off-by: Steven Lee
---
docs/system/arm/aspeed.rst | 50 --
1 file changed, 48 insertions(+), 2 deletions(-)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
Maps following unimplemented devices in SoC memory
- dpmcu
- iomem0
- iomem1
- ltpi
- io
Signed-off-by: Steven Lee
---
hw/arm/aspeed_ast27x0.c | 45 +++--
include/hw/arm/aspeed_soc.h | 6 +
2 files changed, 44 insertions(+), 7 deletions(-)
diff --git a
sdhci_attach_drive and write_boot_rom functions may be used by
the aspeed machine supporting co-processors.
Signed-off-by: Steven Lee
---
hw/arm/aspeed.c | 4 ++--
include/hw/arm/aspeed.h | 6 ++
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm
)
char device redirected to /dev/pts/53 (label serial2)
tio /dev/pts/51
tio /dev/pts/52
tio /dev/pts/53
(qemu) c
Signed-off-by: Steven Lee
---
hw/arm/aspeed_ast27x0-fc.c | 211
hw/arm/meson.build | 4 +-
include/hw/arm/aspeed_soc.h
Add functional test for AST2700a1-fc machine.
Signed-off-by: Steven Lee
Change-Id: I87584164b2632c58d2e051fd92d9e280347bcf19
---
tests/functional/test_aarch64_ast2700fc.py | 38 +-
1 file changed, 30 insertions(+), 8 deletions(-)
diff --git a/tests/functional
Bit 4 -> SSPINT 164
Signed-off-by: Steven Lee
Change-Id: Ic5121dd78c5dacf1ec4b4e791cc7bf476a8b608f
---
hw/arm/aspeed_ast27x0-ssp.c | 91 +
1 file changed, 91 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 88f27
Corrected the hexadecimal notation for several device addresses in the
aspeed_soc_ast2700_memmap array by changing the uppercase 'X' to
lowercase 'x'.
Signed-off-by: Steven Lee
Change-Id: I45426e18ea8e68d7ccdf9b60c4ea235c4da33cc3
---
hw/arm/aspeed_ast27x0.c | 28 +++
support for UART, INTC, and SCU devices
- Map unimplemented devices for IPC and SCUIO
Signed-off-by: Steven Lee
Change-Id: If83e752873af393f3b71249176454399de0be40f
---
include/hw/arm/aspeed_soc.h | 14 ++
hw/arm/aspeed_ast27x0-ssp.c | 309
hw/arm/meson.build
0x14C5000
- PWM at 0x140C
DPMCU stands for Display Port MCU controller. LTPI is used to connect
to AST1700.
AST1700 is an I/O expander that supports the DC-SCM 2.1 LTPI protocol.
It provides AST2700 with additional GPIO, UART, I3C, and other
interfaces.
Signed-off-by: Steven Lee
Change-Id
- Updated Aspeed family boards list to include `ast2700fc`.
- Added boot instructions for the `ast2700fc` machine.
- Detailed the configuration and loading of firmware for the
Cortex-A35 and Cortex-M4 processors.
Signed-off-by: Steven Lee
Change-Id: I48d90589d29ae6bb70a172e1798f18c0c38e6e22
TC
The INTCIO SSPINT_160_169 has 10 output pins, mapped as follows:
Bit 0 -> SSPINT 160
Bit 1 -> SSPINT 161
Bit 2 -> SSPINT 162
Bit 3 -> SSPINT 163
Bit 4 -> SSPINT 164
Signed-off-by: Steven Lee
Change-Id: I5329767b21c0e982d3afcb87c7d1690cc04ce2ef
---
inclu
Bit 4 -> TSPINT 164
Signed-off-by: Steven Lee
Change-Id: Ia96cc94d10c26b77caf00dd1346565382474e937
---
hw/arm/aspeed_ast27x0-tsp.c | 91 +
1 file changed, 91 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index ed14a
terminal emulator.
Signed-off-by: Steven Lee
Change-Id: I1e7645a4689859fdd41be2a734909975ba04a1f9
---
hw/arm/aspeed_ast27x0-fc.c | 150 +
1 file changed, 150 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index d03a1b5f1e
AST27x0 A0 TSP SoC and AST27x0 A1 TSP SoC
- Add functional tests for AST2700FC A0 and AST2700FC A1
- Add Documentation for AST2700FC
Steven Lee (13):
aspeed: ast27x0: Map unimplemented devices in SoC memory
aspeed: ast27x0: Correct hex notation for device addresses
hw/intc/aspeed: Add
TC
The INTCIO TSPINT_160_169 has 10 output pins, mapped as follows:
Bit 0 -> TSPINT 160
Bit 1 -> TSPINT 161
Bit 2 -> TSPINT 162
Bit 3 -> TSPINT 163
Bit 4 -> TSPINT 164
Signed-off-by: Steven Lee
Change-Id: I9e71a8aac400c0cdbd5b78073d0ada79d12a1350
---
inclu
Introduce a new functional test for AST2700 multi-SoCs.
The test includes booting ast2700 with bmc image on
ca35 cores and booting ssp/tsp firmware on cm4 cores.
Assets for SDK and SSP/TSP images are downloaded from
AspeedTech-BMC's OpenBmc release page.
Signed-off-by: Steven Lee
Chan
support for UART, INTC, and SCU devices
- Map unimplemented devices for IPC and SCUIO
Signed-off-by: Steven Lee
Change-Id: I8ac6e79a2739c76b802a1dfd6c7a7ef357de60a6
---
include/hw/arm/aspeed_soc.h | 12 ++
hw/arm/aspeed_ast27x0-tsp.c | 309
hw/arm/meson.build
if the `eth0` ISR is not
handled.
Signed-off-by: Steven Lee
Change-Id: Ic3609eb72218dfd68be6057d78b8953b18828709
---
hw/intc/aspeed_intc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 3fd417084f..f17bf43925 100644
--- a
help to review this patch at your convenience.
Best regards,
Steven Lee
Steven Lee (1):
hw/intc/aspeed: Fix IRQ handler mask check
hw/intc/aspeed_intc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--
2.43.0
o /dev/pts/52 (label serial1)
char device redirected to /dev/pts/53 (label serial2)
- serial0 is the console for the four Cortex-A35 primary processors,
serial1 and serial2 are the consoles for the two Cortex-M4 coprocessors.
- Connect to the consoles using a terminal emulator.
Signed-off-
59 matches
Mail list logo
