Public bug reported:
I an tried arm-aarch64 interrupt routing to EL3, by SCR_EL3.FIQ=1. First I am
started QEMU with secure=on and GICv3 support.
I programmed secure and non-secure timers and set-up appropriate
interrupts.Secure timer to be GRP1_Secure and non-secure timer to be
GRP1_NonSecure.
see possible solution, in #if 0 is original code in #else see possible
fix
static uint64_t icc_pmr_read(CPUARMState *env, const ARMCPRegInfo *ri)
#if 0 // KIURCHER: bug - shall be opposite; see ARM specification
if (value & 0x80) {
/* Secure priorities not visible to NS */
