This patch is trying to make qemu behave like real hardware. This is what
the OSs expect. The ability to create hardware that never existed and
can't
exist due to real hardware limitations is cool but it's not going to work
properly with existing OSs. At best you will have the OS never acces
Make these 3 error messages consistent with the other 20 in the same file.
diff -p -u -r1.79 sun4m.c
--- hw/sun4m.c 1 Jan 2008 20:57:25 - 1.79
+++ hw/sun4m.c 5 Jan 2008 22:26:07 -
@@ -385,7 +385,7 @@ static void sun4m_hw_init(const struct h
for(i = 0; i < smp_cpus; i++) {
Index: hw/eccmemctl.c
===
RCS file: /sources/qemu/qemu/hw/eccmemctl.c,v
retrieving revision 1.2
diff -p -u -r1.2 eccmemctl.c
--- hw/eccmemctl.c 1 Jan 2008 17:06:38 - 1.2
+++ hw/eccmemctl.c 6 Jan 2008 15:03:52 -000
Set limit bit when user timer expires.
Clear limit bit when user timer count set.
Set ptimer count when user timer count set.
Index: hw/slavio_timer.c
===
RCS file: /sources/qemu/qemu/hw/slavio_timer.c,v
retrieving revision 1.28
diff
Change ptimer limit only when mode changes.
Update timer configuration register user timer bits properly.
--- hw/slavio_timer.c.old 2008-01-22 21:35:33.0 -0500
+++ hw/slavio_timer.c 2008-01-22 21:36:13.0 -0500
@@ -198,10 +198,8 @@ static void slavio_timer_mem_writel(void
Add microSPARC II and turboSPARC mask ID register support.
Index: hw/iommu.c
===
RCS file: /sources/qemu/qemu/hw/iommu.c,v
retrieving revision 1.25
diff -p -u -r1.25 iommu.c
--- hw/iommu.c 1 Jan 2008 17:06:38 - 1.25
+++ hw/
Thiemo Seufer wrote:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer08/01/23 19:01:12
Modified files:
. : cpu-all.h cpu-exec.c qemu-doc.texi vl.c
Log message:
Add option to disable TB cache, by Herve Poussineau.
CVSWeb URLs:
htt
diff -p -u -r1.81 sun4m.c
--- hw/sun4m.c 17 Jan 2008 21:04:16 - 1.81
+++ hw/sun4m.c 24 Jan 2008 05:06:38 -
@@ -687,7 +687,7 @@ static const struct hwdef hwdefs[] = {
.dma_base = 0x7840,
.esp_base = 0x7880,
.le_base = 0x78c0,
-
Exactly which version of gcc is this? It appears to work fine with at
least some gcc 3 versions.
gcc (GCC) 3.2.2 20030222 (Red Hat Linux 3.2.2-5)
Standard Red Hat 9.
Blue Swirl wrote:
On 1/23/08, Robert Reif <[EMAIL PROTECTED]> wrote:
Change ptimer limit only when mode changes.
Update timer configuration register user timer bits properly.
The patch does not apply.
It should apply on top of the first user timer patch that is in CVS now.
Rediffed against cvs.
diff -p -u -r1.29 slavio_timer.c
--- hw/slavio_timer.c 25 Jan 2008 19:51:27 - 1.29
+++ hw/slavio_timer.c 25 Jan 2008 21:50:35 -
@@ -199,10 +199,8 @@ static void slavio_timer_mem_writel(void
count = ((uint64_t)s->counthigh << 32) | s->count;
Blue Swirl wrote:
On 1/24/08, Robert Reif <[EMAIL PROTECTED]> wrote:
diff -p -u -r1.81 sun4m.c
This breaks my tests, so I guess a fix is also needed for OpenBIOS.
Probably, they were tested using ss5/170 and ss10 openboot images.
Blue Swirl wrote:
On 1/25/08, Robert Reif <[EMAIL PROTECTED]> wrote:
Blue Swirl wrote:
On 1/24/08, Robert Reif <[EMAIL PROTECTED]> wrote:
diff -p -u -r1.81 sun4m.c
This breaks my tests, so I guess a fix is also needed for OpenBIOS.
Probabl
This patch gets openboot prom mmu register self tests passing for lx,
ss4, ss5 and ss10 prom images.
Index: target-sparc/cpu.h
===
RCS file: /sources/qemu/qemu/target-sparc/cpu.h,v
retrieving revision 1.61
diff -p -u -r1.61 cpu.h
---
Ryan Harper wrote:
> for qemu to pull in a new version of BOCHS to include with QEMU. Any
> chance of getting the latest BOCHS included so guests can use the new
> DMI table generation.
I could send you a newly build BIOS for testing.
Robert Riebisch
--
BTTR Software
http:/
Ryan Harper wrote:
> I've already built the latest BOCHS and tested it myself, what I'm
Oh, I see.
> looking for is what other testing and such needs to be done prior to
> getting QEMU to pull in a newer version of BOCHS.
Sorry, that nobody else seems to be interested. :
Jan Holzhueter wrote:
Hi everyone,
we are planing to get rid of some old sparc hardware.
The problem is that there are applications on it that require
sun4m and Solaris 1.1.2 / SunOS 4.1.4.
As known qemu-system-sparc is not able to boot the Solaris Kernel at
the moment.
I get as far as:
[spar
Andrew Warkentin wrote:
SunOS might run in TME (http://people.csail.mit.edu/fredette/tme/). I
don't think anything other than Linux runs in QEMU's Sun emulation (or
for that matter, any of the non-PC QEMU emulators).
Unfortunately TME only emulates a SPARCstation2 (sun4c).
I have only bee
Show which CPU IRQ is actually being set or reset when debugging.
diff -p -u -r1.86 sun4m.c
--- hw/sun4m.c 2 Mar 2008 08:48:47 - 1.86
+++ hw/sun4m.c 3 Mar 2008 00:35:29 -
@@ -258,12 +258,15 @@ void cpu_check_irqs(CPUState *env)
int old_interrupt = env->interrupt_in
Remove unneeded qemu_irq_lower because user mode timers don't support
IRQs and the IRQ is lowered when switching to user mode.
diff -p -u -r1.30 slavio_timer.c
--- hw/slavio_timer.c 26 Jan 2008 09:13:46 - 1.30
+++ hw/slavio_timer.c 3 Mar 2008 00:35:28 -
@@ -192,7 +192,6 @@ static
Fix microSPARC II SFSR mask.
diff -p -u -r1.96 translate.c
--- target-sparc/translate.c5 Mar 2008 17:59:48 - 1.96
+++ target-sparc/translate.c6 Mar 2008 02:15:30 -
@@ -4259,7 +4259,7 @@ static const sparc_def_t sparc_defs[] =
.mmu_bm = 0x4000,
.mmu_ctpr
Hi,
Shouldn't /usr/bin/qemu be an alias for qemu-system-$(ARCH), where $(ARCH) is
the native architecture? Defaulting to i386 doesn't make much sense nowadays,
specially since x86_64 is gradually obsoleting it.
See attached patch.
--
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My spam trap is [EMAIL PROTEC
This appears to be a remnant of when kqemu was non-free. It broke build
for me (not sure under which conditions it can be reproduced, but the fix
is obvious, see the patch).
--
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My spam trap is [EMAIL PROTECTED] Note: this address is only intended
for spam harvesters. Writing
ferent (specially if you have setup kqemu which only works with
qemu-system-x86_64).
--
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My spam trap is [EMAIL PROTECTED] Note: this address is only intended
for spam harvesters. Writing to it will get you added to my black list.
It's been a few months since I comipled from source so I
just tried with current CVS and got these errors on RH9:
/home/wine/qemu/linux-user/syscall.c: In function `sys_tgkill':
/home/wine/qemu/linux-user/syscall.c:170: `__NR_tgkill' undeclared
(first use in this function)
/home/wine/qemu/linux-
I'm trying to use sparc32 on linux i686 RH9 and am unable to
to get this working with current CVS. My old scripts that
didn't set any networking options no longer work. When
running a debian sparc netinst cd the setup finds a dhcp
connection but is unable to connect to the internet.
Adding -use
I'm trying to run a real ss10 openboot prom image rather than
the supplied prom image and found some issues with the way
counters and timers are implemented. It appears that the processor
and system counter/timers are not independent. The system
config register actually configures the processor
With the patch and ss10 boot prom I get:
TIMER: write 000ff13c
TIMER: write 000ff1310010 0001
TIMER: write 000ff130
TIMER: write 000ff134
TIMER: write 000ff13c 0001
TIMER: write 000ff130
TIMER: write 000ff
Increase size of PROM to match actual hardware.
Index: hw/sun4m.c
===
RCS file: /sources/qemu/qemu/hw/sun4m.c,v
retrieving revision 1.50
diff -p -u -r1.50 sun4m.c
--- hw/sun4m.c 24 Sep 2007 19:44:09 - 1.50
+++ hw/sun4m.c 30
Sparc32 CVS exits after illegal instruction trap.
[H[JNvram id QEMU_BIOS, version 1, machine id 0x80
CPUs: 1
Welcome to OpenBIOS v1.0RC1 built on Aug 11 2007 08:00
Type 'help' for detailed information
[sparc] Kernel already loaded
qemu: fatal: Trap 0x02 while interrupts disabled, Error state
Add support to sparc for loading a real bios image.
Index: hw/sun4m.c
===
RCS file: /sources/qemu/qemu/hw/sun4m.c,v
retrieving revision 1.52
diff -p -u -r1.52 sun4m.c
--- hw/sun4m.c 5 Oct 2007 13:08:35 - 1.52
+++ hw/sun4m.
Some more user timer fixes.
Index: hw/slavio_timer.c
===
RCS file: /sources/qemu/qemu/hw/slavio_timer.c,v
retrieving revision 1.17
diff -p -u -r1.17 slavio_timer.c
--- hw/slavio_timer.c 6 Oct 2007 11:28:21 - 1.17
+++ hw/s
PPC compiling has been broken for me in CVS for a few days and is
getting worse.
I'm running Red Hat 9.
make -C i386-linux-user all
make[1]: Entering directory `/home/wine/qemu/i386-linux-user'
make[1]: Nothing to be done for `all'.
make[1]: Leaving directory `/home/wine/qemu/i386-linux-user'
mak
I'm trying to add SuperSparc II MXCC support and need some feedback.
Is there a better way to read and write physical memory in 64bit chunks?
I'm not sure what I'm doing is portable between 32/64 and big/little endian.
Index: hw/sun4m.c
Blue Swirl wrote:
On 10/13/07, Robert Reif <[EMAIL PROTECTED]> wrote:
I'm trying to add SuperSparc II MXCC support and need some feedback.
Is there a better way to read and write physical memory in 64bit chunks?
I'm not sure what I'm doing is portable between 32/64
Updated patch base of feedback.
This patch adds SuperSparc MXCC support.
DPRINTF_MMU and DPRINTF_MXCC added.
I decided not to use do_unassigned_access() at this time because I don't
know what real hardware does.
Index: hw/sun4m.c
=
Use stq_* for 64 bit stores.
This fixes one bug where T1 was used twice rather than T1 and T2.
Should the address be 64 bit alligned? i.e. T0 & ~7 rather than T0 & ~3?
Should these unaligned address cause traps?
Index: target-sparc/op_helper.c
=
Blue Swirl wrote:
On 10/14/07, Robert Reif <[EMAIL PROTECTED]> wrote:
Should the address be 64 bit alligned? i.e. T0 & ~7 rather than T0 & ~3?
Should these unaligned address cause traps?
Yes, but the checks are already generated from translate.c
(gen_op_check_align_T0
Hi,
there is a new book about QEMU (in German):
http://qemu-buch.de/
Sorry for this advertising.
Robert Warnke
smime.p7s
Description: S/MIME Cryptographic Signature
The sysctrl register is actually 32 bits. Add code to access it as 32 bits.
Index: hw/slavio_misc.c
===
RCS file: /sources/qemu/qemu/hw/slavio_misc.c,v
retrieving revision 1.10
diff -p -u -r1.10 slavio_misc.c
--- hw/slavio_misc.c
Please use this version. The previous version didn't mask off the top
address bit.
The sysctrl register is actually 32 bits. Add code to access it as 32
bits.
Index: hw/slavio_misc.c
===
RCS file: /sources/qemu/qemu/hw/slavio_
I'm looking at adding more complete support for different sparc32
CPUs, MMUs, cache controllers and systems.
Each CPU/MMU/cache controller combination is slightly different and
requires its own unique state. For example the two CPUs currently
supported save the boot mode in different bits in th
This patch adds CPU dependent boot mode flag support.
Different CPUs use different bits for the boot mode flag. The constant
MMU_BM is replaced with a variable which is set for the selected CPU.
This patch also removes the MMU flags from being saved in the
translation block code as a result of
This patch also performs a CPU reset after the CPU is registered rather
than before.
Why is this change needed?
Reset should be doing CPU dependent stuff and the CPU dependent setup
is performed when the CPU is registered.
This patch makes debugging asi and mxcc accesses easier to follow.
Index: target-sparc/op_helper.c
===
RCS file: /sources/qemu/qemu/target-sparc/op_helper.c,v
retrieving revision 1.51
diff -p -u -r1.51 op_helper.c
--- target-sparc/op_
Blue Swirl wrote:
DPRINTF_ASI would be nice.
Here is a revised patch:
Index: target-sparc/op_helper.c
===
RCS file: /sources/qemu/qemu/target-sparc/op_helper.c,v
retrieving revision 1.51
diff -p -u -r1.51 op_helper.c
--- targe
Add iommu version to sparc32. Also reset iommu after initialization.
Index: hw/iommu.c
===
RCS file: /sources/qemu/qemu/hw/iommu.c,v
retrieving revision 1.17
diff -p -u -r1.17 iommu.c
--- hw/iommu.c 6 Oct 2007 11:28:21 - 1
This patch fixes the word order for 64 bit reads of the mxcc registers.
It returns the high 32 bits in ret and the lower 32 bits in T0 just
like other places in the same function.
T0 is defined as: register uint32_t T0 asm(AREG1);
T0 on my machine has a sizeof = 4. Because of this, I don't thi
Add iommu version to sparc32. Also reset iommu after initialization.
Should the version be tied to CPU model instead of machine type? At
least for Turbosparc this seems to be the case.
On SMP systems the IOMMU is on the system board in a separate ASIC. On
single CPU systems the IOM
This patch fixes the word order for 64 bit reads of the mxcc registers.
Index: target-sparc/op_helper.c
===
RCS file: /sources/qemu/qemu/target-sparc/op_helper.c,v
retrieving revision 1.52
diff -p -u -r1.52 op_helper.c
--- targ
Fix MXCC error register bit clearing.
Index: target-sparc/op_helper.c
===
RCS file: /sources/qemu/qemu/target-sparc/op_helper.c,v
retrieving revision 1.52
diff -p -u -r1.52 op_helper.c
--- target-sparc/op_helper.c11 Nov 2007 19:46
Add new MXCC register.
Index: target-sparc/op_helper.c
===
RCS file: /sources/qemu/qemu/target-sparc/op_helper.c,v
retrieving revision 1.52
diff -r1.52 op_helper.c
209a210,217
> case 0x01c00c00: /* Module reset register */
>
Remove unnecessary masking of lower word with 0x.
Index: target-sparc/op_helper.c
===
RCS file: /sources/qemu/qemu/target-sparc/op_helper.c,v
retrieving revision 1.52
diff -p -u -r1.52 op_helper.c
--- target-sparc/op_helper.c
Blue Swirl wrote:
On 11/16/07, Robert Reif <[EMAIL PROTECTED]> wrote:
This patch fixes the word order for 64 bit reads of the mxcc registers.
Otherwise everything seems OK, but it breaks NetBSD version 3 on SS10:
clock0 at obio0 slot 0 offset 0x20: mk48t08
timer0 at obio
Blue Swirl wrote:
On 11/18/07, Robert Reif <[EMAIL PROTECTED]> wrote:
Blue Swirl wrote:
On 11/16/07, Robert Reif <[EMAIL PROTECTED]> wrote:
This patch fixes the word order for 64 bit reads of the mxcc registers.
Otherwise everything seems OK, b
This patch adds support for some more MMU registers:
0x10 TLB replacement control
0x13 read/write access to 0x03 SFSR
0x14 read/write access to 0x04 SFAR
Only support for 1 real register was added (0x10) but 16 were added
to CPUSPARCState because we don't check for invalid register
Set initial value of AFSR register properly.
Index: hw/iommu.c
===
RCS file: /sources/qemu/qemu/hw/iommu.c,v
retrieving revision 1.19
diff -p -u -r1.19 iommu.c
--- hw/iommu.c 17 Nov 2007 17:14:42 - 1.19
+++ hw/iommu.c 21 No
Blue Swirl wrote:
http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/helper.c?cvsroot=qemu&r1=1.30&r2=1.31
Could you please set the mask to 0x7 for 512k proms.
This patch sets the maximum number of CPUs and memory to what is
supported by the actual hardware.
Index: hw/sun4m.c
===
RCS file: /sources/qemu/qemu/hw/sun4m.c,v
retrieving revision 1.66
diff -p -u -r1.66 sun4m.c
--- hw/sun4m.c 2 De
If a sun system is booted without a keyboard, it uses serial port A for
the console.
This patch disables (unplugs) the keyboard when -nographic is set on the
command line.
Another option would be to add a -nokeyboard option to the command line.
Index: hw/slavio_serial.c
===
Blue Swirl wrote:
On 12/3/07, Robert Reif <[EMAIL PROTECTED]> wrote:
This patch sets the maximum number of CPUs and memory to what is
supported by the actual hardware.
While it's not historically accurate to emulate a Sparcstation 5 with
16 CPUs and 2 gigabytes of memory,
Blue Swirl wrote:
On 12/4/07, Robert Reif <[EMAIL PROTECTED]> wrote:
I would be surprised if an SMP kernel actually worked on a multi CPU SS5.
Prepare for a surprise:
That's interesting because the fact that it works shows how inaccurate
the emulation is.
Now could
* QEMU Sparc Sun4m ECC memory controller emulation
+ *
+ * Copyright (c) 2007 Robert Reif
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without re
diff -p -u -r1.60 op_helper.c
--- target-sparc/op_helper.c28 Nov 2007 18:08:28 - 1.60
+++ target-sparc/op_helper.c9 Dec 2007 20:33:02 -
@@ -411,6 +411,9 @@ void helper_ld_asi(int asi, int size, in
break;
}
break;
+case 0x39: /* data cache di
Index: vl.c
===
RCS file: /sources/qemu/qemu/vl.c,v
retrieving revision 1.377
diff -p -u -r1.377 vl.c
--- vl.c6 Dec 2007 22:11:20 - 1.377
+++ vl.c10 Dec 2007 01:17:59 -
@@ -7838,6 +7838,7 @@ static void
Writing data to a serial port on the sparc emulation happens immediately.
I would like to throttle the write speed to match the actual baud rate.
What's the best way to do this in qemu? Will QEMUTimer work for a
1 millisecond timer?
Blue Swirl wrote:
On 12/10/07, Robert Reif <[EMAIL PROTECTED]> wrote:
Writing data to a serial port on the sparc emulation happens immediately.
I would like to throttle the write speed to match the actual baud rate.
What's the best way to do this in qemu? Will QEMUTimer w
Robert Reif wrote:
The problem I'm having is with sparc32 using a sun openboot image in
nographics mode where the prom uses serial port A as the system console.
The serial port output shows up in the host terminal window that qemu
was started in.
Characters written to serial port A ar
Robert Reif wrote:
Characters written to serial port A are not reliably making it to the
screen.
Turning on serial debugging shows that the characters are written to the
serial port. The characters do make it to the screen when debugging.
The problem seems to be caused by multiple streams
It seems qemu-forum.ipi.fi is down. Is there an alternate place one
can obtain source snapshots or browse the user forums?
Hi,
we are developing an x86 application that we are testing using qemu and
are having some issues with the PIT clock count. We are using PIT clock
count as a reference to measure cpu frequency:
wait_wrap()
a=read_current_cycles()
wait_wrap()
b=read_current_cycles()
calculate_freq(a,b)...
The pr
didn't test it, since I don't have a x86_64 box to play with).
Please cc me in any replies - I'm not subscribed to the list.
Regards,
Robert
diff -urN linux-2.6.16/drivers/char/Kconfig linux-2.6.16-qemu/drivers/char/Kconfig
--- linux-2.6.16/drivers/char/Kconfig 2006-03-20 06:53:29.
).
Is this a known bug? I couldnt find any information on that.
Regards,
Robert
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just thought to report this if it's unknown. If you need any more
information just let me know.
Anyway - great work! (:
Regards,
Robert
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Hi,
just wanted to note that FreeBSD (6.1 at least) works with user and
kernel virtualization - at least on a linux host.
Maybe it should be added to
http://fabrice.bellard.free.fr/qemu/kqemu-doc.html#SEC6 and #SEC7.
Regards,
Robert
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Original Message
Subject: Re: [Qemu-devel] qcow2 issues on freebsd
Date: Thu, 10 Aug 2006 12:23:30 +0200
From: Robert Annessi <[EMAIL PROTECTED]>
To: Fabrice Bellard <[EMAIL PROTECTED]>
References: <[EMAIL PROTECTED]> <[EMAIL PROTECTED]>
On 08/09/06 23:3
an already installed version of windows xp results in "random"
memory access errors.
Another user having the same issues:
http://qemu.dad-answers.com/viewtopic.php?p=6748#6748
Regards,
Robert
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On 08/10/06 13:07, Robert Annessi wrote:
> user virtualization works well with windows 2000 and windows xp guests,
> but kernel virtualization doesnt (on a linux host using
> qemu-0.8.2|qemu-cvs with kqemu-1.3.0-pre9).
>
> Trying to install results in a bl
On 08/09/06 23:02, Robert Annessi wrote:
> although it's not yet released, I tried the qcow2 format on some OSes.
> Linux, Windowx XP and OpenBSD worked quite well, but I had a
> reproduceable issue with FreeBSD:
> qemu segfaults when creating a snapshot. Afterwards the disk i
pt it for
x86_64. If someone is interested in it and not able to do it himself I
could provide an updated patch (but I dont have a x86_64 box here, so I
can not test it).
Please cc me in any replies, since I'm not subscribed to the list.
Regards,
Robert
diff -urN linux-2.6.16-ra8/arch/i3
On 09/24/06 01:23, Mihamina Rakotomandimby wrote:
> I am looking for an explanation about kqemu is not free.
It is free (as in beer), but not open source.
Read the faq:
http://kidsquid.com/cgi-bin/moin.cgi/FrequentlyAskedQuestions#head-7550ed5498dedce0f1b9a50dd47e490db719b76e
Regards,
Rob
.
The solution for me was/is to disable acpi for this guest.
Regards,
Robert
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Please can you apply this tiny patch to make /dev/kqemu open failures more
verbose?
It'll help the user distinguish between ENOENT, EPERM and ENXIO, since they
are all common causes of open failure.
--
Robert Millan
My spam trap is [EMAIL PROTECTED] Note: this address is only intende
I asked this in the user group but didn't get an answer, so I figured
I would try here.
I've tried qemu 7.0, 7.1 and today's CVS under Ubuntu Hoary. I've
tried a few CD Linux distributions such as Damn Small Linux, Puppy
Linux, MEPIS and others. In all of the the mouse is stuck in the
centre of
./qvm86/qvm86.ko: ELF 32-bit LSB relocatable, Intel 80386, version 1 (SYSV),
not stripped
I'm using Debian GNU/Linux unstable with kernel-headers-2.6.11-1-k7.
Any idea what's going on?
--
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Bakul Shah wrote:
The three I am aware of are: openbsd, netbsd & plan9. They
work fine with -no-kqemu flag. This is under freebsd but
I believe the same thing happens under linux.
The easiest test case may be plan 9 it seems to dies very
early. Download the plan9 .iso from one of
http://w
On Fri, 2022-11-11 at 10:47 -0500, Emanuele Giuseppe Esposito wrote:
> This API allows the accelerators to prevent vcpus from issuing
> new ioctls while execting a critical section marked with the
> accel_ioctl_inhibit_begin/end functions.
>
> Note that all functions submitting ioctls must mark wh
On Fri, 2022-11-11 at 10:47 -0500, Emanuele Giuseppe Esposito wrote:
> Using the new accel-blocker API, mark where ioctls are being called
> in KVM. Next, we will implement the critical section that will take
> care of performing memslots modifications atomically, therefore
> preventing any new ioc
On Fri, 2022-12-02 at 13:03 +0100, Emanuele Giuseppe Esposito wrote:
...
> > > @@ -3032,7 +3035,9 @@ int kvm_vcpu_ioctl(CPUState *cpu, int type,
> > > ...)
> > > va_end(ap);
> > >
> > > trace_kvm_vcpu_ioctl(cpu->cpu_index, type, arg);
> > > +accel_cpu_ioctl_begin(cpu);
> >
> > Does
On Thu, 2022-07-21 at 10:58 +0200, Igor Mammedov wrote:
[...]
Thanks Igor for review.
> > > The patch it is too intrusive and my hunch is that it breaks
> > > ABI and needs a bunch of compat knobs to work properly and
> > > that I'd like to avoid unless there is not other way around
> > > the probl
And initialize buffer_is_zero() with it, when Intel AVX512F is
available on host.
This function utilizes Intel AVX512 fundamental instructions which
perform over previous AVX2 instructions.
Signed-off-by: Robert Hoo
---
include/qemu/cpuid.h | 3 +++
util/bufferiszero.c | 56
1. Add avx512_opt option and enable it when host has the ability
2. Implement new buffer_zero_avx512() with AVX512F instructions
Robert Hoo (2):
configure: add configure option avx512f_opt
util: add function buffer_zero_avx512()
configure| 39
-programming-reference.pdf
Signed-off-by: Robert Hoo
---
configure | 39 +++
1 file changed, 39 insertions(+)
diff --git a/configure b/configure
index 115dc38..9bf8de0 100755
--- a/configure
+++ b/configure
@@ -1382,6 +1382,11 @@ for opt do
;;
--enable-avx2
On Thu, 2020-02-13 at 11:30 +0100, Paolo Bonzini wrote:
> On 13/02/20 08:52, Robert Hoo wrote:
> > +
> > +}
> > +#pragma GCC pop_options
> > +#endif
> > +
> > +
> > /* Note that for test_buffer_is_zero_next_accel, the most
> > prefer
On Fri, 14 Feb 2020 at 11:54, Alex Bennée wrote:
> > from socket_thread import SocketThread
> > +import yaml
>
> So this throws my setup on my Gentoo SynQuacer. Is this meant to be in
> the standard library or is this a separate dependency?
>
This is a separate dependency. On Ubuntu the package
On Thu, 13 Feb 2020 at 17:51, Alex Bennée wrote:
>
> Otherwise any -D settings the user may have made get ignored.
>
> Signed-off-by: Alex Bennée
Reviewed-by: Robert Foley
On Thu, 13 Feb 2020 at 18:00, Alex Bennée wrote:
>
> Pointer authentication isn't perfect so measure the percentage of
> failed checks. As we want to vary the pointer that is authenticated we
> recurse down the stack.
>
> Signed-off-by: Alex Bennée
Reviewed-by: Robert Foley
em.
>
> This drops opcode from the ctx in favour if passing the appropriately
> sized opcode down a few levels of the decode.
>
> Signed-off-by: Alex Bennée
> Reviewed-by: Richard Henderson
Reviewed-by: Robert Foley
On Thu, 13 Feb 2020 at 17:51, Alex Bennée wrote:
>
> If we have plugins enabled we still need to have built the test to be
> able to run it.
>
> Signed-off-by: Alex Bennée
Reviewed-by: Robert Foley
This method was located in both centos and ubuntu.i386.
Signed-off-by: Robert Foley
Reviewed-by: Alex Bennée
Reviewed-by: Peter Puhov
---
tests/vm/basevm.py | 40
tests/vm/centos | 33 +
tests/vm/ubuntu.i386 | 37
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