Hello,
I am trying to count the number of barrier instructions (dmb) which are being
executed in an multi-threaded ARM executable. I am running the executable using
qemu user mode with the following patch applied.
Basically I created two counters in the ARM cpu state and incrementing them by
gene
Hi Max,
On Wed, Oct 15, 2014 at 9:54 PM, Max Filippov wrote:
> Hi,
>
> On Thu, Oct 16, 2014 at 5:45 AM, Pranith Kumar wrote:
>> Is there something obviously wrong with what I am trying to do? Any help is
>> highly appreciated.
>> --- a/target-arm/translate.c
>
Hi Peter,
On Thu, Oct 16, 2014 at 4:05 AM, Peter Maydell wrote:
> On 16 October 2014 03:45, Pranith Kumar wrote:
>> The problem I am facing is that this seems to be crashing when run with a
>> multi-threaded executable.
>
> This is nothing to do with your changes -- us
On Wed, Oct 15, 2014 at 10:12 PM, Max Filippov wrote:
> On Thu, Oct 16, 2014 at 6:00 AM, Pranith Kumar wrote:
>>>> +tcg_gen_add_i32(cpu_fence_count, cpu_fence_count, 1);
>>>
>>> tcg_gen_addi_i32, as you're adding an immediate.
>>> Enabling
On Thu, Oct 1, 2015 at 12:21 PM, Christopher Covington
wrote:
>
> Are you using KVM or TCG (are you running on an x86 host or an arm64 host)?
I am using TCG, aarch64-softmmu on x86 host.
>
> We have published some patches implementing the PMU registers and instruction
> counting (but not any oth
Hi Dave,
Commit 334e580a6f97 ("fs: XFS_IOC_FS[SG]SETXATTR to
FS_IOC_FS[SG]ETXATTR promotion") breaks building latest qemu as
follows:
In file included from /usr/include/xfs/xfs.h:58:0,
from /home/pranith/qemu/block/raw-posix.c:96:
/usr/include/xfs/xfs_fs.h:42:8: error: redefiniti
Hi,
On Wed, Nov 18, 2015 at 11:48 AM, Hao Bai wrote:
> Sorry about the ambiguity.
> I am using x86-64 architecture in user mode. Basically, I am trying to log
> all the cache activities when I run a guest program with QEMU. That's why I
> asked whether QEMU simulated CPU caches. I was assuming i
On Wed, Nov 18, 2015 at 1:06 PM, Eduardo Habkost wrote:
>
>
> Interesting. How much did you change QEMU to make this work? Have
> you been rebasing this to recent QEMU versions often?
The core of qemu is not changed except for one TCG issue I didn't know
how to fix. Rest is just annotating the c
Hello,
I am interested in working on a portion of the MTTCG project as part
of GSoC 2016. I am writing to ask for guidance in creating a formal
proposal.
On IRC, Alex suggested a project to support proper modelling of memory
consistency between different host and guest architectures. This, I
thin
Hi Alex,
On Tue, Jan 12, 2016 at 12:29 PM, Alex Bennée
wrote:
>
https://github.com/stsquad/qemu/tree/mttcg/multi_tcg_v8_wip_ajb_fix_locks
>
I built this branch and ran an arm64 guest. It seems to be failing
similarly to what I reported earlier:
#0 0x72211cc9 in __GI_raise (sig=sig@ent
Hi Alex,
On Fri, Jan 15, 2016 at 8:53 AM, Alex Bennée wrote:
> Can you try this branch:
>
>
https://github.com/stsquad/qemu/tree/mttcg/multi_tcg_v8_wip_ajb_fix_locks-r1
>
> I think I've caught all the things likely to screw up addressing.
>
I tried this branch and the boot hangs like follows:
[
icount sleep takes on or off as options. A few places mention sleep=no
which is not accepted. This patch corrects them.
Signed-off-by: Pranith Kumar
---
cpus.c | 4 ++--
qemu-options.hx | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/cpus.c b/cpus.c
index
icount sleep takes on or off as options. A few places mention sleep=no
which is not accepted. This patch corrects them.
Signed-off-by: Pranith Kumar
---
cpus.c | 4 ++--
qemu-options.hx | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/cpus.c b/cpus.c
index
Signed-off-by: Pranith Kumar
---
cpus.c | 4 ++--
qemu-options.hx | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/cpus.c b/cpus.c
index 9592163..bc774e2 100644
--- a/cpus.c
+++ b/cpus.c
@@ -630,7 +630,7 @@ void configure_icount(QemuOpts *opts, Error **errp
o '-d' option because of which monitor dumps
the logs to stderr.
Fix this by opening the log file when '-D' is specified on the command line.
Also fix an ancient comment which does not hold true since changing location and
log level has now been streamlined.
Signed-off-by: Pra
Hi,
I occasionally get the following crash while running an AArch64 softmmu on
an x86-64 system. I am using version 2.2 and cannot update to the latest
version. Did anyone else see this happening? If this is fixed, I would love
to get the patch backported.
Thanks!
Program received signal SIGSEGV
On Wed, Jul 15, 2015 at 4:28 PM, Peter Maydell
wrote:
> Googling suggests "qsim" is "a project which aims, as part of the
> Manifold simulation effort at Georgia Tech, to create a thread safe
> multicore emulation library based on the QEMU emulator".
>
> My immediate guess is that this is buggy a
Hello Paolo,
I have a question reg. tcg_cpu_exec(cpu) which is called from tcg_exec_all().
tcg_cpu_exec() is called for each cpu in a loop. I observed that this
call does not always execute TBs on that particular CPU. It return
because the exit_request is set.
I am trying to understand what scen
Hi Alex,
I have one question inline below.
Alex Bennée writes:
> The __atomic primitives have been available since GCC 4.7 and provide
> a richer interface for describing memory ordering requirements. As a
> bonus by using the primitives instead of hand-rolled functions we can
> use tools such
On Sun, Apr 3, 2016 at 9:50 AM, Marwa Hamza wrote:
> hello , i tried to run qemu on x64 system ,
>
> those are steps that i followed
> i compile the kernel 4.4.1 with arch =i386
> i download busybox 1.21.0
> make ARCH=i386 menuconfig
> I checked the option to compile Busybox as a static executable
On Sun, Apr 3, 2016 at 9:50 AM, Marwa Hamza wrote:
> ./i386-softmmu/qemu-system-i386 -M pc -kernel
> /home/marwa/Bureau/lauterbach/i386_qemu/linux-4.1.18/arch/i386/boot/bzImage
> -initrd /home/marwa/Bureau/lauterbach/i386_qemu/busybox-1.21.0/rootfs.img.gz
> -append “root=/dev/ram rdinit=/sbin/ini
On Sun, Apr 3, 2016 at 3:49 PM, Marwa Hamza wrote:
> the output of this command > ./i386-softmmu/qemu-system-i386 -M pc -kernel
>>
>> /home/marwa/Bureau/lauterbach/i386_qemu/linux-4.1.18/arch/i386/boot/bzImage
>> -initrd
>> /home/marwa/Bureau/lauterbach/i386_qemu/busybox-1.21.0/rootfs.img.gz
>> -
Hi Paolo,
On Mon, Apr 4, 2016 at 4:14 AM, Paolo Bonzini wrote:
>
> The issue is that atomic_thread_fence() only affects other atomic
> operations, while smp_rmb() and smp_wmb() affect normal loads and stores
> as well.
That is different from what I understand what atomic_thread_fence()
does. AFA
On Mon, Apr 4, 2016 at 1:03 PM, Paolo Bonzini wrote:
>>
>> Quoting
>> http://www.inf.pucrs.br/~flash/progeng2/cppreference/w/cpp/atomic/atomic_thread_fencehtml.html:
>>
>> "Establishes memory synchronization ordering of non-atomic and relaxed
>> atomic accesses"
>
> You can find some information
Add a missing end brace and update doc to point to the latest access
macro. ACCESS_ONE() is deprecated.
Signed-off-by: Pranith Kumar
---
docs/atomics.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/atomics.txt b/docs/atomics.txt
index ef285e3..bba771e 100644
On Tue, Apr 12, 2016 at 7:42 AM, Marc-André Lureau
wrote:
> Hi
>
> On Mon, Apr 11, 2016 at 7:30 PM, Pranith Kumar wrote:
>> Add a missing end brace and update doc to point to the latest access
>> macro. ACCESS_ONE() is deprecated.
>
> ONE/ONCE
Right, I missed this o
On Tue, Apr 12, 2016 at 5:20 PM, Paolo Bonzini wrote:
> FWIW I'll be mostly offline this week and on vacation starting from the
> next, so it's probably best if you send the patch at the beginning of
> May. It will be fixed _and_ act as a reminder. :)
Sure, I will do so in May.
--
Pranith
Add a missing end brace and update doc to point to the latest access
macro. ACCESS_ONCE() is deprecated.
Signed-off-by: Pranith Kumar
---
docs/atomics.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/atomics.txt b/docs/atomics.txt
index ef285e3..bba771e 100644
On Wed, May 25, 2016 at 3:25 PM, Alex Bennée wrote:
> Should we make the emitting of the function call/TCGop conditional on
> MTTCG being enabled? If we are running in round-robin mode there is no
> need to issue any fence operations.
>
Also, we should check if SMP(> 1 processors) is enabled sinc
On Wed, May 25, 2016 at 3:43 PM, Sergey Fedorov wrote:
>
> I think it would better not to defer native support for the operation.
> It should be relatively simple instruction. Otherwise we could wind up
> deferring this indefinitely.
>
Agreed. I will go with the native generation for now.
Thanks
Hi Richard,
Thank you for the helpful comments.
On Wed, May 25, 2016 at 1:35 PM, Richard Henderson wrote:
> On 05/24/2016 10:18 AM, Pranith Kumar wrote:
>> diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
>> index 92be341..93ea42e 100644
>> --- a/tcg/i386/tcg-
On Thu, May 26, 2016 at 9:00 PM, Richard Henderson wrote:
> This is a reorg of Pranith's first patch set, correcting a few
> mistakes and adding backend support for all of the other hosts.
>
> In addition, I added front-end support for Alpha, since I didn't
> actually have any armv7 images handy t
On Fri, May 27, 2016 at 10:20 AM, Sergey Fedorov wrote:
+case INDEX_op_fence:
+smp_mb();
+break;
default:
TODO();
break;
>>> A bit of bike-shedding. While there's no common ISA term for "memory
>>> bar
Sergey Fedorov writes:
> On 27/05/16 04:00, Richard Henderson wrote:
>> diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
>> index 6d0410c..b772d90 100644
>> --- a/tcg/tcg-opc.h
>> +++ b/tcg/tcg-opc.h
>> @@ -42,6 +42,8 @@ DEF(br, 0, 0, 1, TCG_OPF_BB_END)
>> # define IMPL64 TCG_OPF_64BIT
>> #endif
>>
Hi Sergey,
Sergey Fedorov writes:
> On 27/05/16 04:00, Richard Henderson wrote:
>> diff --git a/tci.c b/tci.c
>> index b488c0d..53b3f71 100644
>> --- a/tci.c
>> +++ b/tci.c
>> @@ -1236,6 +1236,9 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t
>> *tb_ptr)
>> tcg_abort()
Hi Alvise,
On Thu, May 26, 2016 at 12:35 PM, Alvise Rigo
wrote:
> Add tcg_exclusive_{lock,unlock}() functions that will be used for making
> the emulation of LL and SC instructions thread safe.
>
> Signed-off-by: Alvise Rigo
> +__thread bool cpu_have_exclusive_lock;
> +QemuSpin cpu_exclusive_
Signed-off-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
tcg/ppc/tcg-target.inc.c | 8
1 file changed, 8 insertions(+)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 1039407..45a667f 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
Signed-off-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
tcg/mips/tcg-target.inc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index b2a839a..fc9c7fb 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg
Hello,
The following series adds fence instruction generation support to
TCG. The current work has been rebased on-top of Richard's patch
series.
This has been tested and confirmed to fix ordering issues on a x86
host with MTTCG enabled ARMv7 guest using KVM unit tests.
Pranith Kuma
We need to generate fence instructions only for SMP MTTCG guests. This
patch enforces that.
Signed-off-by: Pranith Kumar
---
tcg/tcg-op.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index a6f01a7..eeb0d0c 100644
--- a/tcg/tcg-op.c
+++ b
Cc: Aurelien Jarno
Signed-off-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
tcg/ia64/tcg-target.inc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/tcg/ia64/tcg-target.inc.c b/tcg/ia64/tcg-target.inc.c
index 261861f..88cc560 100644
--- a/tcg/ia64/tcg-target.inc.c
+++ b/tcg
This commit introduces the TCGOpcode for memory barrier instruction.
This opcode takes an argument which is the type of memory barrier
which should be generated.
Signed-off-by: Pranith Kumar
Signed-off-by: Richard Henderson
---
tcg/README| 17 +
tcg/tcg-op.c | 6
Signed-off-by: Pranith Kumar
Signed-off-by: Richard Henderson
---
target-arm/translate.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index c946c0e..e1b16c0 100644
--- a/target-arm/translate.c
+++ b/target-arm
Cc: Andrzej Zaborowski
Cc: Peter Maydell
Signed-off-by: Pranith Kumar
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.inc.c | 12
1 file changed, 12 insertions(+)
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index a914762..e88d8ce 100644
--- a/tcg/arm
Signed-off-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
target-alpha/translate.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 5b86992..17b68f5 100644
--- a/target-alpha/translate.c
+++ b/target-alpha
Generate mfence instruction on SSE2 enabled processors. For older
processors, generate a 'lock orl $0,0(%esp)' instruction which has
similar ordering semantics.
Signed-off-by: Pranith Kumar
[rth: Check for sse2, fallback to locked memory op otherwise.]
Signed-off-by: Richard Henderso
Added correct email for Sergey in CC.
I apologize for getting Sergey's email wrong. Please drop/correct his
email when replying to the patches in this series otherwise you will
see an email bounce.
On Tue, May 31, 2016 at 2:39 PM, Pranith Kumar wrote:
> Hello,
>
> The followi
Cc: Alexander Graf
Signed-off-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
tcg/s390/tcg-target.inc.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index e95b04b..b4f14bc 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b
Cc: Blue Swirl
Signed-off-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
tcg/sparc/tcg-target.inc.c | 8
1 file changed, 8 insertions(+)
diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c
index a611885..81f263f 100644
--- a/tcg/sparc/tcg-target.inc.c
+++ b
Cc: Stefan Weil
Signed-off-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
tcg/tci/tcg-target.inc.c | 3 +++
tci.c| 3 +++
2 files changed, 6 insertions(+)
diff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.inc.c
index 4e91687..a507ceb 100644
--- a/tcg/tci
Cc: Claudio Fontana
Signed-off-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
tcg/aarch64/tcg-target.inc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index 08efdf4..c361a5c 100644
--- a/tcg/aarch64/tcg
Hi Richard,
Thanks for the review. I will make the changes you pointed out. One point below:
On Tue, May 31, 2016 at 4:24 PM, Richard Henderson wrote:
> On 05/31/2016 11:39 AM, Pranith Kumar wrote:
>> +/* TCGOpmb args */
>> +#define TCG_MB_FULL ((TCGArg)(0))
>>
On Tue, May 31, 2016 at 4:27 PM, Richard Henderson wrote:
> On 05/31/2016 11:39 AM, Pranith Kumar wrote:
>>
>> +case INDEX_op_mb:
>> +tcg_out_mb(s);
>
>
> You need to look at the barrier type and DTRT. In particular, the Linux
> smp_rmb and smp
On Wed, Jun 1, 2016 at 5:17 PM, Richard Henderson wrote:
>
> Because x86 has a strong memory model.
>
> It does not require barriers to keep normal loads and stores in order. The
> primary reason for the *fence instructions is to order the "non-temporal"
> memory operations that are part of the S
Sergey Fedorov writes:
> On 31/05/16 21:39, Pranith Kumar wrote:
>> diff --git a/tcg/README b/tcg/README
>> index f4a8ac1..cfe79d7 100644
>> --- a/tcg/README
>> +++ b/tcg/README
>> @@ -402,6 +402,23 @@ double-word product T0. The later is return
On Thu, Jun 2, 2016 at 9:08 PM, Richard Henderson wrote:
> On 06/02/2016 02:37 PM, Sergey Fedorov wrote:
>>
>>
>> It would give us three TCG operations for each memory operation instead
>> of one. But then we might like to combine these barrier operations back
>> with memory operations in each bac
On Thu, Jun 2, 2016 at 5:18 PM, Richard Henderson wrote:
>
> Hum. That does seem helpful-ish. But I'm not certain how helpful it is to
> complicate the helper functions even further.
>
> What if we have tcg_canonicalize_memop (or some such) split off the barriers
> into separate opcodes. E.g.
>
Hi Alex,
On Fri, Jun 3, 2016 at 4:40 PM, Alex Bennée wrote:
> This is the third iteration of the RFC patch set which aims to provide
> the basic framework for MTTCG. There have been some considerable
> changes since the last extensive review (thanks to all the reviewers).
>
>- many updates to
On Thu, Jun 2, 2016 at 3:37 PM, Sergey Fedorov wrote:
> On 31/05/16 21:39, Pranith Kumar wrote:
>> Signed-off-by: Pranith Kumar
>> Signed-off-by: Richard Henderson
>> ---
>> target-arm/translate.c | 7 +--
>> 1 file changed, 5 insertions(+), 2 deletions
On Mon, Jun 6, 2016 at 11:49 AM, Sergey Fedorov wrote:
> On 06/06/16 18:47, Pranith Kumar wrote:
>> On Mon, Jun 6, 2016 at 11:44 AM, Sergey Fedorov wrote:
>>> On 03/06/16 21:27, Pranith Kumar wrote:
>>>> On Thu, Jun 2, 2016 at 5:18 PM, Richard Henderson
On Mon, Jun 6, 2016 at 11:44 AM, Sergey Fedorov wrote:
> On 03/06/16 21:27, Pranith Kumar wrote:
>> On Thu, Jun 2, 2016 at 5:18 PM, Richard Henderson wrote:
>>>
>>> What if we have tcg_canonicalize_memop (or some such) split off the barriers
>>> into separat
On Mon, Jun 6, 2016 at 12:14 PM, Sergey Fedorov wrote:
> On 06/06/16 18:58, Pranith Kumar wrote:
>> On Mon, Jun 6, 2016 at 11:49 AM, Sergey Fedorov wrote:
>>> On 06/06/16 18:47, Pranith Kumar wrote:
>>>> On Mon, Jun 6, 2016 at 11:44 AM, Sergey Fedorov
>&
On Mon, Jun 6, 2016 at 3:23 PM, Richard Henderson wrote:
> On 06/06/2016 10:11 AM, Pranith Kumar wrote:
>>
>> If I read it correctly TCG_BAR_SYNC is equivalent to OR of all the
>> other four barriers. I am not sure if we can just construct SYNC like
>> this or if we n
Hi Peter,
On Tue, May 10, 2016 at 6:11 AM, Peter Maydell wrote:
> The TCR_EL2 and TCR_EL3 regdefs wer incorrectly using the
> vmsa_tcr_el1_write function for writes. Since these registers don't
> have the A1 bit that TCR_EL1 does, we don't need to do a tlb_flush()
> when they are written. Remove
]
&& addr >> TARGET_VIRT_ADDR_SPACE_BITS == addr >> 63);
Fix it by replacing (addr >> 63) by '1' which is what it evaluates to
since addr is negative.
Signed-off-by: Pranith Kumar
---
target-alpha/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 de
On Thu, Jun 16, 2016 at 3:07 PM, Richard Henderson wrote:
> On 06/16/2016 11:56 AM, Pranith Kumar wrote:
>> Using gcc 6.1 for alpha-linux-user target we see the following build
>> error:
>>
>> /mnt/devops/code/qemu/target-alpha/translate.c: In function ‘in_superpage
Hi Richard,
On Tue, May 31, 2016 at 4:34 PM, Richard Henderson wrote:
> On 05/31/2016 11:39 AM, Pranith Kumar wrote:
>>
>> +/* System instructions. */
>> +DMB_ISH = 0xd5033bbf,
>
> ...
>>
>> +case INDEX_op_mb:
>> +tcg_out
On Thu, Jun 16, 2016 at 8:43 PM, Laurent Vivier wrote:
>
>
> Le 16/06/2016 à 21:15, Pranith Kumar a écrit :
>> On Thu, Jun 16, 2016 at 3:07 PM, Richard Henderson wrote:
>>> On 06/16/2016 11:56 AM, Pranith Kumar wrote:
>>>> Using gcc 6.1 for alpha-linux-us
On Fri, Jun 17, 2016 at 2:09 PM, Richard Henderson wrote:
> On 06/17/2016 11:07 AM, Pranith Kumar wrote:
>> On Fri, Jun 17, 2016 at 2:04 PM, Paolo Bonzini wrote:
>>>
>>>
>>> On 16/06/2016 21:07, Richard Henderson wrote:
>>>>> &a
On Fri, Jun 17, 2016 at 2:04 PM, Paolo Bonzini wrote:
>
>
> On 16/06/2016 21:07, Richard Henderson wrote:
>>> && ((addr >> 41) & 3) == 2
>>> -&& addr >> TARGET_VIRT_ADDR_SPACE_BITS == addr >> 63);
>>> +&& addr >> TARGET_VIRT_ADDR_SPACE_BITS == 1);
>
> What you
Generate mfence/sfence/lfence instruction on SSE2 enabled
processors. For older processors, generate a 'lock orl $0,0(%esp)'
instruction which has full ordering semantics.
Signed-off-by: Pranith Kumar
[rth: Check for sse2, fallback to locked memory op otherwise.]
Signed-off-by: Richard
This commit introduces the TCGOpcode for memory barrier instruction.
This opcode takes an argument which is the type of memory barrier
which should be generated.
Signed-off-by: Pranith Kumar
Signed-off-by: Richard Henderson
---
tcg/README| 17 +
tcg/tcg-op.c | 11
Signed-off-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
tcg/ppc/tcg-target.inc.c | 24
1 file changed, 24 insertions(+)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index da10052..766848e 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc
Signed-off-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
tcg/mips/tcg-target.inc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index 50e98ea..fb6cb3e 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg
Cc: Blue Swirl
Signed-off-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
tcg/sparc/tcg-target.inc.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c
index 9938a50..af8a300 100644
--- a/tcg/sparc/tcg
Cc: Alexander Graf
Signed-off-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
tcg/s390/tcg-target.inc.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index e0a60e6..b83b65b 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b
Cc: Aurelien Jarno
Signed-off-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
tcg/ia64/tcg-target.inc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/tcg/ia64/tcg-target.inc.c b/tcg/ia64/tcg-target.inc.c
index 395223e..7b220a7 100644
--- a/tcg/ia64/tcg-target.inc.c
+++ b/tcg
Cc: Andrzej Zaborowski
Cc: Peter Maydell
Signed-off-by: Pranith Kumar
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.inc.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index f9f54c6..1447aa8 100644
--- a
Cc: Stefan Weil
Signed-off-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
tcg/tci/tcg-target.inc.c | 3 +++
tci.c| 3 +++
2 files changed, 6 insertions(+)
diff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.inc.c
index fa74d52..8e950df 100644
--- a/tcg/tci
Signed-off-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
target-alpha/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 76dab15..f0bba40 100644
--- a/target-alpha/translate.c
+++ b/target-alpha
Cc: Claudio Fontana
Signed-off-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
tcg/aarch64/tcg-target.inc.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index 1447f7c..bc8ac9c 100644
--- a/tcg
Signed-off-by: Pranith Kumar
Signed-off-by: Richard Henderson
---
target-arm/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index e525f1e..012e450 100644
--- a/target-arm/translate.c
+++ b/target-arm
r tcg opcode.
Pranith Kumar (14):
Introduce TCGOpcode for memory barrier
tcg/i386: Add support for fence
tcg/aarch64: Add support for fence
tcg/arm: Add support for fence
tcg/ia64: Add support for fence
tcg/mips: Add support for fence
tcg/ppc: Add support for fence
tcg/s390: Add su
Signed-off-by: Pranith Kumar
---
target-arm/translate-a64.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index ce8141a..fa24bf2 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate
Signed-off-by: Pranith Kumar
---
target-i386/translate.c | 4
1 file changed, 4 insertions(+)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index bf33e6b..32b0f5c 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -8012,13 +8012,17 @@ static target_ulong
On Sat, Jun 18, 2016 at 1:48 AM, Richard Henderson wrote:
> On 06/17/2016 09:03 PM, Pranith Kumar wrote:
>>
>> case 0xe8 ... 0xef: /* lfence */
>> +tcg_gen_mb(TCG_MO_LD_LD | TCG_BAR_SC);
>> +break;
>> case 0xf0 ... 0xf7
Hi Sergey,
On Mon, Jun 20, 2016 at 5:21 PM, Sergey Fedorov wrote:
> On 18/06/16 07:03, Pranith Kumar wrote:
>> diff --git a/tcg/tcg.h b/tcg/tcg.h
>> index db6a062..36feca9 100644
>> --- a/tcg/tcg.h
>> +++ b/tcg/tcg.h
>> @@ -408,6 +408,20 @@ static inline intptr_t
On Tue, Jun 21, 2016 at 3:28 AM, Paolo Bonzini wrote:
>
>
> On 18/06/2016 06:03, Pranith Kumar wrote:
>> Signed-off-by: Pranith Kumar
>> ---
>> target-i386/translate.c | 4
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/target-i386/t
On Tue, Jun 21, 2016 at 1:54 PM, Peter Maydell wrote:
> On 21 June 2016 at 18:28, Pranith Kumar wrote:
>> Reg. the second point, I did consider this situation of running x86 on
>> ARM where such barriers are necessary for correctness. But, I am
>> really apprehensive of th
On Tue, Jun 21, 2016 at 11:09 AM, Alex Bennée wrote:
>>>
+TCG_BAR_SC = 128,
>>>
>>> How's that different from TCG_MO_ALL?
>>
>> TCG_BAR_* tells us what ordering is enforced. TCG_MO_* tells what on
>> what operations the ordering is to be enforced.
>
> This would be worthwhile in the
On Tue, Jun 21, 2016 at 2:04 PM, Alex Bennée wrote:
>
> Pranith Kumar writes:
>
>> This commit introduces the TCGOpcode for memory barrier instruction.
>>
>> This opcode takes an argument which is the type of memory barrier
>> which should be generated.
&
late can we rename this to
atomic_load_acquire()/atomic_store_release() like in the linux kernel?
Looks good either way.
Reviewed-by: Pranith Kumar
--
Pranith
Hello all,
I've been selected to participate in GSoC 2016 in the Qemu project. I will be
mentored by Alex Bennée and will be working on solving memory consistency
issues in the MTTCG project. In particular we are targeting to get ARM guests
working on x86 hosts as a first step by adding TCG suppo
Signed-off-by: Pranith Kumar
---
tcg/i386/tcg-target.h | 1 +
tcg/i386/tcg-target.inc.c | 9 +
tcg/tcg-opc.h | 2 +-
tcg/tcg.c | 1 +
4 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 92be341
This commit introduces the TCGOpcode for fence instruction.
Signed-off-by: Pranith Kumar
---
tcg/i386/tcg-target.inc.c | 4
tcg/tcg-opc.h | 2 ++
tcg/tcg.c | 2 ++
3 files changed, 8 insertions(+)
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg
Signed-off-by: Pranith Kumar
---
target-arm/translate.c | 11 +--
tcg/tcg-op.h | 5 +
tcg/tcg-opc.h | 2 +-
3 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index c946c0e..3407176 100644
--- a/target
On Tue, May 24, 2016 at 1:32 PM, Peter Maydell wrote:
>
> Since this is a new TCG op, can we have it documented
> in tcg/README, please? This should describe the semantics of
> the operation in enough detail that:
> * a new TCG backend can implement it correctly
> * a TCG frontend knows when it
8.07 13.33 +65%
10 7.10 8.90 +25%
20 6.34 7.02 +10%
30 5.48 6.11 +9.6%
40 4.90 5.46 +11.42%
I am not able to see any significant increases for lower thread counts though.
Signed-off-by: Pranith Kumar
---
include/qemu/seqlock.h | 2 +-
util/qht.c
On Tue, Oct 25, 2016 at 11:41 AM, Paolo Bonzini wrote:
>
>
> On 25/10/2016 17:35, Pranith Kumar wrote:
>> Using perf, I see that sequence lock is being a bottleneck since it is
>> being read by everyone. Giving it its own cache-line seems to help
>> things quite a bi
Paolo Bonzini writes:
> On 25/10/2016 17:49, Pranith Kumar wrote:
>> But we are taking the seqlock of only the head bucket, while the
>> readers are reading hashes/pointers of the chained buckets.
>
> No, we aren't. See qht_lookup__slowpath.
I don't see it
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