: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 70 --
target/riscv/cpu.h | 11
2 files changed, 79 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6f2b64422086..0632ac08cf35
e correct PMP access exceptions
trap values.
Signed-off-by: Hesham Almatary
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c| 1 +
target/riscv/cpu.h| 2 ++
target/riscv/cpu_helper.c | 16
3 files changed, 19 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0632ac08cf35
inclusion because
pmp_is_in_range(env, i, addr + size) returns 0 whereas
pmp_is_in_range(env, i, addr) returns 1.
Signed-off-by: Dayeol Lee
Reviewed-by: Alistair Francis
Reviewed-by: Michael Clark
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/pmp.c | 2 +-
1 file
From: Alistair Francis
Add support for the ratified RISC-V privledge spec.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 1 +
target/riscv/insn_trans/trans_privileged.inc.c | 2 +-
2 files
git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.1-sf1-v2
for you to fetch changes up to 56bf43fc565a2fa3e0a618ab45e1c82896d0782a:
hw/riscv: Load OpenSBI as the default firmware (2019-06-28 10:10:30 -0700)
RISC-V
From: Bin Meng
The largest pci bus number should be calculated from ECAM size,
instead of its base address.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv
Signed-off-by: Hesham Almatary
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 10 +-
target/riscv/pmp.c| 6 +++---
target/riscv/pmp.h| 2 +-
3 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu_helper
From: Alistair Francis
Deprecate the RISC-V privledge spec version 1.09.1 in favour of the new
1.10.0 and the ratified 1.11.0.
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
qemu-deprecated.texi | 8
1 file changed, 8 insertions(+)
diff --git a/qemu
ch in SiFiveESoCState, so instead we just include them within
the struct.
Fixes: 30efbf330a45 ("SiFive RISC-V GPIO Device")
Signed-off-by: Palmer Dabbelt
Suggested-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
hw/riscv/sifive_e
From: Hesham Almatary
The PMP should be checked when doing a page table walk, and report access
fault exception if the to-be-read PTE failed the PMP check.
Suggested-by: Jonathan Behrens
Signed-off-by: Hesham Almatary
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target
Signed-off-by: Palmer Dabbelt
---
target/riscv/pmp.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 5944f4cb6607..958c7502a0e0 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -258,11 +258,12 @@ bool
From: Alistair Francis
Add support for disabling/enabling the "Counters" extension.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/csr.c | 17 -
3 fil
From: Alistair Francis
Restructure the deprecated CPUs to make it clear in the code that these
are depreated. They are already marked as deprecated in
qemu-deprecated.texi. There are no functional changes.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer
From: Hesham Almatary
The PMP check should be of the memory access size rather
than TARGET_PAGE_SIZE.
Signed-off-by: Hesham Almatary
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git
).
Signed-off-by: Alistair Francis
[Palmer: Fix counter access semantics, change commit message to indicate
the behavior is fully emulated.]
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 17 +++--
2 files
From: Joel Sing
This prevents a load reservation from being placed in one context/process,
then being used in another, resulting in an SC succeeding incorrectly and
breaking atomics.
Signed-off-by: Joel Sing
Reviewed-by: Palmer Dabbelt
Reviewed-by: Richard Henderson
Signed-off-by: Palmer
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ba1325f43533..1689ffecf85f 100644
--- a/target/riscv
-by: Jim Wilson
Reviewed-by: Laurent Vivier
Signed-off-by: Palmer Dabbelt
---
linux-user/riscv/syscall_nr.h | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/linux-user/riscv/syscall_nr.h b/linux-user/riscv/syscall_nr.h
index dab6509e3ade..5c8728220994 100644
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 0bbfb7f48b79..a45b05ef8395 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv
]
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
disas/riscv.c | 62 +--
1 file changed, 45 insertions(+), 17 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 59a9b0437a5f..d37312705516 100644
--- a/disas/riscv.c
+++ b/disas
fence.i has been split out of the base ISA as part of the ratification
process. This patch adds a Zifencei argument, which disables the
fence.i instruction.
Signed-off-by: Palmer Dabbelt
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h
: Palmer Dabbelt
---
hw/riscv/boot.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 883df49a0c65..ff023f42d01d 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -56,12 +56,22 @@ target_ulong riscv_load_kernel(const
/sys/devices/system/cpu/cpu2/topology/core_siblings_list
0-7
Signed-off-by: Atish Patra
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
i
From: Alistair Francis
Set the priv spec version 1.11.0 as the default and allow selecting it
via the command line.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions
The various CSR instructions have been split out of the base ISA as part
of the ratification process. This patch adds a Zicsr argument, which
disables all the CSR instructions.
Signed-off-by: Palmer Dabbelt
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1
Meng
Signed-off-by: Palmer Dabbelt
---
hw/riscv/boot.c | 49 +
hw/riscv/sifive_u.c | 7 +++---
hw/riscv/virt.c | 11 ++---
include/hw/riscv/boot.h | 3 +++
qemu-deprecated.texi| 20 +
5 files changed, 84 insertions(
Signed-off-by: Palmer Dabbelt
---
hw/riscv/boot.c | 26 ++
hw/riscv/sifive_u.c | 4
hw/riscv/virt.c | 4
include/hw/riscv/boot.h | 2 ++
4 files changed, 36 insertions(+)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 0c8e72e455d7
ed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 32 +---
target/riscv/cpu.h | 2 --
2 files changed, 9 insertions(+), 25 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1689ffecf85f..6a54ebf10c62 100644
--- a/target/
From: "Wladimir J. van der Laan"
The constraint for `rdinstreth` was comparing the csr number to 0xc80,
which is `cycleh` instead. Fix this.
Signed-off-by: Wladimir J. van der Laan
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-
From: Alistair Francis
Add OpenSBI version 0.3 as a git submodule and as a prebult binary.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Signed-off-by: Palmer Dabbelt
---
.gitmodules | 3 ++
Makefile
: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 5ecc47cea35d..e2120ac7a5d3 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -
: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index e2120ac7a5d3..a416d5d08b4d 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -344,6
From: Alistair Francis
Split the common RISC-V boot functions into a seperate file. This allows
us to share the common code.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Makefile.objs | 1 +
hw/riscv/boot.c
From: Nathaniel Graff
Writes to the SiFive PRCI registers are preserved while leaving the
ready bits set for the HFX/HFR oscillators and the lock bit set for the
PLL.
Signed-off-by: Nathaniel Graff
Reviewed-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_prci.c
: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 70 --
target/riscv/cpu.h | 11
2 files changed, 79 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6f2b64422086..0632ac08cf35
git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.1-sf1-v3
for you to fetch changes up to 395fd69582a00b76a89c12d9c074055a9d207997:
hw/riscv: Extend the kernel loading support (2019-06-27 02:47:06 -0700)
RISC-V
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 0bbfb7f48b79..a45b05ef8395 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c| 1 +
target/riscv/cpu.h| 2 ++
target/riscv/cpu_helper.c | 16
3 files changed, 19 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0632ac08cf35
Signed-off-by: Hesham Almatary
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 10 +-
target/riscv/pmp.c| 6 +++---
target/riscv/pmp.h| 2 +-
3 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu_helper
From: Hesham Almatary
The PMP check should be of the memory access size rather
than TARGET_PAGE_SIZE.
Signed-off-by: Hesham Almatary
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git
inclusion because
pmp_is_in_range(env, i, addr + size) returns 0 whereas
pmp_is_in_range(env, i, addr) returns 1.
Signed-off-by: Dayeol Lee
Reviewed-by: Alistair Francis
Reviewed-by: Michael Clark
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/pmp.c | 2 +-
1 file
From: Hesham Almatary
The PMP should be checked when doing a page table walk, and report access
fault exception if the to-be-read PTE failed the PMP check.
Suggested-by: Jonathan Behrens
Signed-off-by: Hesham Almatary
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target
Signed-off-by: Palmer Dabbelt
---
target/riscv/pmp.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 5944f4cb6607..958c7502a0e0 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -258,11 +258,12 @@ bool
From: Bin Meng
The largest pci bus number should be calculated from ECAM size,
instead of its base address.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv
e correct PMP access exceptions
trap values.
Signed-off-by: Hesham Almatary
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.
From: Alistair Francis
Add support for the ratified RISC-V privledge spec.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 1 +
target/riscv/insn_trans/trans_privileged.inc.c | 2 +-
2 files
From: Alistair Francis
Add support for disabling/enabling the "Counters" extension.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/csr.c | 17 -
3 fil
ch in SiFiveESoCState, so instead we just include them within
the struct.
Fixes: 30efbf330a45 ("SiFive RISC-V GPIO Device")
Signed-off-by: Palmer Dabbelt
Suggested-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
hw/riscv/sifive_e
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ba1325f43533..1689ffecf85f 100644
--- a/target/riscv
From: Alistair Francis
Restructure the deprecated CPUs to make it clear in the code that these
are depreated. They are already marked as deprecated in
qemu-deprecated.texi. There are no functional changes.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer
From: Alistair Francis
Deprecate the RISC-V privledge spec version 1.09.1 in favour of the new
1.10.0 and the ratified 1.11.0.
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
qemu-deprecated.texi | 8
1 file changed, 8 insertions(+)
diff --git a/qemu
-by: Jim Wilson
Reviewed-by: Laurent Vivier
Signed-off-by: Palmer Dabbelt
---
linux-user/riscv/syscall_nr.h | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/linux-user/riscv/syscall_nr.h b/linux-user/riscv/syscall_nr.h
index dab6509e3ade..5c8728220994 100644
).
Signed-off-by: Alistair Francis
[Palmer: Fix counter access semantics, change commit message to indicate
the behavior is fully emulated.]
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 17 +++--
2 files
fence.i has been split out of the base ISA as part of the ratification
process. This patch adds a Zifencei argument, which disables the
fence.i instruction.
Signed-off-by: Palmer Dabbelt
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h
The various CSR instructions have been split out of the base ISA as part
of the ratification process. This patch adds a Zicsr argument, which
disables all the CSR instructions.
Signed-off-by: Palmer Dabbelt
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1
: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 5ecc47cea35d..e2120ac7a5d3 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -
From: Alistair Francis
Set the priv spec version 1.11.0 as the default and allow selecting it
via the command line.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions
ed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 32 +---
target/riscv/cpu.h | 2 --
2 files changed, 9 insertions(+), 25 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1689ffecf85f..6a54ebf10c62 100644
--- a/target/
From: "Wladimir J. van der Laan"
The constraint for `rdinstreth` was comparing the csr number to 0xc80,
which is `cycleh` instead. Fix this.
Signed-off-by: Wladimir J. van der Laan
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-
: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index e2120ac7a5d3..a416d5d08b4d 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -344,6
/sys/devices/system/cpu/cpu2/topology/core_siblings_list
0-7
Signed-off-by: Atish Patra
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
i
From: Joel Sing
This prevents a load reservation from being placed in one context/process,
then being used in another, resulting in an SC succeeding incorrectly and
breaking atomics.
Signed-off-by: Joel Sing
Reviewed-by: Palmer Dabbelt
Reviewed-by: Richard Henderson
Signed-off-by: Palmer
Signed-off-by: Palmer Dabbelt
---
hw/riscv/boot.c | 26 ++
hw/riscv/sifive_u.c | 4
hw/riscv/virt.c | 4
include/hw/riscv/boot.h | 2 ++
4 files changed, 36 insertions(+)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 0c8e72e455d7
: Palmer Dabbelt
---
hw/riscv/boot.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 883df49a0c65..ff023f42d01d 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -56,12 +56,22 @@ target_ulong riscv_load_kernel(const
]
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
disas/riscv.c | 62 +--
1 file changed, 45 insertions(+), 17 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 59a9b0437a5f..d37312705516 100644
--- a/disas/riscv.c
+++ b/disas
From: Alistair Francis
Split the common RISC-V boot functions into a seperate file. This allows
us to share the common code.
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Makefile.objs | 1 +
hw/riscv/boot.c
On Fri, 13 Sep 2019 02:17:32 PDT (-0700), Peter Maydell wrote:
On Wed, 11 Sep 2019 at 09:24, Palmer Dabbelt wrote:
The following changes since commit 89ea03a7dc83ca36b670ba7f787802791fcb04b1:
Merge remote-tracking branch 'remotes/huth-gitlab/tags/m68k-pull-2019-09-07'
into sta
On Fri, 06 Sep 2019 09:20:05 PDT (-0700), bmeng...@gmail.com wrote:
It is not useful if we only have one management CPU.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3
v, n - 33 + 8, NULL, val, -1);
+result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], NULL,
+ val, -1);
if (result == 0) {
return sizeof(target_ulong);
}
Reviewed-by: Palmer Dabbelt
I just tagged a fixed version of my PR, but I'll include this in the next one.
On Wed, 11 Sep 2019 00:00:56 PDT (-0700), aleksandar.m.m...@gmail.com wrote:
11.09.2019. 08.35, "liuzhiwei" је написао/ла:
Features:
* support specification riscv-v-spec-0.7.1(
https://content.riscv.org/wp-content/uploads/2019/06/17.40-Vector_RISCV-20190611-Vectors.pdf
).
Hi, Zhivei.
The
On Wed, 11 Sep 2019 15:43:29 PDT (-0700), richard.hender...@linaro.org wrote:
On 9/11/19 2:25 AM, liuzhiwei wrote:
@@ -873,7 +925,12 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_FFLAGS] = { fs, read_fflags, write_fflags },
[CSR_FRM] =
On Fri, 13 Sep 2019 08:25:21 PDT (-0700), bmeng...@gmail.com wrote:
Hi Palmer,
On Fri, Sep 13, 2019 at 10:33 PM Palmer Dabbelt wrote:
On Fri, 06 Sep 2019 09:20:05 PDT (-0700), bmeng...@gmail.com wrote:
> It is not useful if we only have one management CPU.
>
> Signed-off-by:
mideleg & -mie) |
(pending & env->mideleg & -sie);
+if (riscv_cpu_virt_enabled(env)) {
+target_ulong pending_hs_irq = hspending & -vsie;
+
+if (pending_hs_irq) {
+riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP);
+ return ctz64(pending_hs_irq);
+}
+}
+
if (irqs) {
return ctz64(irqs); /* since non-zero */
} else {
Reviewed-by: Palmer Dabbelt
MASK;
env->virt |= enable << VIRT_MODE_SHIFT;
}
Reviewed-by: Palmer Dabbelt
On Fri, 23 Aug 2019 16:38:29 PDT (-0700), Alistair Francis wrote:
When the PLIC generates an interrupt ensure we always set it for the SIP
CSR that corresponds to the HS (V=0) register.
Signed-off-by: Alistair Francis
---
hw/riscv/sifive_plic.c | 12 +++-
1 file changed, 11 insertions(
mp;
-get_field(*env->mstatus, MSTATUS_TW)) {
+get_field(*env->mstatus, MSTATUS_TW)) ||
+riscv_cpu_virt_enabled(env)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
} else {
cs->halted = 1;
Reviewed-by: Palmer Dabbelt
On Sun, 15 Sep 2019 06:07:18 PDT (-0700), bmeng...@gmail.com wrote:
Hi Palmer,
On Sun, Sep 15, 2019 at 3:00 AM Palmer Dabbelt wrote:
On Fri, 13 Sep 2019 08:25:21 PDT (-0700), bmeng...@gmail.com wrote:
> Hi Palmer,
>
> On Fri, Sep 13, 2019 at 10:33 PM Palmer Dabbelt wrote:
>>
to run the test suite or figure out how to add a test for this, as
I'm assuming there's a better way to do it.
Signed-off-by: Palmer Dabbelt
---
vl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/vl.c b/vl.c
index 630f5c5e9c..821a5d91c8 100644
--- a/vl.c
+++ b/vl.
It works for me.
Jonathan
On Sun, Sep 15, 2019 at 1:31 PM Palmer Dabbelt wrote:
On Sun, 15 Sep 2019 06:07:18 PDT (-0700), bmeng...@gmail.com wrote:
> Hi Palmer,
>
> On Sun, Sep 15, 2019 at 3:00 AM Palmer Dabbelt
wrote:
>>
>> On Fri, 13 Sep 2019 08:25:21 PDT (-0700), bm
From: Guenter Roeck
Add support for loading initrd with "-initrd "
to the sifive_u machine. This lets us boot into Linux without
disk drive.
Signed-off-by: Guenter Roeck
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 20 +-
The following changes since commit f8c3db33a5e863291182f8862ddf81618a7c6194:
target/sparc: Switch to do_transaction_failed() hook (2019-09-17 12:01:00
+0100)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.2-sf1-v3
for you to fetch
with error -2
when trying to boot Linux.
Signed-off-by: Guenter Roeck
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index
From: Philippe Mathieu-Daudé
The RISC-V Physical Memory Protection is restricted to privileged
modes. Restrict its compilation to QEMU system builds.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/Makefile.objs | 3
: Guenter Roeck
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 8313f2605e..ae5a16e636 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
ng details.
Signed-off-by: Bin Meng
Acked-by: Dr. David Alan Gilbert
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
hmp-commands-info.hx | 2 +-
target/riscv/Makefile.objs | 4 +
target/riscv/monitor.c | 229 +
3 files changed, 234
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Jonathan Behrens
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Chih-Min Chao
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_plic.c | 12
include/hw/riscv/sifive_plic.h | 3 ---
2 files changed
oint operations.
Signed-off-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Christophe de Dinechin
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h| 6 +-
target/riscv/cpu_helper.c | 10 ++
target/riscv/csr.c| 20 +++-
3 fi
cis
Signed-off-by: Palmer Dabbelt
---
target/riscv/pmp.c| 31 ++-
target/riscv/trace-events | 6 ++
2 files changed, 16 insertions(+), 21 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index d836288cb4..d4f1007109 100644
--- a/target/ri
From: Bin Meng
At present when "-bios image" is supplied, we just use the straight
path without searching for the configured data directories. Like
"-bios default", we add the same logic so that "-L" actually works.
Signed-off-by: Bin Meng
Reviewed-by: Alistair
lted in duplicated inclusion of "hw/hw.h".
Fixes: a27bd6c779ba ("Include hw/qdev-properties.h less")
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_prci.c | 1 -
hw/riscv/sifive_test.c | 1 -
2 files changed, 2
From: Alistair Francis
Update the Hypervisor CSR addresses to match the v0.4 spec.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_bits.h | 35 ++-
1 file changed, 18 insertions(+), 17 deletions
From: Bin Meng
Some of the properties only have 1 cell so we should use
qemu_fdt_setprop_cell() instead of qemu_fdt_setprop_cells().
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 18 +-
hw/riscv/virt.c | 24
From: Bin Meng
Like other binary files, the executable attribute of opensbi images
should not be set.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
pc-bios/opensbi-riscv32-virt-fw_jump.bin | Bin
pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
From: Bin Meng
"linux,phandle" property is optional. Remove all instances in the
sifive_u, virt and spike machine device trees.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 4
hw/riscv/spike.c| 1 -
hw/ri
From: Bin Meng
For RV32, the root page table's PPN has 22 bits hence its address
bits could be larger than the maximum bits that target_ulong is
able to represent. Use hwaddr instead.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/
From: Bin Meng
Use create_unimplemented_device() instead.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Kconfig| 1 +
hw/riscv/sifive_e.c | 23 ---
2 files changed, 9 insertions(+), 15 deletions(-)
diff --git a/hw
From: Bin Meng
sifive_u machine does not use PRCI as of today. Remove the prci
header inclusion.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv
From: Bin Meng
This adds a reset opcode for sifive_test device to trigger a system
reset for testing purpose.
Signed-off-by: Bin Meng
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_test.c | 4
include/hw/riscv/sifive_test.h | 3 ++-
2 files
From: Bin Meng
There is no need to return fdt at the end of create_fdt() because
it's already saved in s->fdt.
Signed-off-by: Bin Meng
Reviewed-by: Chih-Min Chao
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_
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