[Qemu-devel] [PATCH v7 03/35] target/riscv: Convert RVXI branch insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Palmer Dabbelt Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32.decode | 19 ++ target/riscv/insn_trans/trans_rvi.inc.c | 49

[Qemu-devel] [PATCH v7 07/35] target/riscv: Convert RVXI fence insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvi.inc.c | 19 +++ target/riscv/translate.c

[Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree

code_* functions. 4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested by Richard. [Patch 31-35] full tree available at https://github.com/palmer-dabbelt/qemu/tree/riscv-dt-v7 Cheers, Bastian v6 -> v7: - Rebased on top of riscv-for-master-4.0-sf1, which co

[Qemu-devel] [PATCH v7 08/35] target/riscv: Convert RVXI csr insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvi.inc.c | 79 + target/riscv/translate.

[Qemu-devel] [PATCH v7 01/35] target/riscv: Move CPURISCVState pointer to DisasContext

From: Bastian Koppelmann CPURISCVState is rarely used, so there is no need to pass it to every translate function. This paves the way for decodetree which only passes DisasContext to translate functions. Reviewed-by: Palmer Dabbelt Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis

[Qemu-devel] [PATCH v7 13/35] target/riscv: Convert RV64F insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32-64.decode | 6 +++ target/riscv/insn_trans/trans_rvf.inc.c | 58 - 2 files changed, 63 ins

[Qemu-devel] [PATCH v7 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64

From: Bastian Koppelmann it splices flwsp_ldsp, fswsp_sdsp, and jal_addiw and makes each of them reuse the code generator used for the non compressed insns. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- target/riscv/insn16-32.decode | 7 + target/riscv/in

[Qemu-devel] [PATCH v7 10/35] target/riscv: Convert RV32A insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32.decode | 17 +++ target/riscv/insn_trans/trans_rva.inc.c | 149 target/riscv/translate

[Qemu-devel] [PATCH v7 11/35] target/riscv: Convert RV64A insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32-64.decode | 13 +++ target/riscv/insn_trans/trans_rva.inc.c | 58 ++ target/riscv/translate.c

[Qemu-devel] [PATCH v7 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators

From: Bastian Koppelmann only one translate functions of rvc needs to handle special cases. For the other rvc insns we can remove the extra layer of indirection. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- target/riscv/insn16.decode | 37 +

[Qemu-devel] [PATCH v7 09/35] target/riscv: Convert RVXM insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32-64.decode | 7 ++ target/riscv/insn32.decode | 10 +++ target/riscv/insn_trans/trans_rvm.inc.c | 10

[Qemu-devel] [PATCH v7 30/35] target/riscv: Remove decode_RV32_64G()

From: Bastian Koppelmann decodetree handles all instructions now so the fallback is not necessary anymore. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/translate.c | 21 + 1 file changed, 1 insertion(+), 20 de

[Qemu-devel] [PATCH v7 05/35] target/riscv: Convert RV64I load/store insns to decodetree

From: Bastian Koppelmann this splits the 64-bit only instructions into its own decode file such that we generate the decoder for these instructions only for the RISC-V 64 bit target. Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Pee

[Qemu-devel] [PATCH v7 06/35] target/riscv: Convert RVXI arithmetic insns to decodetree

From: Bastian Koppelmann we cannot remove the call to gen_arith() in decode_RV32_64G() since it is used to translate multiply instructions. Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32-64.decode

[Qemu-devel] [PATCH v7 28/35] target/riscv: Rename trans_arith to gen_arith

From: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- target/riscv/insn_trans/trans_rvi.inc.c | 18 +- target/riscv/insn_trans/trans_rvm.inc.c | 14 +++--- target/riscv/translate.c| 4 ++-- 3 files changed, 18 ins

[Qemu-devel] [PATCH v7 21/35] target/riscv: Remove manual decoding from gen_branch()

From: Bastian Koppelmann We now utilizes argument-sets of decodetree such that no manual decoding is necessary. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn_trans/trans_rvi.inc.c | 46 +--- target/riscv/t

[Qemu-devel] [PATCH v7 31/35] target/riscv: Convert @cs_2 insns to share translation functions

From: Bastian Koppelmann These all expand simply to R format instructions. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- target/riscv/Makefile.objs | 10 +++--- target/riscv/insn16-64.decode | 24 ++ target/riscv/insn16.decode

[Qemu-devel] [PATCH v7 04/35] target/riscv: Convert RV32I load/store insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32.decode | 10 ++ target/riscv/insn_trans/trans_rvi.inc.c | 48 + 2 files changed, 58

[Qemu-devel] [PATCH v7 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions

From: Bastian Koppelmann gen_arith_imm() does a lot of decoding manually, which was hard to read in case of the shift instructions and is not necessary anymore with decodetree. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32.

[Qemu-devel] [PATCH v7 26/35] target/riscv: Remove shift and slt insn manual decoding

From: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn_trans/trans_rvi.inc.c | 93 + target/riscv/translate.c| 59 +--- 2 files changed, 81 insertions(+), 71

[Qemu-devel] [PATCH v7 20/35] target/riscv: Remove gen_jalr()

From: Bastian Koppelmann trans_jalr() is the only caller, so move the code into trans_jalr(). Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn_trans/trans_rvi.inc.c | 28 +- target/ris

[Qemu-devel] [PATCH v7 23/35] target/riscv: Remove manual decoding from gen_store()

From: Bastian Koppelmann With decodetree we don't need to convert RISC-V opcodes into to MemOps as the old gen_store() did. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn_trans/trans_rvi.inc.c | 27 + t

[Qemu-devel] [PATCH v7 14/35] target/riscv: Convert RV32D insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32.decode | 28 ++ target/riscv/insn_trans/trans_rvd.inc.c | 335 target/riscv/translate.

[Qemu-devel] [PATCH v7 22/35] target/riscv: Remove manual decoding from gen_load()

From: Bastian Koppelmann With decodetree we don't need to convert RISC-V opcodes into to MemOps as the old gen_load() did. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn_trans/trans_rvi.inc.c | 35 +++-- ta

[Qemu-devel] [PATCH v7 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64

From: Bastian Koppelmann this finally removes the old decoder functions that we carried along with it. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- target/riscv/Makefile.objs | 1 + target/riscv/insn16-32.decode | 24 target/riscv/insn16-

[Qemu-devel] [PATCH v7 12/35] target/riscv: Convert RV32F insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32.decode | 35 +++ target/riscv/insn_trans/trans_rvf.inc.c | 353 target/riscv/translate

[Qemu-devel] [PATCH v7 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree

From: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/Makefile.objs | 9 ++- target/riscv/insn16.decode | 55 ++ target/riscv/insn_trans/trans_rvc.inc.c | 75 +

[Qemu-devel] [PATCH v7 15/35] target/riscv: Convert RV64D insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32-64.decode | 8 + target/riscv/insn_trans/trans_rvd.inc.c | 76 +++ target/riscv/translate.c| 601

[Qemu-devel] [PATCH v7 16/35] target/riscv: Convert RV priv insns to decodetree

From: Bastian Koppelmann Acked-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32.decode| 15 +++ .../riscv/insn_trans/trans_privileged.inc.c | 110 ++ target/riscv/tra

[Qemu-devel] [PATCH v7 19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree

From: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn16.decode | 31 target/riscv/insn_trans/trans_rvc.inc.c | 101 target/riscv/translate.c| 83

[Qemu-devel] [PATCH v7 18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree

From: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn16.decode | 43 +++ target/riscv/insn_trans/trans_rvc.inc.c | 151 target/riscv/translate.c| 118

[Qemu-devel] [PATCH v7 29/35] target/riscv: Remove gen_system()

From: Bastian Koppelmann with all 16 bit insns moved to decodetree no path is falling back to gen_system(), so we can remove it. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/translate.c | 34 -- 1

[Qemu-devel] [PATCH v7 27/35] target/riscv: Remove manual decoding of RV32/64M insn

From: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn_trans/trans_rvm.inc.c | 55 ++-- target/riscv/translate.c| 320 ++-- 2 files changed, 164 insertions(+), 211 deletions

[Qemu-devel] [PATCH v7 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists

From: Bastian Koppelmann manual decoding in gen_arith() is not necessary with decodetree. For now the function is called trans_arith as the original gen_arith still exists. The former will be renamed to gen_arith as soon as the old gen_arith can be removed. Reviewed-by: Richard Henderson Signed

[Qemu-devel] [PATCH v7 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns

From: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- target/riscv/insn16.decode | 20 ++-- target/riscv/insn32.decode | 3 ++- target/riscv/insn_trans/trans_rvc.inc.c | 24 3 files chan

Re: [Qemu-devel] [PATCH] RISC-V: Fix pmpcfg register indexing

On Fri, 08 Feb 2019 10:57:17 PST (-0800), alistai...@gmail.com wrote: On Wed, Jan 30, 2019 at 2:20 PM Luke Nelson wrote: pmpcfg_csr_{read,write} do not correctly handle accesses to PMP configurations 8 through 15 (CSR pmpcfg2) on RV64. The current code computes the pmpcfg index using: (reg

Re: [Qemu-devel] [PATCH] hw/riscv/sifive_clint.c: avoid integer overflow in timecmp write

On Fri, 08 Feb 2019 10:41:17 PST (-0800), alistai...@gmail.com wrote: On Thu, Feb 7, 2019 at 2:08 AM Fabien Chouteau wrote: Hello Alistair, On 07/02/2019 01:42, Alistair Francis wrote:> > Can you describe what this fixes? > I encountered this problem when I tried to write 0x

[Qemu-devel] [Bug 1815078] Re: Qemu 3.1.0 risc-v mie.MEIE

It looks like this is fixed as of c7b951718815 ("RISC-V: Implement modular CSR helper interface"), which was merged on January 14th. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1815078 Title: Qem

Re: [Qemu-devel] [PATCH] SiFive RISC-V GPIO Device

On Wed, 13 Feb 2019 10:54:08 PST (-0800), th...@redhat.com wrote: On 2019-02-13 18:14, Peter Maydell wrote: On Wed, 13 Feb 2019 at 00:13, Alistair Francis wrote: I know the other RISC-V files don't do it, but this should go in the hw/gpio directory instead of hw/riscv. It might be nice to mo

Re: [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree

On Wed, 13 Feb 2019 01:06:41 PST (-0800), Bastian Koppelmann wrote: On 2/13/19 3:15 AM, Palmer Dabbelt wrote: On Tue, Feb 12, 2019 at 3:21 PM Palmer Dabbelt wrote: [snip] Do you, by any chance, have a v7? It looks like there's quite a few merge conflicts here, and while I'm OK f

[Qemu-devel] [Bug 1815078] Re: Qemu 3.1.0 risc-v mie.MEIE

e of April. ** Changed in: qemu Assignee: (unassigned) => Palmer Dabbelt (palmerdabbelt) ** Changed in: qemu Status: New => Fix Committed -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/181507

Re: [PATCH v1 22/28] target/riscv: Allow specifying MMU stage

On Fri, 23 Aug 2019 16:38:47 PDT (-0700), Alistair Francis wrote: Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 39 ++- 1 file changed, 30 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c inde

Re: [PATCH v1 24/28] target/riscv: Implement second stage MMU

*physical = (ppn | (vpn & ((1L << (ptshift + widened)) - 1))) << + PGSHIFT; +} else { +*physical = (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT; +} /* set permissions on the TLB entry */ if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { Reviewed-by: Palmer Dabbelt

Re: [PATCH v1 25/28] target/riscv: Call the second stage MMU in virtualisation mode

prot, mmu_idx, TARGET_PAGE_SIZE); @@ -738,9 +813,12 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } else if (probe) { return false; } else { -raise_mmu_exception(env, address, access_type, pmp_violation, true); +raise_mmu_exception(env, address, access_type, pmp_violation, first_stage_error); riscv_raise_exception(env, cs->exception_index, retaddr); } + +return true; + #else switch (access_type) { case MMU_INST_FETCH: Reviewed-by: Palmer Dabbelt

Re: [PATCH v1 27/28] target/riscv: Add the MSTATUS_MPV_ISSET helper macro

On Fri, 23 Aug 2019 16:39:00 PDT (-0700), Alistair Francis wrote: Add a helper macro MSTATUS_MPV_ISSET() which will determine if the MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V. Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 11 +++ target/riscv/cpu_helper

Re: [PATCH v1 26/28] target/riscv: Add support for the 32-bit MSTATUSH CSR

On Fri, 23 Aug 2019 16:38:58 PDT (-0700), Alistair Francis wrote: Signed-off-by: Alistair Francis --- target/riscv/cpu.c| 6 ++ target/riscv/cpu.h| 7 +++ target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_helper.c | 7 +++ target/riscv/csr.c| 23 +++

Re: [PATCH v1 28/28] target/riscv: Allow enabling the Hypervisor extension

bool ext_h; bool ext_counters; bool ext_ifencei; bool ext_icsr; Reviewed-by: Palmer Dabbelt

Re: [PATCH v2 4/7] riscv/sifive_u: Add the start-in-flash property

a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index a921079fbe..2656b43c58 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -57,6 +57,8 @@ typedef struct SiFiveUState { void *fdt; int fdt_size; + +bool start_in_flash; } SiFiveUState; enum { Reviewed-by: Palmer Dabbelt

Re: [PATCH v2 4/7] riscv/sifive_u: Add the start-in-flash property

On Mon, 30 Sep 2019 11:04:45 PDT (-0700), alistai...@gmail.com wrote: On Fri, Sep 27, 2019 at 12:57 AM Bin Meng wrote: On Fri, Sep 27, 2019 at 8:55 AM Alistair Francis wrote: > > Add a property that when set to true QEMU will jump from the ROM code to > the start of flash memory instead of DR

Re: [PATCH 2/2] riscv: sifive_u: Add ethernet0 to the aliases node

On Fri, 20 Sep 2019 02:19:02 PDT (-0700), bmeng...@gmail.com wrote: U-Boot expects this alias to be in place in order to fix up the mac address of the ethernet node. This is to keep in sync with Linux kernel commit below: https://patchwork.kernel.org/patch/11133033/ Signed-off-by: Bin Meng ---

Re: [PATCH] memory: Replace DEBUG_UNASSIGNED printf calls by trace events

On Fri, 20 Sep 2019 07:20:34 PDT (-0700), Peter Maydell wrote: On Fri, 20 Sep 2019 at 15:17, Paolo Bonzini wrote: I think it's simplest if all series (RISC-V, remove unassigned_access, this one) go through the RISC-V tree. I don't inherently object but IME the risc-v tree tends to move compar

Re: [PATCH v2 0/2] RISC-V: Convert to do_transaction_failed hook

4:target_ulong pte = address_space_ldq(cs->as, pte_addr, attrs, &res); translate.c:782:ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); gdbstub.c:328:env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */ All of these look safe to me. v2: - Rebase on master Palmer Dabbe

[PATCH] RISC-V: fcvt can set fflags, so set FS accordingly

cvt into F registers already did so). I haven't actually tried to manifest a bug here, but as far as I can tell the soft float stuff does set the invalid flag. Signed-off-by: Palmer Dabbelt --- target/riscv/insn_trans/trans_rvd.inc.c | 2 ++ target/riscv/insn_trans/trans_rvf.inc.c | 4 2 fi

Re: [PATCH V6] target/riscv: Ignore reserved bits in PTE for RV64

On Wed, 25 Sep 2019 17:14:21 PDT (-0700), guo...@kernel.org wrote: From: Guo Ren Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we need to ignore them. They cannot be a part of ppn. 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture 4.4 Sv39: Pag

Re: [Qemu-devel] [PATCH 2/2] riscv: sifive_u: Update the plic hart config to support multicore

On Fri, 17 May 2019 14:35:56 PDT (-0700), Alistair Francis wrote: On Fri, 2019-05-17 at 08:51 -0700, Bin Meng wrote: At present the PLIC is instantiated to support only one hart, while the machine allows at most 4 harts to be created. When more than 1 hart is configured, PLIC needs to instantiat

Re: [Qemu-devel] [PATCH 1/2] riscv: sifive_u: Do not create hard-coded phandles in DT

On Tue, 25 Jun 2019 18:47:15 PDT (-0700), bmeng...@gmail.com wrote: Hi, On Sat, May 18, 2019 at 5:34 AM Alistair Francis wrote: On Fri, 2019-05-17 at 08:51 -0700, Bin Meng wrote: > At present the cpu, plic and ethclk nodes' phandles are hard-coded > to 1/2/3 in DT. If we configure more than 1

Re: [Qemu-devel] [PATCH] riscv: virt: Correct pci "bus-range" encoding

On Tue, 25 Jun 2019 18:47:33 PDT (-0700), bmeng...@gmail.com wrote: Hi, On Fri, Jun 7, 2019 at 2:46 AM Alistair Francis wrote: On Thu, Jun 6, 2019 at 5:55 AM Bin Meng wrote: > > On Thu, May 30, 2019 at 11:36 AM Bin Meng wrote: > > > > Hi Alistair, > > > > On Thu, May 30, 2019 at 11:14 AM Al

Re: [Qemu-devel] [PATCH for 4.1 v3] target/riscv: Expose time CSRs when allowed by [m|s]counteren

On Tue, 25 Jun 2019 23:58:34 PDT (-0700), bmeng...@gmail.com wrote: On Wed, Jun 26, 2019 at 4:23 AM Jonathan Behrens wrote: I just did some testing on a HiFive Unleashed board and can confirm what you are saying. The low 5 bits of both mcounteren and scounteren are writable (if you try to writ

Re: [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64

On Wed, 26 Jun 2019 00:48:51 PDT (-0700), richard.hender...@linaro.org wrote: On 6/26/19 8:07 AM, Palmer Dabbelt wrote: On Tue, 25 Jun 2019 08:36:28 PDT (-0700), richard.hender...@linaro.org wrote: On 6/24/19 8:08 PM, Joel Sing wrote: Regarding the alignment for reservations, the

Re: [Qemu-devel] [PATCH for 4.1 v3] target/riscv: Expose time CSRs when allowed by [m|s]counteren

On Tue, 25 Jun 2019 23:54:06 PDT (-0700), bmeng...@gmail.com wrote: Hi Palmer, On Tue, Jun 25, 2019 at 5:57 PM Palmer Dabbelt wrote: On Mon, 24 Jun 2019 16:03:20 PDT (-0700), finte...@gmail.com wrote: > Apparently my previous message didn't make it out onto the list (sorry > abou

Re: [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64

On Wed, 26 Jun 2019 01:30:35 PDT (-0700), richard.hender...@linaro.org wrote: On 6/26/19 10:25 AM, Palmer Dabbelt wrote: You misunderstand.  The code is exactly correct as-is.  The alignment check happens implicitly as a part of the softmmu tlb resolution. Sorry, I thought you said it wasn&#

[Qemu-devel] [PULL 02/34] sifive_prci: Read and write PRCI registers

From: Nathaniel Graff Writes to the SiFive PRCI registers are preserved while leaving the ready bits set for the HFX/HFR oscillators and the lock bit set for the PLL. Signed-off-by: Nathaniel Graff Reviewed-by: Michael Clark Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_prci.c

[Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2

git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.1-sf1 for you to fetch changes up to c08a8317e31033ec76b8460a0b75cbcdaeeef481: hw/riscv: Load OpenSBI as the default firmware (2019-06-27 02:47:06 -0700) RISC-V

[Qemu-devel] [PULL 03/34] target/riscv: Fix PMP range boundary address bug

inclusion because pmp_is_in_range(env, i, addr + size) returns 0 whereas pmp_is_in_range(env, i, addr) returns 1. Signed-off-by: Dayeol Lee Reviewed-by: Alistair Francis Reviewed-by: Michael Clark Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/pmp.c | 2 +- 1 file

[Qemu-devel] [PULL 01/34] target/riscv: Allow setting ISA extensions via CPU props

: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 70 -- target/riscv/cpu.h | 11 2 files changed, 79 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6f2b64422086..0632ac08cf35

[Qemu-devel] [PULL 15/34] target/riscv: Add the mcountinhibit CSR

). Signed-off-by: Alistair Francis [Palmer: Fix counter access semantics, change commit message to indicate the behavior is fully emulated.] Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 17 +++-- 2 files

[Qemu-devel] [PULL 04/34] target/riscv: Implement riscv_cpu_unassigned_access

Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c| 1 + target/riscv/cpu.h| 2 ++ target/riscv/cpu_helper.c | 16 3 files changed, 19 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0632ac08cf35

[Qemu-devel] [PULL 25/34] riscv: virt: Add cpu-topology DT node.

/sys/devices/system/cpu/cpu2/topology/core_siblings_list 0-7 Signed-off-by: Atish Patra Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/virt.c | 22 -- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c i

[Qemu-devel] [PULL 30/34] hw/riscv: Split out the boot functions

From: Alistair Francis Split the common RISC-V boot functions into a seperate file. This allows us to share the common code. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv/Makefile.objs | 1 + hw/riscv/boot.c

[Qemu-devel] [PULL 14/34] target/riscv: Add the privledge spec version 1.11.0

From: Alistair Francis Add support for the ratified RISC-V privledge spec. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_privileged.inc.c | 2 +- 2 files

[Qemu-devel] [PULL 19/34] target/riscv: Remove user version information

ed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 32 +--- target/riscv/cpu.h | 2 -- 2 files changed, 9 insertions(+), 25 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1689ffecf85f..6a54ebf10c62 100644 --- a/target/

[Qemu-devel] [PULL 13/34] target/riscv: Restructure deprecatd CPUs

From: Alistair Francis Restructure the deprecated CPUs to make it clear in the code that these are depreated. They are already marked as deprecated in qemu-deprecated.texi. There are no functional changes. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer

[Qemu-devel] [PULL 20/34] target/riscv: Add support for disabling/enabling Counters

From: Alistair Francis Add support for disabling/enabling the "Counters" extension. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv/csr.c | 17 - 3 fil

[Qemu-devel] [PULL 06/34] RISC-V: Raise access fault exceptions on PMP violations

e correct PMP access exceptions trap values. Signed-off-by: Hesham Almatary Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.

[Qemu-devel] [PULL 05/34] RISC-V: Only Check PMP if MMU translation succeeds

Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 0bbfb7f48b79..a45b05ef8395 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv

[Qemu-devel] [PULL 12/34] RISC-V: Fix a memory leak when realizing a sifive_e

ch in SiFiveESoCState, so instead we just include them within the struct. Fixes: 30efbf330a45 ("SiFive RISC-V GPIO Device") Signed-off-by: Palmer Dabbelt Suggested-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/riscv/sifive_e

[Qemu-devel] [PULL 08/34] RISC-V: Check PMP during Page Table Walks

From: Hesham Almatary The PMP should be checked when doing a page table walk, and report access fault exception if the to-be-read PTE failed the PMP check. Suggested-by: Jonathan Behrens Signed-off-by: Hesham Almatary Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target

[Qemu-devel] [PULL 26/34] disas/riscv: Disassemble reserved compressed encodings as illegal

] Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- disas/riscv.c | 62 +-- 1 file changed, 45 insertions(+), 17 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index 59a9b0437a5f..d37312705516 100644 --- a/disas/riscv.c +++ b/disas

[Qemu-devel] [PULL 16/34] target/riscv: Set privledge spec 1.11.0 as default

From: Alistair Francis Set the priv spec version 1.11.0 as the default and allow selecting it via the command line. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions

[Qemu-devel] [PULL 07/34] RISC-V: Check for the effective memory privilege mode during PMP checks

Signed-off-by: Hesham Almatary Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 10 +- target/riscv/pmp.c| 6 +++--- target/riscv/pmp.h| 2 +- 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu_helper

[Qemu-devel] [PULL 23/34] RISC-V: Clear load reservations on context switch and SC

From: Joel Sing This prevents a load reservation from being placed in one context/process, then being used in another, resulting in an SC succeeding incorrectly and breaking atomics. Signed-off-by: Joel Sing Reviewed-by: Palmer Dabbelt Reviewed-by: Richard Henderson Signed-off-by: Palmer

[Qemu-devel] [PULL 09/34] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off

Signed-off-by: Palmer Dabbelt --- target/riscv/pmp.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 5944f4cb6607..958c7502a0e0 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -258,11 +258,12 @@ bool

[Qemu-devel] [PULL 11/34] riscv: virt: Correct pci "bus-range" encoding

From: Bin Meng The largest pci bus number should be calculated from ECAM size, instead of its base address. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv

[Qemu-devel] [PULL 29/34] riscv: sifive_u: Update the plic hart config to support multicore

: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 16 +++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index e2120ac7a5d3..a416d5d08b4d 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -344,6

[Qemu-devel] [PULL 34/34] hw/riscv: Load OpenSBI as the default firmware

Meng Signed-off-by: Palmer Dabbelt --- hw/riscv/boot.c | 49 + hw/riscv/sifive_u.c | 7 +++--- hw/riscv/virt.c | 11 ++--- include/hw/riscv/boot.h | 3 +++ qemu-deprecated.texi| 20 + 5 files changed, 84 insertions(

[Qemu-devel] [PULL 21/34] RISC-V: Add support for the Zifencei extension

fence.i has been split out of the base ISA as part of the ratification process. This patch adds a Zifencei argument, which disables the fence.i instruction. Signed-off-by: Palmer Dabbelt Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 1 + target/riscv/cpu.h

[Qemu-devel] [PULL 31/34] hw/riscv: Add support for loading a firmware

Signed-off-by: Palmer Dabbelt --- hw/riscv/boot.c | 26 ++ hw/riscv/sifive_u.c | 4 hw/riscv/virt.c | 4 include/hw/riscv/boot.h | 2 ++ 4 files changed, 36 insertions(+) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 0c8e72e455d7

[Qemu-devel] [PULL 10/34] RISC-V: Fix a PMP check with the correct access size

From: Hesham Almatary The PMP check should be of the memory access size rather than TARGET_PAGE_SIZE. Signed-off-by: Hesham Almatary Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git

[Qemu-devel] [PULL 28/34] riscv: sifive_u: Do not create hard-coded phandles in DT

: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 17 ++--- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 5ecc47cea35d..e2120ac7a5d3 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -

[Qemu-devel] [PULL 22/34] RISC-V: Add support for the Zicsr extension

The various CSR instructions have been split out of the base ISA as part of the ratification process. This patch adds a Zicsr argument, which disables all the CSR instructions. Signed-off-by: Palmer Dabbelt Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1

[Qemu-devel] [PULL 32/34] hw/riscv: Extend the kernel loading support

: Palmer Dabbelt --- hw/riscv/boot.c | 18 ++ 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 883df49a0c65..ff023f42d01d 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -56,12 +56,22 @@ target_ulong riscv_load_kernel(const

[Qemu-devel] [PULL 17/34] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1

From: Alistair Francis Deprecate the RISC-V privledge spec version 1.09.1 in favour of the new 1.10.0 and the ratified 1.11.0. Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- qemu-deprecated.texi | 8 1 file changed, 8 insertions(+) diff --git a/qemu

[Qemu-devel] [PULL 18/34] target/riscv: Require either I or E base extension

From: Alistair Francis Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ba1325f43533..1689ffecf85f 100644 --- a/target/riscv

[Qemu-devel] [PULL 24/34] RISC-V: Update syscall list for 32-bit support.

-by: Jim Wilson Reviewed-by: Laurent Vivier Signed-off-by: Palmer Dabbelt --- linux-user/riscv/syscall_nr.h | 15 ++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/linux-user/riscv/syscall_nr.h b/linux-user/riscv/syscall_nr.h index dab6509e3ade..5c8728220994 100644

[Qemu-devel] [PULL 27/34] disas/riscv: Fix `rdinstreth` constraint

From: "Wladimir J. van der Laan" The constraint for `rdinstreth` was comparing the csr number to 0xc80, which is `cycleh` instead. Fix this. Signed-off-by: Wladimir J. van der Laan Signed-off-by: Michael Clark Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-

[Qemu-devel] [PULL 33/34] roms: Add OpenSBI version 0.3

From: Alistair Francis Add OpenSBI version 0.3 as a git submodule and as a prebult binary. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Signed-off-by: Palmer Dabbelt --- .gitmodules | 3 ++ Makefile

Re: [Qemu-devel] [PATCH for 4.1 v3] target/riscv: Expose time CSRs when allowed by [m|s]counteren

On Thu, 27 Jun 2019 12:56:57 PDT (-0700), alistai...@gmail.com wrote: On Wed, Jun 26, 2019 at 1:25 AM Palmer Dabbelt wrote: On Tue, 25 Jun 2019 23:58:34 PDT (-0700), bmeng...@gmail.com wrote: > On Wed, Jun 26, 2019 at 4:23 AM Jonathan Behrens wrote: >> >> I just did some test

Re: [Qemu-devel] [PULL 33/34] roms: Add OpenSBI version 0.3

On Fri, 28 Jun 2019 09:12:45 PDT (-0700), alistai...@gmail.com wrote: On Fri, Jun 28, 2019 at 2:47 AM Jonathan Cameron wrote: On Thu, 27 Jun 2019 08:20:10 -0700 Palmer Dabbelt wrote: > From: Alistair Francis > > Add OpenSBI version 0.3 as a git submodule and as a prebult binary. &

Re: [Qemu-devel] [PATCH] fixup! roms: Add OpenSBI version 0.3

On Fri, 28 Jun 2019 09:15:03 PDT (-0700), Alistair Francis wrote: --- roms/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/roms/Makefile b/roms/Makefile index 562ed726fd..dc70fb5aea 100644 --- a/roms/Makefile +++ b/roms/Makefile @@ -179,7 +179,7 @@ opensbi64-virt:

[Qemu-devel] [PULL 02/34] sifive_prci: Read and write PRCI registers

From: Nathaniel Graff Writes to the SiFive PRCI registers are preserved while leaving the ready bits set for the HFX/HFR oscillators and the lock bit set for the PLL. Signed-off-by: Nathaniel Graff Reviewed-by: Michael Clark Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_prci.c

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