with error -2
when trying to boot Linux.
Signed-off-by: Guenter Roeck
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index
oint operations.
Signed-off-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Christophe de Dinechin
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h| 6 +-
target/riscv/cpu_helper.c | 10 ++
target/riscv/csr.c| 20 +++-
3 fi
cis
Signed-off-by: Palmer Dabbelt
---
target/riscv/pmp.c| 31 ++-
target/riscv/trace-events | 6 ++
2 files changed, 16 insertions(+), 21 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index d836288cb4..d4f1007109 100644
--- a/target/ri
From: Guenter Roeck
Add support for loading initrd with "-initrd "
to the sifive_u machine. This lets us boot into Linux without
disk drive.
Signed-off-by: Guenter Roeck
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 20 +-
From: Philippe Mathieu-Daudé
The RISC-V Physical Memory Protection is restricted to privileged
modes. Restrict its compilation to QEMU system builds.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/Makefile.objs | 3
From: Bin Meng
This adds a helper routine for finding firmware. It is currently
used only for "-bios default" case.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/boot.c | 22 +++---
include/hw/riscv/boot.h
From: Bin Meng
For RV32, the root page table's PPN has 22 bits hence its address
bits could be larger than the maximum bits that target_ulong is
able to represent. Use hwaddr instead.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/
From: Alistair Francis
Update the Hypervisor CSR addresses to match the v0.4 spec.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_bits.h | 35 ++-
1 file changed, 18 insertions(+), 17 deletions
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Jonathan Behrens
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Chih-Min Chao
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_plic.c | 12
include/hw/riscv/sifive_plic.h | 3 ---
2 files changed
From: Bin Meng
This removes "reg-names" and "riscv,max-priority" properties of the
PLIC node from device tree.
Signed-off-by: Bin Meng
Reviewed-by: Jonathan Behrens
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 2 --
hw/riscv/
From: Bin Meng
This adds a reset opcode for sifive_test device to trigger a system
reset for testing purpose.
Signed-off-by: Bin Meng
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_test.c | 4
include/hw/riscv/sifive_test.h | 3 ++-
2 files
ng details.
Signed-off-by: Bin Meng
Acked-by: Dr. David Alan Gilbert
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
hmp-commands-info.hx | 2 +-
target/riscv/Makefile.objs | 4 +
target/riscv/monitor.c | 229 +
3 files changed, 234
From: Bin Meng
At present when "-bios image" is supplied, we just use the straight
path without searching for the configured data directories. Like
"-bios default", we add the same logic so that "-L" actually works.
Signed-off-by: Bin Meng
Reviewed-by: Alistair
From: Bin Meng
The inclusion of "target/riscv/cpu.h" is unnecessary in various
sifive model drivers.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_prci.c | 1 -
hw/riscv/sifive_test.c | 1 -
hw/riscv/sifive_uart.c | 1
From: Bin Meng
"linux,phandle" property is optional. Remove all instances in the
sifive_u, virt and spike machine device trees.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 4
hw/riscv/spike.c| 1 -
hw/ri
From: Bin Meng
Replace the call to hw_error() with qemu_log_mask(LOG_GUEST_ERROR,...)
in various sifive models.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_prci.c | 8 +---
hw/riscv/sifive_test.c | 5 +++--
hw/riscv
lted in duplicated inclusion of "hw/hw.h".
Fixes: a27bd6c779ba ("Include hw/qdev-properties.h less")
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_prci.c | 1 -
hw/riscv/sifive_test.c | 1 -
2 files changed, 2
From: Bin Meng
Some of the properties only have 1 cell so we should use
qemu_fdt_setprop_cell() instead of qemu_fdt_setprop_cells().
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 18 +-
hw/riscv/virt.c | 24
From: Bin Meng
Like other binary files, the executable attribute of opensbi images
should not be set.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
pc-bios/opensbi-riscv32-virt-fw_jump.bin | Bin
pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
ed based on the property value.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/riscv_hart.c | 3 ++-
include/hw/riscv/riscv_hart.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/ris
From: Bin Meng
Use create_unimplemented_device() instead.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Kconfig| 1 +
hw/riscv/sifive_e.c | 23 ---
2 files changed, 9 insertions(+), 15 deletions(-)
diff --git a/hw
From: Bin Meng
sifive_u machine does not use PRCI as of today. Remove the prci
header inclusion.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv
From: Bin Meng
There is no need to return fdt at the end of create_fdt() because
it's already saved in s->fdt.
Signed-off-by: Bin Meng
Reviewed-by: Chih-Min Chao
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_
From: Bin Meng
It is not useful if we only have one management CPU.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 4 +++-
include/hw/riscv/sifive_u.h | 2 ++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a
From: Bin Meng
Group SiFive E and U cpu type defines into one header file.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Palmer Dabbelt
---
include/hw/riscv/sifive_cpu.h | 31 +++
include/hw/riscv
ions.
Signed-off-by: Bin Meng
Reviewed-by: Chih-Min Chao
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Makefile.objs | 2 +-
hw/riscv/sifive_e.c | 4 +-
hw/riscv/{sifive_prci.c => sifive_e_prci.c} | 79 ++--
From: Bin Meng
For hfxosccfg register programming, SIFIVE_E_PRCI_HFXOSCCFG_RDY and
SIFIVE_E_PRCI_HFXOSCCFG_EN should be used.
Signed-off-by: Bin Meng
Acked-by: Alistair Francis
Reviewed-by: Chih-Min Chao
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Palmer Dabbelt
---
hw/riscv
From: Bin Meng
Now that we have added a PRCI node, update existing UART and ethernet
nodes to reference PRCI as their clock sources, to keep in sync with
the Linux kernel device tree.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c
From: Bin Meng
With heterogeneous harts config, the PLIC hart topology configuration
string are "M,MS,.." because of the monitor hart #0.
Suggested-by: Fabien Chouteau
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 7
From: Bin Meng
Currently the PRCI register block size is set to 0x8000, but in fact
0x1000 is enough, which is also what the manual says.
Signed-off-by: Bin Meng
Reviewed-by: Chih-Min Chao
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_e_prci.c | 2
the file header says the RISC-V hart array holds the state
of a heterogeneous array of RISC-V harts, which is not true.
Update the comment to mention homogeneous array of RISC-V harts.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/riscv_hart.c
hem any more.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 24 +---
include/hw/riscv/sifive_u.h | 3 +--
2 files changed, 2 insertions(+), 25 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/
Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Makefile.objs | 1 +
hw/riscv/sifive_u_otp.c | 191
include/hw/riscv/sifive_u_otp.h | 80 +
3 files changed, 272 insertions(+)
create mode 100644 hw/riscv/sifive_u_otp.c
create mode
heterogeneous harts.
The cpu nodes in the generated DTS have been updated as well.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 92 +++--
include/hw/riscv/sifive_u.h | 6 ++-
2 files changed
From: Bin Meng
Add PRCI mmio base address and size mappings to sifive_u machine,
and generate the corresponding device tree node.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 24 +++-
include/hw
From: Bin Meng
This updates model and compatible strings to use the same strings
as used in the Linux kernel device tree (hifive-unleashed-a00.dts).
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 5 +++--
1 file changed, 3
From: Bin Meng
With the support of heterogeneous harts and PRCI model, it's now
possible to use the OpenSBI image (PLATFORM=sifive/fu540) built
for the real hardware.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
pc-bios/opensbi-riscv64-sif
From: Bin Meng
This updates the UART base address and IRQs to match the hardware.
Signed-off-by: Bin Meng
Reviewed-by: Jonathan Behrens
Acked-by: Alistair Francis
Reviewed-by: Chih-Min Chao
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 4 ++--
include/hw/riscv/sifive_u.h
From: Bin Meng
To keep in sync with Linux kernel device tree, generate hfclk and
rtcclk nodes in the device tree, to be referenced by PRCI node.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 23
From: Alistair Francis
This is meant to mask off the hypervisor bits, but a typo caused it to
mask MPP instead.
Fixes: 1f0419cb04 ("target/riscv: Allow setting mstatus virtulisation bits")
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Signed-off-by: Palmer Dabbelt
---
ta
From: Bin Meng
This adds a simple PRCI model for FU540 (sifive_u). It has different
register layout from the existing PRCI model for FE310 (sifive_e).
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Makefile.objs | 1 +
hw/riscv
e name as "/soc/uart@...",
causing U-Boot fail to find the serial node in DT.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.
From: Alistair Francis
Use the TB_FLAGS_MSTATUS_FS macro when enabling floating point in the tb
flags.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target
reg base
& size to the property encoding.
Tested with upstream U-Boot and Linux kernel MACB drivers.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Kconfig| 1 +
hw/riscv/sifive_u.c | 24
includ
From: Bin Meng
This adds an OTP memory with a given serial number to the sifive_u
machine. With such support, the upstream U-Boot for sifive_fu540
boots out of the box on the sifive_u machine.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv
From: Atish Patra
Use both the generic register name and ABI name for the general purpose
registers and floating point registers.
Signed-off-by: Atish Patra
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 19
On Fri, 23 Aug 2019 16:38:18 PDT (-0700), Alistair Francis wrote:
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h| 24 ---
target/riscv/cpu_bits.h | 7
target/riscv/cpu_helper.c | 88 +++
3 files changed, 113 insertions(+), 6 de
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 19 ++
target/riscv/insn_trans
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 10 ++
target/riscv/insn_trans/trans_rvi.inc.c | 48
From: Bastian Koppelmann
we cannot remove the call to gen_arith() in decode_RV32_64G() since it
is used to translate multiply instructions.
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
staging (2019-03-01 11:20:49 +)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.0-sf2
for you to fetch changes up to 0bcba29464ea9969fc69cd729e4c8bddfb2e18e3:
target/riscv: Remaining rvc insn reuse 32 bit translators (2019-0
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvi.inc.c | 19
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 17 +++
target/riscv/insn_trans/trans_rva.inc.c | 160
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvi.inc.c | 79
From: Bastian Koppelmann
for now only LUI & AUIPC are decoded and translated. If decodetree fails, we
fall back to the old decoder.
Reviewed-by: Richard Henderson
Acked-by: Alistair Francis
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dab
: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/Makefile.objs | 8 +---
target/riscv/insn32-64.decode | 25 +
target/riscv/insn_trans/trans_rvi.inc.c | 20
target/riscv/translate.c| 7 ---
4
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn16.decode | 43 +++
target/riscv/insn_trans/trans_rvc.inc.c | 151
target/riscv
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32-64.decode | 13 +++
target/riscv/insn_trans/trans_rva.inc.c | 58
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32-64.decode | 7 ++
target/riscv/insn32.decode | 10 +++
target/riscv
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/Makefile.objs | 9 ++-
target/riscv/insn16.decode | 55 ++
target/riscv/insn_trans
From: Bastian Koppelmann
We now utilizes argument-sets of decodetree such that no manual
decoding is necessary.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 46
From: Bastian Koppelmann
gen_arith_imm() does a lot of decoding manually, which was hard to read
in case of the shift instructions and is not necessary anymore with
decodetree.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 35 +++
target/riscv/insn_trans/trans_rvf.inc.c | 379
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32-64.decode | 6 +++
target/riscv/insn_trans/trans_rvf.inc.c | 60
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvi.inc.c | 21 +
target/riscv/translate.c| 40 +++--
3 files changed, 34
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32-64.decode | 8 +
target/riscv/insn_trans/trans_rvd.inc.c | 82
target/riscv
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode| 15 +++
.../riscv/insn_trans/trans_privileged.inc.c | 110
From: Bastian Koppelmann
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_store() did.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvi.
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 18 +-
target/riscv/insn_trans/trans_rvm.inc.c | 14 +++---
target/riscv/translate.c
From: Bastian Koppelmann
with all 16 bit insns moved to decodetree no path is falling back to
gen_system(), so we can remove it.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/translate.c | 34
From: Bastian Koppelmann
trans_jalr() is the only caller, so move the code into trans_jalr().
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvi.inc.c
From: Bastian Koppelmann
These all expand simply to R format instructions.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Palmer Dabbelt
---
target/riscv/Makefile.objs | 10 +++---
target/riscv/insn16-64.decode | 24
From: Bastian Koppelmann
this finally removes the old decoder functions that we carried along
with it.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Palmer Dabbelt
---
target/riscv/Makefile.objs | 1 +
target/riscv/insn16-32.decode
From: Bastian Koppelmann
it splices flwsp_ldsp, fswsp_sdsp, and jal_addiw and makes each of them
reuse the code generator used for the non compressed insns.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn16-32.decode
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn16.decode | 20 ++--
target/riscv/insn32.decode | 3 ++-
target/riscv/insn_trans/trans_rvc.inc.c | 24
From: Bastian Koppelmann
decodetree handles all instructions now so the fallback is not necessary
anymore.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/translate.c | 21 +
1
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 93 +
target/riscv/translate.c| 59 +---
2
From: Bastian Koppelmann
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_load() did.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvi.
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn16.decode | 31
target/riscv/insn_trans/trans_rvc.inc.c | 101
target/riscv
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 28 ++
target/riscv/insn_trans/trans_rvd.inc.c | 360
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvm.inc.c | 55 ++--
target/riscv/translate.c| 320 ++--
2 files changed
From: Bastian Koppelmann
only one translate functions of rvc needs to handle special cases. For
the other rvc insns we can remove the extra layer of indirection.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn16.decode
On Mon, 04 Mar 2019 11:30:21 PST (-0800), richard.hender...@linaro.org wrote:
On 3/4/19 4:52 AM, Bastian Koppelmann wrote:
This looks like an unforeseen decodetree problem (CC' Richard). As these 16/32
instructions share the same trans_* function, we emit the same typedef once for
16 bit and onc
On Fri, 08 Feb 2019 11:28:48 PST (-0800), alistai...@gmail.com wrote:
On Fri, Feb 8, 2019 at 11:09 AM Jim Wilson wrote:
On Fri, Feb 8, 2019 at 10:17 AM Alistair Francis wrote:
> Can we just write a wrapper function then that sets and unsets the variable?
> Something like this:
>
> riscv_csrrw
On Wed, 23 Jan 2019 01:25:03 PST (-0800), Bastian Koppelmann wrote:
Hi,
this patchset converts the RISC-V decoder to decodetree in four major steps:
1) Convert 32-bit instructions to decodetree [Patch 1-16]:
Many of the gen_* functions are called by the decode functions for 16-bit
and 3
On Tue, Feb 12, 2019 at 3:21 PM Palmer Dabbelt wrote:
> On Wed, 23 Jan 2019 01:25:03 PST (-0800), Bastian Koppelmann wrote:
> > Hi,
> >
> > this patchset converts the RISC-V decoder to decodetree in four major
> steps:
> >
> > 1) Convert 32-bit in
On Wed, 13 Feb 2019 01:06:41 PST (-0800), Bastian Koppelmann wrote:
On 2/13/19 3:15 AM, Palmer Dabbelt wrote:
On Tue, Feb 12, 2019 at 3:21 PM Palmer Dabbelt wrote:
[snip]
Do you, by any chance, have a v7? It looks like there's quite a few merge
conflicts here, and while I'm OK f
From: Richard Henderson
Signed-off-by: Michael Clark
Reviewed-by: Michael Clark
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 6 +++---
target/riscv/translate.c | 10 +-
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a
From: Michael Clark
gen methods should access state from DisasContext. Add misa
field to the DisasContext struct and remove CPURISCVState
argument from all gen methods.
Signed-off-by: Michael Clark
Reviewed-by: Richard Henderson
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
02-11 17:04:57 +)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.0-sf1
for you to fetch changes up to 40e46e516d90c2dfe8e8de3741c1c65f1b526502:
riscv: Ensure the kernel start address is correctly cast (2019-0
From: Alistair Francis
The gen methods should access state from DisasContext. Add priv_ver
field to the DisasContext struct.
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Palmer Dabbelt
---
target/riscv/translate.c | 7 +--
1 file changed, 5 insertions
From: Xi Wang
Access to a counter in U-mode is permitted only if the corresponding
bit is set in both mcounteren and scounteren. The current code
ignores mcounteren and checks scounteren only for U-mode access.
Signed-off-by: Xi Wang
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
From: Michael Clark
This adds the necessary minimum to support S-mode
virtualization for priv ISA >= v1.10
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
Co-authored-by: Matthew Suozzo
Co-authored-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target/riscv/cs
tatus.FS so the bug in the first
spin of this patch has been fixed in a prior commit.
Signed-off-by: Michael Clark
Reviewed-by: Michael Clark
Signed-off-by: Alistair Francis
Co-authored-by: Richard Henderson
Co-authored-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c
* rename riscv_set_mode to riscv_cpu_set_mode
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Palmer Dabbelt
---
linux-user/riscv/signal.c | 4 ++--
target/riscv/cpu.h| 21 ++---
target/riscv/cpu_helper.c | 10
. The
reason is that the binary was loaded to a negative address.
Signed-off-by: Alistair Francis
Suggested-by: Alexander Graf
Reported-by: Alexander Graf
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_e.c | 2 +-
hw/riscv/sifive_u.c | 2 +-
hw/riscv
Signed-off-by: Palmer Dabbelt
---
target/riscv/translate.c | 158 +++
1 file changed, 158 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index bb80387088e2..b7176cbf98e1 100644
--- a/target/riscv/translate.c
+++ b/target/riscv
Michael is no longer employed by SiFive and does not want to continue
maintianing the RISC-V port.
Signed-off-by: Palmer Dabbelt
---
MAINTAINERS | 1 -
1 file changed, 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index a2da141a928f..e170a4c73376 100644
--- a/MAINTAINERS
+++ b
A conservative approach to consistency is
taken by flushing the translation cache on misa writes. misa_mask
is added to the CPU struct to store the original set of extensions.
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
t
From: Bastian Koppelmann
for now only LUI & AUIPC are decoded and translated. If decodetree fails, we
fall back to the old decoder.
Reviewed-by: Richard Henderson
Acked-by: Alistair Francis
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/Makefile.objs
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