On Wed, 21 Nov 2018 10:32:45 PST (-0800), alistai...@gmail.com wrote:
On Wed, Nov 21, 2018 at 10:05 AM Logan Gunthorpe wrote:
On 2018-11-21 10:02 a.m., Alistair Francis wrote:
> Connect the Xilinx PCIe device based on the information in the device
> tree stored in the ROM of the HiFish Unlea
On Wed, 21 Nov 2018 11:21:40 PST (-0800), alistai...@gmail.com wrote:
On Wed, Nov 21, 2018 at 11:19 AM Logan Gunthorpe wrote:
On 2018-11-21 12:16 p.m., Alistair Francis wrote:
>>> Do you see the MicroSemi PCIe probe in your dmesg?
>>
>> I do when I have a kernel with microsemi PCI Support (s
On Wed, 21 Nov 2018 14:01:10 PST (-0800), alistai...@gmail.com wrote:
On Wed, Nov 21, 2018 at 1:37 PM Palmer Dabbelt wrote:
On Wed, 21 Nov 2018 11:21:40 PST (-0800), alistai...@gmail.com wrote:
> On Wed, Nov 21, 2018 at 11:19 AM Logan Gunthorpe wrote:
>>
>>
>>
>&
On Wed, 21 Nov 2018 13:49:53 PST (-0800), alistai...@gmail.com wrote:
On Wed, Nov 21, 2018 at 1:26 PM Palmer Dabbelt wrote:
On Wed, 21 Nov 2018 10:32:45 PST (-0800), alistai...@gmail.com wrote:
> On Wed, Nov 21, 2018 at 10:05 AM Logan Gunthorpe wrote:
>>
>>
>>
>&
On Wed, 21 Nov 2018 14:01:34 PST (-0800), log...@deltatee.com wrote:
On 2018-11-21 2:54 p.m., Alistair Francis wrote:
The last time I tested this it worked (although I might not have
tested interrupts) and now it doesn't. Nothing has changed in the
series, my guest software has changed though.
On Wed, 21 Nov 2018 14:23:13 PST (-0800), alistai...@gmail.com wrote:
On Wed, Nov 21, 2018 at 2:15 PM Palmer Dabbelt wrote:
On Wed, 21 Nov 2018 13:49:53 PST (-0800), alistai...@gmail.com wrote:
> On Wed, Nov 21, 2018 at 1:26 PM Palmer Dabbelt wrote:
>>
>> On Wed, 21 Nov 20
There was a recent thread about unmaintained files in QEMU where it was
noted that a few RISC-V related files had slipped through the patterns
in our MAINTAINERS file entry. This patch adds some more aggressive
pattern matching in an attempt to rectify this situation.
Signed-off-by: Palmer
There's three of us that are paid to work on this.
Signed-off-by: Palmer Dabbelt
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index e89adc81d5d5..d5ec5e74f328 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -250,7 +250,7
hrough the emulation fidelity issues apparent in the other targets
before adding machines for those.
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_e.c | 26 --
hw/riscv/sifive_u.c | 2 ++
qemu-deprecated.texi | 7 +++
3 files changed, 33 insertions(+), 2 deletions
On Wed, 21 Nov 2018 16:29:09 PST (-0800), phi...@redhat.com wrote:
On 22/11/18 0:46, Palmer Dabbelt wrote:
There was a recent thread about unmaintained files in QEMU where it was
noted that a few RISC-V related files had slipped through the patterns
in our MAINTAINERS file entry. This patch
On Wed, 21 Nov 2018 14:34:44 PST (-0800), Alistair Francis wrote:
> Ensure that the calculate initrd offset points to a valid address for
> the architecture.
>
> Signed-off-by: Alistair Francis
> Suggested-by: Alexander Graf
> Reported-by: Alexander Graf
> ---
> hw/riscv/virt.c | 7 ++-
> 1
On Wed, 21 Nov 2018 15:26:01 PST (-0800), log...@deltatee.com wrote:
On 2018-11-21 4:10 p.m., Guenter Roeck wrote:
FWIW, I absoutely agree. If the board can only be used to boot an initrd,
it is quite pointless to have it around. Actually it is worse than pointless,
since it will result in peo
On Wed, 21 Nov 2018 18:09:27 PST (-0800), alistai...@gmail.com wrote:
On Wed, Nov 21, 2018 at 5:58 PM Palmer Dabbelt wrote:
On Wed, 21 Nov 2018 14:34:44 PST (-0800), Alistair Francis wrote:
> Ensure that the calculate initrd offset points to a valid address for
> the architecture.
>
On Wed, 21 Nov 2018 18:23:26 PST (-0800), alistai...@gmail.com wrote:
On Wed, Nov 21, 2018 at 6:13 PM Palmer Dabbelt wrote:
On Wed, 21 Nov 2018 15:26:01 PST (-0800), log...@deltatee.com wrote:
>
>
> On 2018-11-21 4:10 p.m., Guenter Roeck wrote:
>> FWIW, I absoutely agree. I
On Thu, 22 Nov 2018 00:44:32 PST (-0800), th...@redhat.com wrote:
Hi,
On 2018-11-22 00:31, Palmer Dabbelt wrote:
These machines had names that were too general: there are many E
and U machines, and it's easy for users to get confused about which one
is which. The one configuration tha
On Thu, 22 Nov 2018 02:59:18 PST (-0800), abolo...@redhat.com wrote:
> On Wed, 2018-11-21 at 17:02 +, Alistair Francis wrote:
>> V7:
>> - Fix the GPEX memory mapping thanks to Bin Meng
>> - Fix the interrupt mapping thanks to Logan Gunthorpe
>>
> [...]
>>
>> Alistair Francis (6):
>> hw/risc
On Mon, 26 Nov 2018 01:06:33 PST (-0800), Bastian Koppelmann wrote:
On 11/26/18 4:20 AM, Mao Zhongyi wrote:
Signed-off-by: Mao Zhongyi
---
target/riscv/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Bastian Koppelmann
Shouldn't we also use device_class_set
On Tue, 27 Nov 2018 17:46:04 PST (-0800), maozhon...@cmss.chinamobile.com wrote:
Hi, Palmer
On 11/28/18 8:34 AM, Palmer Dabbelt wrote:
On Mon, 26 Nov 2018 01:06:33 PST (-0800), Bastian Koppelmann wrote:
On 11/26/18 4:20 AM, Mao Zhongyi wrote:
Signed-off-by: Mao Zhongyi
---
target/riscv
On Thu, 20 Dec 2018 11:04:41 PST (-0800), alistai...@gmail.com wrote:
On Thu, Dec 20, 2018 at 10:45 AM Palmer Dabbelt wrote:
On Thu, 20 Dec 2018 09:20:05 PST (-0800), alistai...@gmail.com wrote:
> On Wed, Dec 19, 2018 at 10:07 PM Richard Henderson
> wrote:
>>
>> On
On Thu, 20 Dec 2018 09:20:05 PST (-0800), alistai...@gmail.com wrote:
On Wed, Dec 19, 2018 at 10:07 PM Richard Henderson
wrote:
On 12/19/18 11:16 AM, Alistair Francis wrote:
> This patch set adds RISC-V backend support to QEMU. This is based on
> Michael Clark's original work with extra work o
From: Alistair Francis
Increase the number of interrupts to match the HiFive Unleashed board.
Signed-off-by: Alistair Francis
Tested-by: Guenter Roeck
Tested-by: Andrea Bolognani
Signed-off-by: Palmer Dabbelt
---
include/hw/riscv/virt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion
The following changes since commit b72566a4ffaddbc0c0c1f6f5ee91b42ab13ff429:
Merge remote-tracking branch
'remotes/vivier2/tags/trivial-patches-pull-request' into staging (2018-12-19
15:31:02 +)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qem
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Logan Gunthorpe
Tested-by: Guenter Roeck
Tested-by: Andrea Bolognani
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/riscv/virt.c b
ned-off-by: Palmer Dabbelt
---
default-configs/riscv32-softmmu.mak | 3 +++
default-configs/riscv64-softmmu.mak | 3 +++
2 files changed, 6 insertions(+)
diff --git a/default-configs/riscv32-softmmu.mak
b/default-configs/riscv32-softmmu.mak
index c5ea36cba597..dbc93982848a 100644
--- a/default-confi
: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 18 +-
include/hw/riscv/sifive_u.h | 3 ++-
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index ef07df244241
Anup Patel
Signed-off-by: Anup Patel
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/pmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 03abd8fe5eb7..15a5366616bd 1
There's at least two of us that are paid to work on this.
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index d676c73f8840..317eff6cec4d 100644
--- a/MAINTAINERS
From: Alistair Francis
Connect the gpex PCIe device based on the device tree included in the
HiFive Unleashed ROM.
Signed-off-by: Alistair Francis
Signed-off-by: Logan Gunthorpe
Reviewed-by: Logan Gunthorpe
Tested-by: Guenter Roeck
Tested-by: Andrea Bolognani
Signed-off-by: Palmer Dabbelt
register.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Reported-by: Vincent Siles
Signed-off-by: Michael Clark
Reviewed-by: Alistair Francis
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_plic.c | 2 +-
1 file changed
From: Mao Zhongyi
Signed-off-by: Mao Zhongyi
Reviewed-by: Bastian Koppelmann
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a025a0a3baac
From: Michael Clark
Previously the second UARTs on the sifive_e and sifive_u machines
where disabled due to check-qtest-riscv32 and check-qtest-riscv64
failures. Recent changes in the QEMU core serial code have
resolved these failures so the second UARTs can be instantiated.
Cc: Palmer Dabbelt
up as the low order bits are
usually written first followed by the high order
bits meaning the high order bits contained an invalid
value between the timecmp_lo and timecmp_hi update.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Co-Authored-by: Johannes H
From: Michael Clark
Add carriage return that was erroneously removed
when converting to qemu_log. Change hard coded
core number to the actual hartid.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Alistair
.
Signed-off-by: Nathaniel Graff
Reviewed-by: Michael Clark
Reviewed-by: Alistair Francis
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_uart.c | 24 +++-
include/hw/riscv/sifive_uart.h | 3 +++
2 files changed, 22 insertions(+), 5
ned-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 5c41ee5017e4..849fa2e6311a 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_
From: Michael Clark
Use the new CSR read/modify/write interface to implement
atomic updates to mip/sip.
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 56
The following changes since commit 147923b1a901a0370f83a0f4c58ec1baffef22f0:
Merge remote-tracking branch 'remotes/kraxel/tags/usb-20190108-pull-request'
into staging (2019-01-08 16:07:32 +)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags
implement new CSR operations.
Signed-off-by: Michael Clark
Signed-off-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Palmer Dabbelt
---
target/riscv/Makefile.objs | 2 +-
target/riscv/cpu.h | 35 +-
target/riscv/cpu_helper.c | 4 +-
target/riscv/csr.c
From: Alistair Francis
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
default-configs/riscv32-softmmu.mak | 1 +
default-configs/riscv64-softmmu.mak | 1 +
2 files changed, 2 insertions(+)
diff --git a/default-configs/riscv32-softmmu.mak
b/default-configs/riscv32
ned-off-by: Palmer Dabbelt
---
target/riscv/cpu.c| 6 ++
target/riscv/cpu.h| 6 +-
target/riscv/cpu_helper.c | 3 +-
target/riscv/csr.c| 169 +-
4 files changed, 105 insertions(+), 79 deletions(-)
diff --git a/target/riscv/cpu.
The following changes since commit b72566a4ffaddbc0c0c1f6f5ee91b42ab13ff429:
Merge remote-tracking branch
'remotes/vivier2/tags/trivial-patches-pull-request' into staging (2018-12-19
15:31:02 +)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qem
ned-off-by: Palmer Dabbelt
---
default-configs/riscv32-softmmu.mak | 3 +++
default-configs/riscv64-softmmu.mak | 3 +++
2 files changed, 6 insertions(+)
diff --git a/default-configs/riscv32-softmmu.mak
b/default-configs/riscv32-softmmu.mak
index c5ea36cba597..dbc93982848a 100644
--- a/default-confi
: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 18 +-
include/hw/riscv/sifive_u.h | 3 ++-
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index ef07df244241
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Logan Gunthorpe
Tested-by: Guenter Roeck
Tested-by: Andrea Bolognani
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/riscv/virt.c b
up as the low order bits are
usually written first followed by the high order
bits meaning the high order bits contained an invalid
value between the timecmp_lo and timecmp_hi update.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Co-Authored-by: Johannes H
From: Alistair Francis
Increase the number of interrupts to match the HiFive Unleashed board.
Signed-off-by: Alistair Francis
Tested-by: Guenter Roeck
Tested-by: Andrea Bolognani
Signed-off-by: Palmer Dabbelt
---
include/hw/riscv/virt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion
From: Michael Clark
Previously the second UARTs on the sifive_e and sifive_u machines
where disabled due to check-qtest-riscv32 and check-qtest-riscv64
failures. Recent changes in the QEMU core serial code have
resolved these failures so the second UARTs can be instantiated.
Cc: Palmer Dabbelt
register.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Reported-by: Vincent Siles
Signed-off-by: Michael Clark
Reviewed-by: Alistair Francis
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_plic.c | 2 +-
1 file changed
.
Signed-off-by: Nathaniel Graff
Reviewed-by: Michael Clark
Reviewed-by: Alistair Francis
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_uart.c | 24 +++-
include/hw/riscv/sifive_uart.h | 3 +++
2 files changed, 22 insertions(+), 5
From: Alistair Francis
Connect the gpex PCIe device based on the device tree included in the
HiFive Unleashed ROM.
Signed-off-by: Alistair Francis
Signed-off-by: Logan Gunthorpe
Reviewed-by: Logan Gunthorpe
Tested-by: Guenter Roeck
Tested-by: Andrea Bolognani
Signed-off-by: Palmer Dabbelt
ned-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 5c41ee5017e4..849fa2e6311a 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_
From: Mao Zhongyi
Signed-off-by: Mao Zhongyi
Reviewed-by: Bastian Koppelmann
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a025a0a3baac
Anup Patel
Signed-off-by: Anup Patel
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/pmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 03abd8fe5eb7..15a5366616bd 1
There's at least two of us that are paid to work on this.
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index d676c73f8840..317eff6cec4d 100644
--- a/MAINTAINERS
From: Michael Clark
Add carriage return that was erroneously removed
when converting to qemu_log. Change hard coded
core number to the actual hartid.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Alistair
On Thu, 03 Jan 2019 08:46:11 PST (-0800), Peter Maydell wrote:
On Wed, 26 Dec 2018 at 17:20, Palmer Dabbelt wrote:
The following changes since commit b72566a4ffaddbc0c0c1f6f5ee91b42ab13ff429:
Merge remote-tracking branch
'remotes/vivier2/tags/trivial-patches-pull-request' in
On Tue, 08 Jan 2019 12:35:17 PST (-0800), jcmvb...@gmail.com wrote:
Hi Palmer,
On Tue, Jan 8, 2019 at 11:37 AM Palmer Dabbelt wrote:
It looks like I don't have an account and I'm supposed to ask on qemu-devel for
one.
I've created an account for you. Will send details in
On Wed, 09 Jan 2019 16:01:34 PST (-0800), Alistair Francis wrote:
Signed-off-by: Alistair Francis
---
default-configs/riscv32-softmmu.mak | 1 +
default-configs/riscv64-softmmu.mak | 1 +
2 files changed, 2 insertions(+)
diff --git a/default-configs/riscv32-softmmu.mak
b/default-configs/riscv
On Fri, 31 Aug 2018 15:22:49 PDT (-0700), c...@braap.org wrote:
On Fri, Aug 10, 2018 at 13:39:38 -0400, Emilio G. Cota wrote:
Changes wrt v1: changed patch 3 as suggested by Richard. Also
added his R-b's.
You can fetch this series from:
https://github.com/cota/qemu/tree/riscv-lookup_ptr-v2
nderstand this correctly, this will make host kernels older than 4.15.0
look like 4.15.0 when a program running in user-mode emulation on a RISC-V
system? I think that's the correct thing to do, so if that's the case then
feel free to add a
Reviewed-by: Palmer Dabbelt
if that helps any.
Thanks!
On Tue, 24 Apr 2018 12:07:43 PDT (-0700), peter.mayd...@linaro.org wrote:
On 24 April 2018 at 17:40, Palmer Dabbelt wrote:
On Tue, 24 Apr 2018 09:03:29 PDT (-0700), alex.ben...@linaro.org wrote:
As support was merged into the mainline kernel at 4.15 it is unlikely
3.8.0 is the correct value
On Wed, 25 Apr 2018 16:45:13 PDT (-0700), Michael Clark wrote:
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/translate.c b/target
On Fri, 22 Jun 2018 12:28:14 PDT (-0700), alistair.fran...@wdc.com wrote:
Alistair Francis (5):
hw/riscv/virtio: Set the soc device tree node as a simple-bus
hw/riscv/virt: Increase the number of interrupts
hw/riscv/virt: Connect the Xilinx PCIe
hw/riscv/virt: Connect a VGA PCIe device
On Fri, 29 Jun 2018 14:20:34 PDT (-0700), alistai...@gmail.com wrote:
On Fri, Jun 29, 2018 at 2:05 PM, G 3 wrote:
Hi, I noticed your RISC-V patches on the mailing list and had a question
that I think you may be able to answer. Has anyone defined a RISC-V platform
yet? What I mean is defining wh
On Mon, 09 Jul 2018 16:04:48 PDT (-0700), Michael Clark wrote:
On Tue, Jul 10, 2018 at 9:52 AM, Alistair Francis
wrote:
On Mon, Jul 9, 2018 at 3:00 AM, Andreas Schwab wrote:
> What is the state of the sifive_u emulation? When I tried to boot a bbl
> with an included kernel I get these errors
On Fri, 09 Mar 2018 13:49:57 PST (-0800), c...@braap.org wrote:
On Fri, Mar 09, 2018 at 11:34:56 +, Michael Clark wrote:
Isn't Cc'ing riscv-patches an obvious use case for using the --cc flag?
(BTW You can add as many --cc's as you want, and these apply to all patches
in a series.)
FWIW, th
On Wed, 10 Jan 2018 23:58:12 PST (-0800), h...@lst.de wrote:
On Wed, Jan 10, 2018 at 03:46:19PM -0800, Michael Clark wrote:
- RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
- RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1
- RISC-V Instruction Set Manual
On Thu, 11 Jan 2018 09:55:36 PST (-0800), Michael Clark wrote:
On Fri, Jan 12, 2018 at 3:37 AM, Richard Henderson <
richard.hender...@linaro.org> wrote:
On 01/10/2018 06:21 PM, Michael Clark wrote:
> +static inline void cpu_get_tb_cpu_state(CPURISCVState *env,
target_ulong *pc,
> +
From: Palmer Dabbelt
The RISC-V Linux port was recently accept upstream and will be released
as part of 4.15. While working on our glibc port I discovered that
qemu's user-mode emulation doesn't support renameat2, which has replaced
rename as part of the default system call li
On Thu, 21 Dec 2017 06:01:25 PST (-0800), peter.mayd...@linaro.org wrote:
On 20 December 2017 at 00:29, Palmer Dabbelt wrote:
+#if defined(TARGET_NR_renameat2) && defined(__NR_renameat2)
+case TARGET_NR_renameat2:
+{
+void *p2;
+p = lock_user_str
On Thu, 22 Mar 2018 15:17:16 PDT (-0700), d...@redhat.com wrote:
"Richard W.M. Jones" writes:
DJ, am I remembering correctly that you tried the test case on the
HiFive evaluation board and it didn't demonstrate the bug?
I tested it on the vc707 board, without seeing the bug.
FWIW, the cores
ng the FPU and set mstatus.FS to initial or
clean. With this workaround, mstatus.FS will always return
dirty if set to a non-zero value, indicating floating point
save restore is necessary, versus misreporting mstatus.FS
resulting in floating point register file corruption.
Cc: Palmer Dabbelt
On Thu, 08 Mar 2018 03:41:33 PST (-0800), Michael Clark wrote:
On Fri, 9 Mar 2018 at 12:18 AM, Michael Clark wrote:
On Fri, 9 Mar 2018 at 12:10 AM, Michael Clark wrote:
On Thu, 8 Mar 2018 at 11:02 PM, Peter Maydell
wrote:
On 6 March 2018 at 19:46, Michael Clark wrote:
You are making this
On Thu, 26 Mar 2020 15:44:04 PDT (-0700), Alistair Francis wrote:
This series fixes two bugs in the RISC-V two stage lookup
implementation. This fixes the Hypervisor userspace failing to start.
Alistair Francis (2):
riscv: Don't use stage-2 PTE lookup protection flags
riscv: AND stage-1 and
The following changes since commit 8b6b68e05b43f976714ca1d2afe01a64e1d82cba:
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
(2020-02-27 19:15:15 +)
are available in the Git repository at:
g...@github.com:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-sf3
f
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/translate.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d5de7f468a..eff064dc44 100644
From: Alistair Francis
The v0.5 Hypervisor spec add new execption numbers, let's add support
for those.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c| 8
target/riscv/cpu_bits.h
From: Alistair Francis
The MIP CSR is a xlen CSR, it was only 32-bits to allow atomic access.
Now that we don't use atomics for MIP we can change this back to a xlen
CSR.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Chih-Min Chao
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 95de9e58a2..010125efd6 100644
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 136 -
1 file changed, 134 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h| 4
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_helper.c | 18 ++
3 files changed, 25 insertions(+)
diff --git a
From: Alistair Francis
Update the CSR permission checking to work correctly when we are in
HS-mode.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions
From: Alistair Francis
Add the Hypervisor CSRs to CPUState and at the same time (to avoid
bisect issues) update the CSR macros for the v0.5 Hyp spec.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 21
From: Alistair Francis
Dump the Hypervisor registers and the current Hypervisor state.
While we are editing this code let's also dump stvec and scause.
Signed-off-by: Alistair Francis
Signed-off-by: Atish Patra
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/
: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h| 2 ++
target/riscv/cpu_bits.h | 6 ++
target/riscv/cpu_helper.c | 18 ++
3 files changed, 26 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 3fa8d2cfda..f7333286bd 100644
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 116 +
1 file changed, 116 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 6 +++---
target/riscv/cpu_bits.h | 12 ++--
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.c b/target
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h| 11 +++
target/riscv/cpu_bits.h | 7 +
target/riscv/cpu_helper.c | 61 +++
3 files changed, 79
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 918678789a..2e6700bbeb
From: Alistair Francis
To ensure our TLB isn't out-of-date we flush it on all virt mode
changes. Unlike priv mode this isn't saved in the mmu_idx as all
guests share V=1. The easiest option is just to flush on all changes.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/op_helper.c | 62 +---
1 file changed, 52 insertions(+), 10 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f7333286bd..c0e942684d 100644
--- a/target/riscv/csr.c
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 33 -
1 file changed, 28 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5b889a0065..aa04e5cca7 100644
--- a
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 37 -
1 file changed, 28 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 69 +--
1 file changed, 59 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/op_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index e87c9115bc
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 24
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index c0e942684d
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode| 23 ++-
.../riscv/insn_trans/trans_privileged.inc.c | 40 +++
2 files changed, 54 insertions(+), 9
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