Message-ID: <20230302091212.999767-4-suni...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 2 ++
include/hw/riscv/virt.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 90579a4c0e..aed303e1e6 100644
--- a/hw
From: Sunil V L
ACPI will be enabled by default. Add a switch to turn off
for testing and debug purposes.
Signed-off-by: Sunil V L
Reviewed-by: Andrew Jones
Message-ID: <20230302091212.999767-3-suni...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c
From: Sunil V L
Initialize the ACPI tables if the acpi option is not
disabled.
Signed-off-by: Sunil V L
Reviewed-by: Bin Meng
Reviewed-by: Andrew Jones
Message-ID: <20230302091212.999767-8-suni...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 4
1 file c
52.892893-5-alexgh...@rivosinc.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 93 ++
target/riscv/cpu.h | 8 +++-
2 files changed, 75 insertions(+), 26 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e1e8057836..1e97473af
From: Mayuresh Chitale
Implement the callback for getting the architecture-dependent CPU ID ie
mhartid.
Signed-off-by: Mayuresh Chitale
Signed-off-by: Anup Patel
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230303065055.915652-2-mchit...@ventanamicro.com>
Signed-off-by: Palmer D
nderson
Reviewed-by: Weiwei Li
Co-developed-by: Philipp Tomsich
Signed-off-by: Christoph Muellner
Signed-off-by: Daniel Henrique Barboza
Message-ID: <20230224132536.552293-4-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c
From: Sunil V L
RISC-V ACPI platforms need to provide RISC-V Hart Capabilities
Table (RHCT). Add this to the ACPI tables.
Signed-off-by: Sunil V L
Reviewed-by: Andrew Jones
Message-ID: <20230302091212.999767-7-suni...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/vir
From: Sunil V L
Add Multiple APIC Description Table (MADT) with the
RINTC structure for each cpu.
Signed-off-by: Sunil V L
Acked-by: Alistair Francis
Reviewed-by: Andrew Jones
Message-ID: <20230302091212.999767-6-suni...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
hw/risc
The following changes since commit 2946e1af2704bf6584f57d4e3aec49d1d5f3ecc0:
configure: Disable thread-safety warnings on macOS (2023-03-04 14:03:46 +)
are available in the Git repository at:
https://gitlab.com/palmer-dabbelt/qemu.git tags/pull-riscv-to-apply-20230306
for you to fetch
be replaced by
cpu_by_arch_id which performs lookup based on the sparse physical hart IDs.
Signed-off-by: Mayuresh Chitale
Signed-off-by: Anup Patel
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230303065055.915652-3-mchit...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
h
-build.c and enable
building this infrastructure.
Signed-off-by: Sunil V L
Reviewed-by: Andrew Jones
Message-ID: <20230302091212.999767-5-suni...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Kconfig | 1 +
hw/riscv/meson.build | 1 +
hw/riscv/virt-acpi-b
Message-ID: <20230303131252.892893-6-alexgh...@rivosinc.com>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 7f70fa11a1..26eb81d036 100644
--- a/hw/riscv/virt.
-developed-by: Philipp Tomsich
Signed-off-by: Christoph Muellner
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
Reviewed-by: Weiwei Li
Message-ID: <20230224132536.552293-5-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 1 +
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Bin Meng
Message-ID: <20230302091406.407824-2-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 4f81
7-2-suni...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 5 +
include/hw/riscv/virt.h | 2 ++
2 files changed, 7 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 26eb81d036..5a059489b5 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@
adictory configurations:
-cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme
Co-Developed-by: Ludovic Henry
Signed-off-by: Ludovic Henry
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Bin Meng
Acked-by: Alistair Francis
Reviewed-by: Frank Chang
Message-ID: <
derson
Co-developed-by: Philipp Tomsich
Signed-off-by: Christoph Muellner
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Message-ID: <20230224132536.552293-3-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 4
49-1-ivan.klo...@syntacore.com>
Signed-off-by: Palmer Dabbelt
---
disas/riscv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index ddda687c13..544558 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1645,7 +1645,7 @@ const rv_opcode_
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
Reviewed-by: Frank Chang
Message-ID: <20230303131252.892893-3-alexgh...@rivosinc.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/target
On Sat, 09 Sep 2023 00:18:02 PDT (-0700), pbonz...@redhat.com wrote:
Il sab 9 set 2023, 03:35 Atish Patra ha scritto:
On Fri, Sep 8, 2023 at 3:29 AM Paolo Bonzini wrote:
>
> Queued, thanks.
>
I didn't realize it was already queued. Gmail threads failed me this time.
@Paolo Bonzini : Can you
uc);
+pc = host_sigbus_handler(cpu, info, uc);
sync_sig = true;
break;
case SIGILL:
--
2.40.1
Either way,
Reviewed-by: Palmer Dabbelt
Thanks!
qemu.
>>
>> Â Â Â .text
>> ENTRY(__vdso_rt_sigreturn)
>> Â Â Â .cfi_startproc
>> Â Â Â .cfi_signal_frame
>> Â Â Â li a7, __NR_rt_sigreturn
>> Â Â Â ecall
>> Â Â Â .cfi_endproc
>> ENDPROC(__vdso_rt_sigreturn)
>
> Perhaps it'
Support for probing the Zicboz block size landed in Linux 6.6, which was
released a few weeks ago. This provides the user-configured block size
when Zicboz is enabled.
Signed-off-by: Palmer Dabbelt
---
linux-user/syscall.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/linux-user
On Thu, 26 Oct 2023 16:03:28 PDT (-0700), turt...@utexas.edu wrote:
From 4af1fca6e5c99578a5b80b834c22b70f6419639f Mon Sep 17 00:00:00 2001
From: Brendan Sweeney
Date: Thu, 26 Oct 2023 17:01:29 -0500
Subject: [PATCH] Support for the RISCV Zalasr extension
This doesn't have a commit body. At l
);
+}
+break;
+#endif
#ifdef TARGET_NR_mkdir
case TARGET_NR_mkdir:
if (!(p = lock_user_string(arg1)))
Thanks! My patch got lost in the shuffle, but I think these are functionally
identical. Feel free to add my
Reviewed-by: Palmer Dabbelt
On Tue, 23 Jan 2018 12:13:07 PST (-0800), laur...@vivier.eu wrote:
Le 23/01/2018 à 20:13, Palmer Dabbelt a écrit :
On Tue, 23 Jan 2018 06:48:07 PST (-0800), laur...@vivier.eu wrote:
From: Andreas Schwab
This is needed for new architectures like RISC-V which do not provide any
other rename
On Fri, 12 Jan 2018 00:09:16 PST (-0800), h...@lst.de wrote:
On Fri, Jan 12, 2018 at 07:24:54AM +1300, Michael Clark wrote:
I'm going to be restoring branches for bbl and riscv-linux that work again
priv 1.9.1. There are still other emulators and RTL that support priv1.9.1.
Folk will have silico
On Tue, 11 Dec 2018 14:37:07 PST (-0800), Alistair Francis wrote:
This series is now ready to be merged, all of the patches are reviewed
and tested.
Palmer can you take this with all the other RISC-V patches sent during
the freeze?
Yep, I'll be collecting everything this week.
Thanks!
V8:
ewed-by: Palmer Dabbelt
On Mon, 05 Nov 2018 09:00:10 PST (-0800), Bastian Koppelmann wrote:
On 11/1/18 4:59 PM, Palmer Dabbelt wrote:
On Wed, 31 Oct 2018 15:38:08 PDT (-0700), richard.hender...@linaro.org
wrote:
On 10/31/18 1:20 PM, Bastian Koppelmann wrote:
static bool trans_slt(DisasContext *ctx, arg_slt *a
On Tue, 06 Nov 2018 10:43:17 PST (-0800), Peter Maydell wrote:
I had an idea for how to get a rough list of source files
containing devices that haven't been QOMified. The theory
is that a pre-QOM device generally has an "init" function
which allocates memory for the device struct. So looking in
On Wed, 07 Nov 2018 13:51:45 PST (-0800), Alistair Francis wrote:
Signed-off-by: Alistair Francis
---
hw/riscv/virt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 4a137a503c..2b38f89070 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -240,6 +
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
hw/riscv/spike.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 8a712ed49026..268df04c3c7d 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -316,9 +316,7 @@ static
The following changes since commit a7ce790a029bd94eb320d8c69f38900f5233997e:
tcg/tcg-op.h: Add multiple include guard (2018-11-08 15:15:32 +)
are available in the Git repository at:
git://github.com/riscv/riscv-qemu.git tags/riscv-for-master-3.1-rc1
for you to fetch changes up to 00a014
On Thu, 08 Nov 2018 10:37:28 PST (-0800), alistai...@gmail.com wrote:
On Wed, Nov 7, 2018 at 6:38 PM Palmer Dabbelt wrote:
On Wed, 07 Nov 2018 13:51:45 PST (-0800), Alistair Francis wrote:
> Signed-off-by: Alistair Francis
> ---
> hw/riscv/virt.c | 1 +
> 1 file changed,
On Thu, 08 Nov 2018 10:38:51 PST (-0800), alistai...@gmail.com wrote:
On Thu, Nov 8, 2018 at 10:35 AM Palmer Dabbelt wrote:
The following changes since commit a7ce790a029bd94eb320d8c69f38900f5233997e:
tcg/tcg-op.h: Add multiple include guard (2018-11-08 15:15:32 +)
are available in
e(nodename);
>
> nodename = g_strdup_printf("/uart@%lx",
> (long)memmap[VIRT_UART0].base);
> --
> 2.19.1
>
Reviewed-by: Palmer Dabbelt
On Thu, 08 Nov 2018 09:29:26 PST (-0800), Bastian Koppelmann wrote:
On 11/8/18 4:53 PM, Richard Henderson wrote:
On 11/8/18 1:06 PM, Bastian Koppelmann wrote:
while going through the reviews of the riscv-decodetree patches, two bugs came
up that I fix here. There is one more problem [1] mentio
On Fri, 09 Nov 2018 02:53:45 PST (-0800), Peter Maydell wrote:
On 8 November 2018 at 18:52, Palmer Dabbelt wrote:
On Thu, 08 Nov 2018 10:38:51 PST (-0800), alistai...@gmail.com wrote:
On Thu, Nov 8, 2018 at 10:35 AM Palmer Dabbelt wrote:
The following changes since commit
I'd like to target this for 3.1: while it's a pretty esoteric bug the
risk of breaking anything is low and tracking down a manifestation of
the bug would be a nightmare.
I don't think the performance improvement alluded to will be a 3.1
candidiate, and as a result I probably won't get around to it
issues.
Signed-off-by: Palmer Dabbelt
---
target/riscv/translate.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 18d7b6d1471d..624d1c679a84 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1766,7 +1
Fix sfence.vm/a both available in any priv version
Palmer Dabbelt (1):
RISC-V: Respect fences for user-only emulators
hw/riscv/virt.c | 1 +
target/riscv/translate.c | 24
2 files changed, 17 insertions(+), 8 deletions(-)
From: Bastian Koppelmann
sfence.vm has been replaced in priv v1.10 spec by sfence.vma.
Reported-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Palmer Dabbelt
---
target/riscv/translate.c | 18 +-
1 file changed, 13
issues.
Signed-off-by: Palmer Dabbelt
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/translate.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f44eb9c41b48..312bf298b3c2 100644
--- a/target/riscv/tran
From: Alistair Francis
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 4a137a503c8a..2b38f890702c 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -240,6 +240,7
From: Bastian Koppelmann
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Palmer Dabbelt
---
target/riscv/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 18d7b6d1471d
From: Alistair Francis
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 4a137a503c8a..2b38f890702c 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -240,6 +240,7
From: Bastian Koppelmann
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Palmer Dabbelt
---
target/riscv/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 18d7b6d1471d
Fix sfence.vm/a both available in any priv version
Palmer Dabbelt (1):
RISC-V: Respect fences for user-only emulators
hw/riscv/virt.c | 1 +
target/riscv/translate.c | 24
2 files changed, 17 insertions(+), 8 deletions(-)
From: Bastian Koppelmann
sfence.vm has been replaced in priv v1.10 spec by sfence.vma.
Reported-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Palmer Dabbelt
---
target/riscv/translate.c | 18 +-
1 file changed, 13
issues.
Signed-off-by: Palmer Dabbelt
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/translate.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f44eb9c41b48..312bf298b3c2 100644
--- a/target/riscv/tran
On Mon, 08 Oct 2018 11:25:07 PDT (-0700), alistair.fran...@wdc.com wrote:
These are some patches that I have cherry picked from Michael's RISC-V
tree that are ready to be applied.
Unless anyone has any comments against these I'll send a PR later this
week.
Michael Clark (5):
RISC-V: Allow sett
On Wed, 10 Oct 2018 11:10:07 PDT (-0700), peter.mayd...@linaro.org wrote:
On 10 October 2018 at 18:49, Palmer Dabbelt wrote:
we should really
get the ball rolling on our big patch backlog.
Yes, please do. Softfreeze is not all that far away and I
would strongly prefer not to get an enormous
riscv_cpu_update_mip.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Alistair Francis
---
hw/riscv/sifive_clint.c | 8
hw/riscv/sifive_plic.c | 4 ++--
target/riscv/cpu.h | 22
interrupts.
* Remove erroneous until comments on machine mode interrupts.
* Move together paging mode and page table bit definitions.
* Move together interrupt and exception cause definitions.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Mic
On Mon, 08 Oct 2018 11:25:56 PDT (-0700), alistair.fran...@wdc.com wrote:
From: Michael Clark
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Alistair Francis
---
hw/riscv/sifive_u.c | 4 +++-
hw/riscv/spike.c| 6 --
hw/riscv/virt.c | 4
Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Alistair Francis
---
target/riscv/Makefile.objs | 2 +-
target/riscv/{helper.c => cpu_helper.c} | 35 -
target/riscv/op_helpe
On Mon, 08 Oct 2018 11:25:45 PDT (-0700), alistair.fran...@wdc.com wrote:
From: Michael Clark
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Alistair Francis
---
hw/riscv/virt.c | 2 ++
1 file changed, 2
On Thu, 11 Oct 2018 02:34:16 PDT (-0700), peter.mayd...@linaro.org wrote:
On 10 October 2018 at 19:22, Palmer Dabbelt wrote:
On Wed, 10 Oct 2018 11:10:07 PDT (-0700), peter.mayd...@linaro.org wrote:
On 10 October 2018 at 18:49, Palmer Dabbelt wrote:
we should really
get the ball rolling
On Fri, 12 Oct 2018 02:34:12 PDT (-0700), peter.mayd...@linaro.org wrote:
On 11 October 2018 at 21:52, Michael Clark wrote:
Peter, I have to pull in your remote wholesale. I don't cherry-pick from
your tree. I think this is truly dumb. This might serve the needs of some
folk running Linux but w
On Tue, 16 Oct 2018 01:05:11 PDT (-0700), peter.mayd...@linaro.org wrote:
On 15 October 2018 at 21:28, Palmer Dabbelt wrote:
On Fri, 12 Oct 2018 02:34:12 PDT (-0700), peter.mayd...@linaro.org wrote:
The expected patch flow for QEMU is:
* original patch author posts patch to qemu-devel
From: Michael Clark
Signed-off-by: Michael Clark
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Palmer Dabbelt
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/riscv
The following changes since commit 09558375a634e17cea6cfbfec883ac2376d2dc7f:
Merge remote-tracking branch
'remotes/pmaydell/tags/pull-target-arm-20181016-1' into staging (2018-10-16
17:42:56 +0100)
are available in the Git repository at:
git://github.com/riscv/riscv-qemu.git tags/riscv-for
-Daudé
Reviewed-by: Palmer Dabbelt
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/Makefile.objs | 2 +-
target/riscv/{helper.c => cpu_helper.c} | 35 -
target/riscv/op_helper.c| 34
Reviewed-by: Palmer Dabbelt
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_clint.c | 8
hw/riscv/sifive_plic.c | 4 ++--
target/riscv/cpu.h | 22 +-
target/riscv/op_helper.c | 24 +++-
4 files changed
From: Michael Clark
Signed-off-by: Michael Clark
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Palmer Dabbelt
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 4 +++-
hw/riscv/spike.c| 6 --
hw/riscv/virt.c
e together paging mode and page table bit definitions.
* Move together interrupt and exception cause definitions.
Signed-off-by: Michael Clark
Reviewed-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c
On Wed, 17 Oct 2018 16:32:10 PDT (-0700), ebl...@redhat.com wrote:
On 10/17/18 4:54 PM, Palmer Dabbelt wrote:
The following changes since commit 09558375a634e17cea6cfbfec883ac2376d2dc7f:
Merge remote-tracking branch
'remotes/pmaydell/tags/pull-target-arm-20181016-1' into stagin
lt
promotion rules will result in an integer here ("i*8" is integer, which flows
through) resulting in a 32-bit signed value on most hosts. That's obviously
bogus on RV64I, with the high bits of the CSR being wrong.
Aside from the metadata
Reviewed-by: Palmer Dabbelt
Thanks!
certainly don't want to step on your toes here, but I really would like to get
patches to start flowing upstream.
Sorry for the confusion, everyone!
On Thu, Oct 18, 2018 at 1:01 PM Palmer Dabbelt wrote:
On Wed, 17 Oct 2018 16:32:10 PDT (-0700), ebl...@redhat.com wrote:
> On 10/17
On Thu, 18 Oct 2018 18:05:45 PDT (-0700), c...@braap.org wrote:
Cc: Michael Clark
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Signed-off-by: Emilio G. Cota
---
target/riscv/op_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
On Thu, 18 Oct 2018 18:06:20 PDT (-0700), c...@braap.org wrote:
Soon we will call cpu_has_work without the BQL.
Cc: Michael Clark
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Emilio G. Cota
---
target/riscv/cpu.c | 21 -
1 file changed
On Fri, 19 Oct 2018 04:00:33 PDT (-0700), kbast...@mail.uni-paderborn.de wrote:
Hi Richard,
On 10/12/18 8:46 PM, Richard Henderson wrote:
On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
+static bool trans_andi(DisasContext *ctx, arg_andi *a, uint32_t insn)
+{
+gen_arith_imm(ctx, OPC_RISC_A
On Fri, 19 Oct 2018 08:28:38 PDT (-0700), kbast...@mail.uni-paderborn.de wrote:
On 10/13/18 8:53 PM, Richard Henderson wrote:
On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
+static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a, uint16_t insn)
+{
+if (a->imm == 0) {
+return tru
On Sat, 20 Oct 2018 00:14:22 PDT (-0700), kbast...@mail.uni-paderborn.de wrote:
Hi,
this patchset converts the RISC-V decoder to decodetree in three major steps:
1) Convert 32-bit instructions to decodetree [Patch 1-14]:
Many of the gen_* functions are called by the decode functions for 16-
On Sat, 20 Oct 2018 00:14:23 PDT (-0700), kbast...@mail.uni-paderborn.de wrote:
CPURISCVState is rarely used, so there is no need to pass it to every
translate function. This paves the way for decodetree which only passes
DisasContext to translate functions.
Signed-off-by: Bastian Koppelmann
--
decode_opc(DisasContext *ctx)
}
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 4;
-decode_RV32_64G(ctx->env, ctx);
+if (!decode_insn32(ctx, ctx->opcode)) {
+ /* fallback to old decoder */
+decode_RV32_64G(ctx->env, ctx);
+}
On Thu, 25 Oct 2018 09:54:56 PDT (-0700), Peter Maydell wrote:
On 25 October 2018 at 17:38, Palmer Dabbelt wrote:
On Sat, 20 Oct 2018 00:14:23 PDT (-0700), kbast...@mail.uni-paderborn.de
wrote:
CPURISCVState is rarely used, so there is no need to pass it to every
translate function. This
_JALR(ctx->opcode), rd, rs1, imm);
-break;
-case OPC_RISC_BRANCH:
-gen_branch(env, ctx, MASK_OP_BRANCH(ctx->opcode), rs1, rs2,
- GET_B_IMM(ctx->opcode));
- break;
case OPC_RISC_LOAD:
gen_load(ctx, MASK_OP_LOAD(ctx->opcode), rd, rs1, imm);
break;
Reviewed-by: Palmer Dabbelt
On Fri, 26 Oct 2018 07:53:17 PDT (-0700), Bastian Koppelmann wrote:
On 10/26/18 3:58 PM, Richard Henderson wrote:
On 10/26/18 11:49 AM, Bastian Koppelmann wrote:
I think you can pick up everything up to the RVC conversion which still needs
the work suggested by Richard. Thanks, for picking it
On Fri, 26 Oct 2018 03:53:11 PDT (-0700), kbast...@mail.uni-paderborn.de wrote:
On 10/25/18 12:21 AM, Palmer Dabbelt wrote:
On Sat, 20 Oct 2018 00:14:22 PDT (-0700),
kbast...@mail.uni-paderborn.de wrote:
Hi,
this patchset converts the RISC-V decoder to decodetree in three
major steps:
1
igned-off-by: Palmer Dabbelt
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d794bd7a66fe..d550fd8b809c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -241,6 +241,7 @@ F: disas/ppc.c
RISC-V
M: Michael Clark
M: Palmer Dabbelt
+M: Alistai
On Mon, 29 Oct 2018 09:30:54 PDT (-0700), phi...@redhat.com wrote:
On 29/10/18 17:16, Palmer Dabbelt wrote:
Alistair has been contributing to the RISC-V QEMU port for a while now
so I'd like him to be officially listed as a maintainer. I've checked
with the other RISC-V mainatiners
On Mon, 29 Oct 2018 09:48:30 PDT (-0700), alistai...@gmail.com wrote:
On Mon, Oct 29, 2018 at 9:44 AM Philippe Mathieu-Daudé
wrote:
On 29/10/18 17:16, Palmer Dabbelt wrote:
> Alistair has been contributing to the RISC-V QEMU port for a while now
> so I'd like him to be officially
On Mon, 29 Oct 2018 10:59:47 PDT (-0700), Peter Maydell wrote:
On 29 October 2018 at 17:14, Palmer Dabbelt wrote:
I don't think we have anything ready to go right now: your PCIe patches
still have some outstanding feedback (on interrupt stuff), and Bastian's
decodetree stuff has so
; That's bogus on RV64I, with the high bits of the CSR being wrong.
>
> Signed-off-by: Dayeol Lee
> Reviewed-by: Palmer Dabbelt
> ---
> target/riscv/pmp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
We now have a RISC-V specific QEMU development list.
Signed-off-by: Palmer Dabbelt
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d550fd8b809c..10983bd52d64 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -244,6 +244,7 @@ M: Palmer Dabbelt
M
, with the high bits of the CSR being wrong.
Signed-off-by: Dayeol Lee
Reviewed-by: Palmer Dabbelt
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/pmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
ind
igned-off-by: Palmer Dabbelt
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d794bd7a66fe..d550fd8b809c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -241,6 +241,7 @@ F: disas/ppc.c
RISC-V
M: Michael Clark
M: Palmer Dabbelt
+M: Alistai
We now have a RISC-V specific QEMU development list.
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Palmer Dabbelt
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
Dayeol Lee (1):
target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64
Palmer Dabbelt (2):
Add Alistair as a RISC-V Maintainer
Add qemu-ri...@nongnu.org as the RISC-V list
MAINTAINERS| 2 ++
target/riscv/pmp.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
On Tue, 30 Oct 2018 14:33:23 PDT (-0700), alistai...@gmail.com wrote:
On Tue, Oct 30, 2018 at 2:23 PM Palmer Dabbelt wrote:
Alistair has been contributing to the RISC-V QEMU port for a while now
so I'd like him to be officially listed as a maintainer. I've checked
with the ot
On Wed, 31 Oct 2018 03:44:27 PDT (-0700), Bastian Koppelmann wrote:
On 10/20/18 9:14 AM, Bastian Koppelmann wrote:
[...]
+static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+REQUIRE_FPU;
+
+TCGv t0 = tcg_temp_new();
+gen_hel
On Wed, 31 Oct 2018 15:38:08 PDT (-0700), richard.hender...@linaro.org wrote:
On 10/31/18 1:20 PM, Bastian Koppelmann wrote:
static bool trans_slt(DisasContext *ctx, arg_slt *a)
{
-gen_arith(ctx, OPC_RISC_SLT, a->rd, a->rs1, a->rs2);
+TCGv source1 = tcg_temp_new();
+TCGv source2 =
igned-off-by: Palmer Dabbelt
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d794bd7a66fe..d550fd8b809c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -241,6 +241,7 @@ F: disas/ppc.c
RISC-V
M: Michael Clark
M: Palmer Dabbelt
+M: Alistai
Alistair as
a RISC-V maintainer, and one to add our newly created mailing list.
Dayeol Lee (1):
target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64
Palmer Dabbelt (2):
Add Alistair as a RISC-V Maintainer
Add qemu
, with the high bits of the CSR being wrong.
Signed-off-by: Dayeol Lee
Reviewed-by: Palmer Dabbelt
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/pmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
ind
We now have a RISC-V specific QEMU development list.
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Palmer Dabbelt
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
I don't have anything in my patch queue for this week, so I don't plan on
sending a pull request. Let me know if I'm missing anything.
On Tue, 20 Nov 2018 17:15:11 PST (-0800), alistai...@gmail.com wrote:
On Fri, Nov 16, 2018 at 12:33 AM Richard Henderson
wrote:
On 11/15/18 11:35 PM, Alistair Francis wrote:
> +static void reloc_sbimm12(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
> +{
> +intptr_t offset = (intptr_t)tar
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