Signed-off-by: Michael Rolnik
---
arch_init.c | 2 +
configure | 7 +-
default-configs/avr-softmmu.mak | 21 +++
include/disas/bfd.h | 6 +
include/sysemu/arch_init.h | 1 +
target-avr/Makefile.objs| 23 +++
target-avr
Signed-off-by: Michael Rolnik
---
target-avr/cpu-qom.h | 2 +-
target-avr/cpu.c | 2 +-
target-avr/machine.c | 107 ---
3 files changed, 87 insertions(+), 24 deletions(-)
diff --git a/target-avr/cpu-qom.h b/target-avr/cpu-qom.h
index
Signed-off-by: Michael Rolnik
---
target-avr/cpugen/CMakeLists.txt | 38 +++
target-avr/cpugen/README.md| 17 ++
target-avr/cpugen/cpu/avr.yaml | 214 ++
target-avr/cpugen/src/CMakeLists.txt | 62
target-avr/cpugen/src/cpugen.cpp
Signed-off-by: Michael Rolnik
---
target-avr/helper.c | 59 -
1 file changed, 58 insertions(+), 1 deletion(-)
diff --git a/target-avr/helper.c b/target-avr/helper.c
index ad8f83e..f96fa27 100644
--- a/target-avr/helper.c
+++ b/target-avr
Signed-off-by: Michael Rolnik
---
configure | 2 +-
target-avr/gdbstub.c| 19 ++-
target-avr/translate-inst.c | 45 +
target-avr/translate.c | 5 -
4 files changed, 28 insertions(+), 43 deletions
Signed-off-by: Michael Rolnik
---
target-avr/translate-inst.c | 2624 +++
target-avr/translate.h | 119 ++
2 files changed, 2743 insertions(+)
create mode 100644 target-avr/translate-inst.c
create mode 100644 target-avr/translate.h
diff --git a
Signed-off-by: Michael Rolnik
---
hw/Makefile.objs | 1 +
hw/avr/Makefile.objs | 21 +
hw/avr/sample-io.c | 215 +++
hw/avr/sample.c | 118
4 files changed, 355 insertions(+)
create mode 100644 hw/avr
Signed-off-by: Michael Rolnik
---
target-avr/translate-inst.h | 762
1 file changed, 762 insertions(+)
create mode 100644 target-avr/translate-inst.h
diff --git a/target-avr/translate-inst.h b/target-avr/translate-inst.h
new file mode 100644
index
Signed-off-by: Michael Rolnik
---
target-avr/decode.c | 693
1 file changed, 693 insertions(+)
create mode 100644 target-avr/decode.c
diff --git a/target-avr/decode.c b/target-avr/decode.c
new file mode 100644
index 000..44a5815
--- /dev
and testing gen_push_ret/gen_pop_ret
changes since v7
1. folding back v6
2. logging at helper_outb and helper_inb are done for non supported yet
registers only
3. MAINTAINERS updated
Michael Rolnik (12):
target-avr: AVR cores support is added. 1. basic CPU
structure 2.
Signed-off-by: Michael Rolnik
---
hw/Makefile.objs | 1 +
hw/avr/Makefile.objs | 21 +
hw/avr/sample-io.c | 215 +++
hw/avr/sample.c | 118
4 files changed, 355 insertions(+)
create mode 100644 hw/avr
Signed-off-by: Michael Rolnik
---
target-avr/decode.c | 693
1 file changed, 693 insertions(+)
create mode 100644 target-avr/decode.c
diff --git a/target-avr/decode.c b/target-avr/decode.c
new file mode 100644
index 000..44a5815
--- /dev
Signed-off-by: Michael Rolnik
---
target-avr/translate-inst.h | 762
1 file changed, 762 insertions(+)
create mode 100644 target-avr/translate-inst.h
diff --git a/target-avr/translate-inst.h b/target-avr/translate-inst.h
new file mode 100644
index
Signed-off-by: Michael Rolnik
---
target-avr/helper.c | 147
target-avr/helper.h | 5 ++
2 files changed, 142 insertions(+), 10 deletions(-)
diff --git a/target-avr/helper.c b/target-avr/helper.c
index f96fa27..44d8f44 100644
--- a/target
Signed-off-by: Michael Rolnik
---
arch_init.c | 2 +
configure | 5 +
default-configs/avr-softmmu.mak | 21 +++
include/disas/bfd.h | 6 +
include/sysemu/arch_init.h | 1 +
target-avr/Makefile.objs| 23 +++
target-avr
Signed-off-by: Michael Rolnik
---
target-avr/cpu.c | 307 ++-
target-avr/cpu.h | 53 ++
2 files changed, 359 insertions(+), 1 deletion(-)
diff --git a/target-avr/cpu.c b/target-avr/cpu.c
index 99bd788..197f9ac 100644
--- a/target-avr
Signed-off-by: Michael Rolnik
---
target-avr/cpugen/CMakeLists.txt | 38 +++
target-avr/cpugen/README.md| 17 ++
target-avr/cpugen/cpu/avr.yaml | 214 ++
target-avr/cpugen/src/CMakeLists.txt | 62
target-avr/cpugen/src/cpugen.cpp
Signed-off-by: Michael Rolnik
---
target-avr/cpu-qom.h | 2 +-
target-avr/cpu.c | 2 +-
target-avr/machine.c | 107 ---
3 files changed, 87 insertions(+), 24 deletions(-)
diff --git a/target-avr/cpu-qom.h b/target-avr/cpu-qom.h
index
Signed-off-by: Michael Rolnik
---
target-avr/Makefile.objs | 4 +-
target-avr/translate.c | 137 ---
2 files changed, 61 insertions(+), 80 deletions(-)
diff --git a/target-avr/Makefile.objs b/target-avr/Makefile.objs
index 2a10104..9757721 100644
Signed-off-by: Michael Rolnik
---
target-avr/helper.c | 59 -
1 file changed, 58 insertions(+), 1 deletion(-)
diff --git a/target-avr/helper.c b/target-avr/helper.c
index ad8f83e..f96fa27 100644
--- a/target-avr/helper.c
+++ b/target-avr
Signed-off-by: Michael Rolnik
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index fe2279e..6a4e398 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -110,6 +110,12 @@ F: disas/arm.c
F: disas/arm-a64.cc
F: disas/libvixl/
+AVR
+M: Michael
Signed-off-by: Michael Rolnik
---
target-avr/translate-inst.c | 2629 +++
target-avr/translate.h | 119 ++
2 files changed, 2748 insertions(+)
create mode 100644 target-avr/translate-inst.c
create mode 100644 target-avr/translate.h
diff --git a
it did compile for me.
how do you compile? what machine?
On Sun, Jun 19, 2016 at 8:45 PM, Richard Henderson wrote:
> On 06/18/2016 12:55 PM, Michael Rolnik wrote:
>
>> This series of patches adds 8bit AVR cores to QEMU.
>> All instruction, except BREAK/DES/SPM/SPMX, are impl
I am building on MAC.
I just do
./configure --target-list=avr-softmmu
build
no errors
On Sun, Jun 19, 2016 at 8:50 PM, Michael Rolnik wrote:
> it did compile for me.
> how do you compile? what machine?
>
> On Sun, Jun 19, 2016 at 8:45 PM, Richard Henderson
> wrote:
>
>>
Signed-off-by: Michael Rolnik
---
target-avr/helper.c | 59 -
1 file changed, 58 insertions(+), 1 deletion(-)
diff --git a/target-avr/helper.c b/target-avr/helper.c
index 3e23646..060b2f0 100644
--- a/target-avr/helper.c
+++ b/target-avr
3. testing on
a. Mac, Apple LLVM version 7.0.0
b. Ubuntu 12.04, gcc 4.9.2
c. Fedora 23, gcc 5.3.1
4. folding back some patches
5. translation bug fixes for ADIW, SBIW, XOR instructions
6. propper handling of cpu register writes though memory
Michael Rolnik (10):
target-avr: AVR cores sup
Signed-off-by: Michael Rolnik
---
arch_init.c | 2 +
configure | 5 +
default-configs/avr-softmmu.mak | 21 +++
include/disas/bfd.h | 6 +
include/sysemu/arch_init.h | 1 +
target-avr/Makefile.objs| 23 +++
target-avr
Signed-off-by: Michael Rolnik
---
target-avr/translate-inst.h | 762
1 file changed, 762 insertions(+)
create mode 100644 target-avr/translate-inst.h
diff --git a/target-avr/translate-inst.h b/target-avr/translate-inst.h
new file mode 100644
index
Signed-off-by: Michael Rolnik
---
MAINTAINERS | 6 ++
hw/avr/Makefile.objs | 21 +
hw/avr/sample-io.c | 227 +++
hw/avr/sample.c | 116 ++
4 files changed, 370 insertions(+)
create mode 100644 hw/avr
Signed-off-by: Michael Rolnik
---
target-avr/cpu.c | 307 ++-
target-avr/cpu.h | 53 +
target-avr/machine.c | 1 +
3 files changed, 360 insertions(+), 1 deletion(-)
diff --git a/target-avr/cpu.c b/target-avr/cpu.c
index 1fdc1e6
Signed-off-by: Michael Rolnik
---
target-avr/decode.c | 693
1 file changed, 693 insertions(+)
create mode 100644 target-avr/decode.c
diff --git a/target-avr/decode.c b/target-avr/decode.c
new file mode 100644
index 000..44a5815
--- /dev
Signed-off-by: Michael Rolnik
---
target-avr/helper.c | 222 +---
target-avr/helper.h | 6 ++
2 files changed, 215 insertions(+), 13 deletions(-)
diff --git a/target-avr/helper.c b/target-avr/helper.c
index 060b2f0..1a324cb 100644
--- a/target
Signed-off-by: Michael Rolnik
---
target-avr/Makefile.objs | 4 +-
target-avr/translate.c | 142 ---
2 files changed, 64 insertions(+), 82 deletions(-)
diff --git a/target-avr/Makefile.objs b/target-avr/Makefile.objs
index 2a10104..9757721 100644
Signed-off-by: Michael Rolnik
---
target-avr/cpugen/CMakeLists.txt | 38 +++
target-avr/cpugen/README.md| 17 ++
target-avr/cpugen/cpu/avr.yaml | 214 ++
target-avr/cpugen/src/CMakeLists.txt | 62
target-avr/cpugen/src/cpugen.cpp
Signed-off-by: Michael Rolnik
---
target-avr/translate-inst.c | 2636 +++
target-avr/translate.h | 119 ++
2 files changed, 2755 insertions(+)
create mode 100644 target-avr/translate-inst.c
create mode 100644 target-avr/translate.h
diff --git a
Reviewed-by: Michael Rolnik
On Sat, Nov 19, 2022 at 7:56 AM Pavel Dovgalyuk
wrote:
> Bit vector for features has 64 bits. This patch fixes bit shifts in
> avr_feature and set_avr_feature functions to be 64-bit too.
>
> Signed-off-by: Pavel Dovgalyuk
> ---
> target/avr/cpu.
Hi Richard.
I can maintain it
Sent from my cell phone, please ignore typos
On Sun, May 5, 2019, 8:57 AM Richard Henderson
wrote:
> On 5/4/19 1:36 AM, Sarah Harris wrote:
> > Signed-off-by: Sarah Harris
> ...
> >
> > +AVR
> > +M: Michael Rolnik
> > +S:
', 'moxie', 'nios2', 'or1k', 'ppc',
> > 'ppc64', 'riscv32', 'riscv64', 's390x', 'sh4',
>
> Missing documentation that the new 'avr' member is available only since
&g
From: Sarah Harris
This includes:
- TCG translations for each instruction
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 2937
1 file changed, 2937 insertions(+)
create mode 100644 target/avr/translate.c
diff --git a/target/avr
From: Sarah Harris
This includes:
- CPU data structures
- object model classes and functions
- migration functions
- GDB hooks
Signed-off-by: Michael Rolnik
---
target/avr/cpu-qom.h | 83 +++
target/avr/cpu.c | 558 +++
target/avr/cpu.h
From: Sarah Harris
A simple board setup that configures an AVR CPU to run a given firmware image.
This is all that's useful to implement without peripheral emulation as AVR CPUs
include a lot of on-board peripherals.
Signed-off-by: Michael Rolnik
---
hw/Kconfig | 1 +
h
-off-by: Michael Rolnik
---
hw/char/Kconfig| 3 +
hw/char/Makefile.objs | 1 +
hw/char/avr_usart.c| 316 ++
hw/timer/Kconfig | 3 +
hw/timer/Makefile.objs | 1 +
hw/timer/avr_timer16.c | 587
wake interrupts.
Memory access instructions are implemented here because some address ranges
actually refer to CPU registers.
Signed-off-by: Michael Rolnik
---
target/avr/helper.c | 354
target/avr/helper.h | 29
2 files changed, 383 insertions
This includes:
- encoding of all 16 bit instructions
- encoding of all 32 bit instructions
Signed-off-by: Michael Rolnik
---
target/avr/insn.decode | 176 +
1 file changed, 176 insertions(+)
create mode 100644 target/avr/insn.decode
diff --git a/target
convention
2. merging insn16.decode & insn32.decode files
3. modifying skip next instruction mechanizm
4. translate BREAK as NOP for now
*** BLURB HERE ***
Michael Rolnik (1):
target/avr: Add instruction decoding
Sarah Harris (6):
target/avr: Add outward facing interfaces and core CPU logi
From: Sarah Harris
Signed-off-by: Michael Rolnik
---
MAINTAINERS | 6 ++
arch_init.c | 2 ++
configure | 6 ++
default-configs/avr-softmmu.mak | 5 +
include/disas/dis-asm.h | 6 ++
include/sysemu
Hi Richard.
I merged all you fixes and I get an assert(use_icount) in cpu_loop_exec_tb
function, it happens on an instruction following SBRC.
what might cause it?
On Tue, Jun 11, 2019 at 12:20 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 6/6/19 12:30 PM, Michael Rol
org> wrote:
> On 6/11/19 1:21 PM, Michael Rolnik wrote:
> > I merged all you fixes and I get an assert(use_icount)
> in cpu_loop_exec_tb
> > function, it happens on an instruction following SBRC.
> > what might cause it?
>
> No idea. What is your test case? And
From: Sarah Harris
This includes:
- CPU data structures
- object model classes and functions
- migration functions
- GDB hooks
Signed-off-by: Michael Rolnik
---
gdb-xml/avr-cpu.xml| 49
target/avr/cpu-param.h | 37 +++
target/avr/cpu.c | 599
This includes:
- TCG translations for each instruction
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 2886
1 file changed, 2886 insertions(+)
create mode 100644 target/avr/translate.c
diff --git a/target/avr/translate.c b/target/avr
aro.org
2. Drop cpc and fix page cross condition.
by richard.hender...@linaro.org
3. Refactor checking supported/unsupported instructions
4. Add gdb-xml/avr-cpu.xml
Michael Rolnik (2):
target/avr: Add instruction decoding
target/avr: Add instruction translation
Sarah Harris (5):
From: Sarah Harris
Signed-off-by: Michael Rolnik
---
MAINTAINERS | 6 ++
arch_init.c | 2 ++
configure | 7 +++
default-configs/avr-softmmu.mak | 5 +
include/disas/dis-asm.h | 6 ++
include/sysemu
wake interrupts.
Memory access instructions are implemented here because some address ranges
actually refer to CPU registers.
Signed-off-by: Michael Rolnik
---
target/avr/helper.c | 354
target/avr/helper.h | 29
2 files changed, 383 insertions
From: Sarah Harris
A simple board setup that configures an AVR CPU to run a given firmware image.
This is all that's useful to implement without peripheral emulation as AVR CPUs
include a lot of on-board peripherals.
Signed-off-by: Michael Rolnik
---
hw/Kconfig | 1 +
h
This includes:
- encoding of all 16 bit instructions
- encoding of all 32 bit instructions
Signed-off-by: Michael Rolnik
---
target/avr/insn.decode | 175 +
1 file changed, 175 insertions(+)
create mode 100644 target/avr/insn.decode
diff --git a/target
-off-by: Michael Rolnik
---
hw/char/Kconfig| 3 +
hw/char/Makefile.objs | 1 +
hw/char/avr_usart.c| 316 ++
hw/timer/Kconfig | 3 +
hw/timer/Makefile.objs | 1 +
hw/timer/avr_timer16.c | 587
Signed-off-by: Michael Rolnik
---
MAINTAINERS | 9 +
arch_init.c | 2 ++
configure | 7 +++
default-configs/avr-softmmu.mak | 5 +
include/disas/dis-asm.h | 6 ++
include/sysemu/arch_init.h | 1
ince' instread of 'added in'
changes since v30
1. rebase
changes since v31
1. splitting 'Add instruction translation' commit
2. fixing typo in qapi/machine.json sicne -> since
3. removing unintended changes in configure file
4. adding Richard Henderson as a co developer to
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 132 +
1 file changed, 132 insertions(+)
create mode 100644 target/avr/translate.c
diff --git a/target/avr/translate.c b/target/avr/translate.c
new file mode 100644
index 00..53c9892a60
This includes:
- ADD, ADC, ADIW
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 811 +
1 file changed, 811 insertions(+)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 53c9892a60..3eaa3e5099 100644
--- a/target/avr
This includes:
- BREAK
- NOP
- SLEEP
- WDR
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 174 +
1 file changed, 174 insertions(+)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 19540634df..21ba6004ee
0,0 +1,282 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the L
On Thu, Oct 17, 2019 at 8:25 PM Aleksandar Markovic
wrote:
>
>
>
> On Monday, October 14, 2019, Michael Rolnik wrote:
>>
>> Signed-off-by: Michael Rolnik
>> ---
>> target/avr/translate.c | 132 +
>> 1 file
nt singlestep;
>> >> +
>> >> +TCGv skip_var0;
>> >> + TCGv skip_var1;
>> >> +TCGCond skip_cond;
>> >> +bool free_skip_var0;
>> >> +};
>> >> +
>> >> +static int to_A(DisasContext *ctx, int indx) { return 16 + (indx % 16); }
>> >> +static int to_B(DisasContext *ctx, int indx) { return 16 + (indx % 8); }
>> >> +static int to_C(DisasContext *ctx, int indx) { return 24 + (indx % 4) *
>> >> 2; }
>> >> +static int to_D(DisasContext *ctx, int indx) { return (indx % 16) * 2; }
>> >> +
>> >> +static uint16_t next_word(DisasContext *ctx)
>> >> +{
>> >> +return cpu_lduw_code(ctx->env, ctx->npc++ * 2);
>> >> +}
>> >> +
>> >> +static int append_16(DisasContext *ctx, int x)
>> >> +{
>> >> +return x << 16 | next_word(ctx);
>> >> +}
>> >> +
>> >> +
>> >> +static bool avr_have_feature(DisasContext *ctx, int feature)
>> >> +{
>> >> +if (!avr_feature(ctx->env, feature)) {
>> >> +gen_helper_unsupported(cpu_env);
>> >> +ctx->bstate = DISAS_NORETURN;
>> >> +return false;
>> >> +}
>> >> +return true;
>> >> +}
>> >> +
>> >> +static bool decode_insn(DisasContext *ctx, uint16_t insn);
>> >> +#include "decode_insn.inc.c"
>> >> +
>> >> --
>> >> 2.17.2 (Apple Git-113)
>> >>
>>
>>
>> --
>> Best Regards,
>> Michael Rolnik
--
Best Regards,
Michael Rolnik
On Fri, Oct 18, 2019 at 11:52 AM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Thursday, October 17, 2019, Michael Rolnik wrote:
>
>> On Thu, Oct 17, 2019 at 11:17 PM Aleksandar Markovic
>> wrote:
>> >>
>> >>
>
resending.
On Fri, Oct 18, 2019 at 2:27 PM Michael Rolnik wrote:
>
>
>
> On Fri, Oct 18, 2019 at 11:52 AM Aleksandar Markovic
> wrote:
>>
>>
>>
>> On Thursday, October 17, 2019, Michael Rolnik wrote:
>>>
>>> On Thu
On Fri, Oct 18, 2019 at 4:23 PM Aleksandar Markovic
wrote:
>
>
>
> On Friday, October 18, 2019, Michael Rolnik wrote:
>>
>>
>>
>> On Fri, Oct 18, 2019 at 11:52 AM Aleksandar Markovic
>> wrote:
>>>
>>>
>>>
>>> On Thu
On Fri, Oct 18, 2019 at 9:08 PM Aleksandar Markovic
wrote:
>
>
>
> On Friday, October 18, 2019, Aleksandar Markovic
> wrote:
>>
>>
>>
>> On Friday, October 18, 2019, Michael Rolnik wrote:
>>>
>>> On Fri, Oct 18, 2019 at 4:23 PM Aleksand
This includes:
- CPU data structures
- object model classes and functions
- migration functions
- GDB hooks
Co-developed-by: Michael Rolnik
Co-developed-by: Sarah Harris
Signed-off-by: Michael Rolnik
Signed-off-by: Sarah Harris
Signed-off-by: Michael Rolnik
Acked-by: Igor Mammedov
---
gdb
This includes:
- encoding of all 16 bit instructions
- encoding of all 32 bit instructions
Signed-off-by: Michael Rolnik
---
target/avr/insn.decode | 175 +
1 file changed, 175 insertions(+)
create mode 100644 target/avr/insn.decode
diff --git a/target
#x27;Add instruction translation
- CPU main translation funcions' commit
changes since v32
1. modify cpu_get_sreg to treat sreg C as other flags, except sreg Z
Michael Rolnik (12):
target/avr: Add outward facing interfaces and core CPU logic
target/avr: Add instruction helpers
This includes:
- BREAK
- NOP
- SLEEP
- WDR
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 174 +
1 file changed, 174 insertions(+)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 19540634df..21ba6004ee
access instructions are implemented here because some address ranges
actually refer to CPU registers.
Signed-off-by: Michael Rolnik
---
target/avr/helper.c | 354
target/avr/helper.h | 29
2 files changed, 383 insertions(+)
create mode 100644
#x27;T' through serial port
Signed-off-by: Michael Rolnik
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Acked-by: Thomas Huth
---
tests/Makefile.include | 2 ++
tests/acceptance/machine_avr6.py | 36
tests/boot-serial
Co-developed-by: Richard Henderson
Co-developed-by: Michael Rolnik
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 234 +
1 file changed, 234 insertions(+)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 21ba6004ee
Signed-off-by: Michael Rolnik
---
target/avr/cpu.h | 2 +-
target/avr/translate.c | 132 +
2 files changed, 133 insertions(+), 1 deletion(-)
create mode 100644 target/avr/translate.c
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index
This includes:
- RJMP, IJMP, EIJMP, JMP
- RCALL, ICALL, EICALL, CALL
- RET, RETI
- CPSE, CP, CPC, CPI
- SBRC, SBRS, SBIC, SBIS
- BRBC, BRBS
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 542 +
1 file changed, 542
This includes:
- ADD, ADC, ADIW
- SBIW, SUB, SUBI, SBC, SBCI
- AND, ANDI
- OR, ORI, EOR
- COM, NEG
- INC, DEC
- MUL, MULS, MULSU
- FMUL, FMULS, FMULSU
- DES
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 811 +
1 file changed, 811 insertions
Signed-off-by: Michael Rolnik
---
MAINTAINERS | 9 +
arch_init.c | 2 ++
configure | 7 +++
default-configs/avr-softmmu.mak | 5 +
include/disas/dis-asm.h | 6 ++
include/sysemu/arch_init.h | 1
This includes:
- LSR, ROR
- ASR
- SWAP
- SBI, CBI
- BST, BLD
- BSET, BCLR
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 1123
1 file changed, 1123 insertions(+)
diff --git a/target/avr/translate.c b/target/avr
0,0 +1,282 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the L
config UNIMP
bool
+config AVR_MASK
+bool
+
source macio/Kconfig
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index a150680966..946bfc396d 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -80,3 +80,5 @@ common-obj-$(CONFIG_MSF2) += msf2-sysreg.o
common-
this revision has a bug, flag C is not calculated correctly.
On Tue, Oct 22, 2019 at 1:37 AM Michael Rolnik wrote:
>
> This series of patches adds 8bit AVR cores to QEMU.
> All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested
> yet.
> However I was
Hi Aleksandar.
I am fixing flag C and I will make flag Z to be like the others, just once
bit
Sent from my cell phone, please ignore typos
On Tue, Oct 22, 2019, 1:37 AM Michael Rolnik wrote:
> This includes:
> - CPU data structures
> - object model classes and functions
>
Hi all.
How is it going?
Regards,
Michael.
On Mon, Feb 10, 2020 at 9:39 AM Michael Rolnik wrote:
> Hi all.
>
> When I decided to implement AVR 8 bit CPU support for QEMU I found this
> document
> <http://ww1.microchip.com/downloads/en/devicedoc/atmel-0856-avr-instruct
I think they do follow the division in the docs.
On Thu, Dec 5, 2019 at 2:28 PM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Wednesday, November 27, 2019, Michael Rolnik wrote:
>
>> This includes:
>> - LSR, ROR
>> - ASR
>>
my mistake. Thanks. I will split it.
On Thu, Dec 5, 2019 at 3:17 PM Michael Rolnik wrote:
> I think they do follow the division in the docs.
>
> On Thu, Dec 5, 2019 at 2:28 PM Aleksandar Markovic <
> aleksandar.m.m...@gmail.com> wrote:
>
>>
>>
>> On Wedne
Ok, understood.
On Thu, Dec 5, 2019 at 8:45 PM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Tuesday, October 29, 2019, Michael Rolnik wrote:
>
>> From: Sarah Harris
>>
>> These were designed to facilitate testing but should provide enou
access instructions are implemented here because some address ranges
actually refer to CPU registers.
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
---
target/avr/helper.h | 29
target/avr/helper.c | 347
2 files changed, 376
This includes:
- encoding of all 16 bit instructions
- encoding of all 32 bit instructions
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
---
target/avr/insn.decode | 194 +
1 file changed, 194 insertions(+)
create mode 100644 target
unnecessary includes from target/avr/helper.c file
8. remove empty lines from target/avr/translate.c file
9. set number of interrupt lines to 64
10. determine cpu type by reading ELF flags
11. update license of all new files to be LGPL
12. udpate QEMU documentation
Michael Rolnik (22):
target/avr: A
This includes:
- ADD, ADC, ADIW
- SBIW, SUB, SUBI, SBC, SBCI
- AND, ANDI
- OR, ORI, EOR
- COM, NEG
- INC, DEC
- MUL, MULS, MULSU
- FMUL, FMULS, FMULSU
- DES
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
---
target/avr/translate.c | 734
This includes:
- RJMP, IJMP, EIJMP, JMP
- RCALL, ICALL, EICALL, CALL
- RET, RETI
- CPSE, CP, CPC, CPI
- SBRC, SBRS, SBIC, SBIS
- BRBC, BRBS
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
---
target/avr/translate.c | 537
, r24
0x04c2: RET
...
```
Signed-off-by: Michael Rolnik
Suggested-by: Richard Henderson
Suggested-by: Philippe Mathieu-Daudé
Suggested-by: Aleksandar Markovic
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
---
target/avr/cpu.h | 1 +
target/avr/cpu.c
This includes:
- CPU data structures
- object model classes and functions
- migration functions
- GDB hooks
Co-developed-by: Michael Rolnik
Co-developed-by: Sarah Harris
Signed-off-by: Michael Rolnik
Signed-off-by: Sarah Harris
Signed-off-by: Michael Rolnik
Acked-by: Igor Mammedov
Tested-by
Co-developed-by: Richard Henderson
Co-developed-by: Michael Rolnik
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
---
target/avr/translate.c | 234 +
1 file changed, 234 insertions(+)
diff --git a/target/avr/translate.c b/target/avr
This includes:
- BREAK
- NOP
- SLEEP
- WDR
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 174 +
1 file changed, 174 insertions(+)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index d8d8f11933..68025112ff
Signed-off-by: Michael Rolnik
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
---
target/avr/translate.c | 143 +
1 file changed, 143 insertions(+)
create mode 100644 target/avr/translate.c
diff --git a/target/avr/translate.c b
These were designed to facilitate testing but should provide enough function to
be useful in other contexts.
Only a subset of the functions of each peripheral is implemented, mainly due to
the lack of a standard way to handle electrical connections (like GPIO pins).
Signed-off-by: Sarah Harris
Signed-off-by: Michael Rolnik
---
include/hw/misc/avr_mask.h | 47
hw/misc/avr_mask.c | 112 +
hw/misc/Kconfig| 3 +
hw/misc/Makefile.objs | 2 +
4 files changed, 164 insertions(+)
create mode 100644 include/hw
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