> On 27 Jul 2017, at 8:58 AM, kr...@berkeley.edu wrote:
>
>
> Given that one of the goals of RISC-V is extensibility, it would be
> nice if the QEMU port was done in a way to make it easier to extend by
> third parties, including other automated tools. I'm sure that, over
> time, the preprocess
On Wed, Jan 3, 2018 at 12:10 PM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 01/02/2018 04:44 PM, Michael Clark wrote:
> > +/* convert RISC-V rounding mode to IEEE library numbers */
> > +unsigned int ieee_rm[] = {
>
> static const.
Done.
>
On Wed, Jan 3, 2018 at 12:10 PM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 01/02/2018 04:44 PM, Michael Clark wrote:
> > +/* convert RISC-V rounding mode to IEEE library numbers */
> > +unsigned int ieee_rm[] = {
>
> static const.
>
>
On Tue, Jan 23, 2018 at 3:15 PM, Michael Clark wrote:
>
>
> On Wed, Jan 3, 2018 at 12:10 PM, Richard Henderson <
> richard.hender...@linaro.org> wrote:
>
>> On 01/02/2018 04:44 PM, Michael Clark wrote:
>> > +/* convert RISC-V rounding mode to IEEE library n
On Tue, Jan 23, 2018 at 4:01 PM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 01/23/2018 01:37 PM, Michael Clark wrote:
> >
> >
> > On Wed, Jan 3, 2018 at 12:10 PM, Richard Henderson
> > mailto:richard.hender...@linaro.org>>
> wrote:
&
On Wed, Jan 24, 2018 at 8:16 AM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 01/23/2018 05:31 PM, Michael Clark wrote:
> > For the meantime we've greatly simplified cpu_mmu_index to just return
> the
> > processor mode as well as
On Mon, Jan 15, 2018 at 5:44 AM, Igor Mammedov wrote:
> On Wed, 10 Jan 2018 15:46:22 -0800
> Michael Clark wrote:
>
> > Add CPU state header, CPU definitions and initialization routines
> >
> > Signed-off-by: Michael Clark
> > ---
&
On Mon, Jan 29, 2018 at 12:33 PM, Jim Wilson wrote:
> On Wed, Jan 24, 2018 at 3:47 PM, Richard Henderson
> wrote:
> > On 01/24/2018 10:58 AM, Jim Wilson wrote:
> >> Although, looking at this again, I see another statement in a
> >> different place that says:
> >>
> >> Except when otherwise state
On Fri, Jan 5, 2018 at 7:22 PM, Michael Clark wrote:
>
> On Fri, 5 Jan 2018 at 5:55 AM, Antony Pavlov
> wrote:
>
>> On Wed, 3 Jan 2018 13:44:25 +1300
>> Michael Clark wrote:
>>
>> > This adds RISC-V into the build system enabling the followi
s I wrote, however perhaps thats just a matter
style with respect to writing (or re-writing) history.
Reviewed-by: Michael Clark
---
> target/riscv/translate.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index f
On Wed, Nov 14, 2018 at 12:52 PM Palmer Dabbelt wrote:
> The following changes since commit
> cb968d275c145467c8b385a3618a207ec111eab1:
>
> Update version for v3.1.0-rc1 release (2018-11-13 18:16:14 +)
>
> are available in the Git repository at:
>
> git://github.com/riscv/riscv-qemu.git t
Hi All,
On Thu, Oct 11, 2018 at 7:22 AM Palmer Dabbelt wrote:
> On Wed, 10 Oct 2018 11:10:07 PDT (-0700), peter.mayd...@linaro.org wrote:
> > On 10 October 2018 at 18:49, Palmer Dabbelt wrote:
> >> we should really
> >> get the ball rolling on our big patch backlog.
> >
> > Yes, please do. Soft
for you to fetch changes up to 7c28f4da20e5585dce7d575691dac5392b7c6f78:
> >>
> >>RISC-V: Don't add NULL bootargs to device-tree (2018-10-17 13:02:30
> -0700)
> >>
> >> --------
> >
On Wed, May 16, 2018 at 4:00 AM, Igor Mammedov wrote:
> cpu_init() was removed since 2.12, so drop the define that is now unused.
>
> Signed-off-by: Igor Mammedov
> Reviewed-by: Philippe Mathieu-Daudé
>
Reviewed-by: Michael Clark
---
> v2:
> * refine commi
On Tue, May 15, 2018 at 12:07 PM, Alistair Francis wrote:
> Signed-off-by: Alistair Francis
>
Reviewed-by: Michael Clark
> ---
> hw/riscv/sifive_e.c | 97 +++--
> include/hw/riscv/sifive_e.h | 16 +-
> 2 files changed, 86
On Tue, May 15, 2018 at 12:07 PM, Alistair Francis wrote:
> To allow Linux to ennumerate devices on the /soc/ node set it as a
> "simple-bus".
>
> Signed-off-by: Alistair Francis
>
Reviewed-by: Michael Clark
> ---
> hw/riscv/sifive_u.c | 2 +-
> 1 file c
On Sun, May 13, 2018 at 12:52 PM, Philippe Mathieu-Daudé
wrote:
> On 05/11/2018 12:52 AM, Richard Henderson wrote:
> > Cc: Michael Clark
> > Cc: Palmer Dabbelt
> > Cc: Sagar Karandikar
> > Cc: Bastian Koppelmann
> > Signed-off-by: Richard Henderson
>
&
On Fri, May 11, 2018 at 3:52 PM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> Cc: Michael Clark
> Cc: Palmer Dabbelt
> Cc: Sagar Karandikar
> Cc: Bastian Koppelmann
> Signed-off-by: Richard Henderson
>
I'm not against this change but it conflicts w
to maintain reconfigurable hardware support in a SiFive tree. I'll
leave the RFC proper for another email. This is just an abstract.
BTW - there are plently of others you can get to accept this patch ;-) See
the 'Cc.
Signed-off-by: Antony Pavlov
> Cc: Michael Clark
> Cc: Palmer Da
irt bbl/linux-4.16-rc2 board test: pass
* sifive_e board test (HiFive1 binaries): pass
* sifive_u board test (HiFive Unleashed): pass
* riscv-tests: pass
* checkpatch: pass
Kito Cheng (1):
RISC-V: linux-user support for RVE ABI
Michael Clark (27):
RISC-V: Update address bits to support sv39
PTE X flag and mstatus.mxr
- Use memory_region_is_ram in pte update
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Alistair Francis
---
target/riscv/cpu_bits.h | 2 --
target/riscv/helper.c | 64
This commit is intended to improve readability.
There is no change to the logic.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Alistair Francis
---
target/riscv/helper.c | 34
Francis
Signed-off-by: Michael Clark
---
target/riscv/Makefile.objs | 2 +-
target/riscv/cpu.h | 18 +-
target/riscv/cpu_helper.c | 4 +-
target/riscv/csr.c | 857 +
target/riscv/gdbstub.c | 10 +-
target/riscv/op_helper.c | 611
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 34abc383e3d4..e0608e6d5f08 100644
her paging mode and page table bit definitions.
* Move together interrupt and exception cause definitions.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Alistair Francis
---
target/riscv/cpu_bit
This adds the necessary minimum to support S-mode
virtualization for priv ISA >= v1.10
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Cc: Matthew Suozzo
Signed-off-by: Michael Clark
Co-authored-by: Matthew Suozzo
Co-authored-by: Michael Cl
r and
software interrupts by other interrupt controller models.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
hw/riscv/sifive_plic.c| 13 +
target/riscv/cpu.h| 2 ++
target/riscv/cpu_helper.c
the
count of pending interrupts is not used.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Richard Henderson
---
hw/riscv/sifive_plic.c | 49 +++---
include/hw/riscv
tatus.FS so the bug in the first
spin of this patch has been fixed in a prior commit.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Cc: Richard Henderson
Signed-off-by: Michael Clark
Reviewed-by: Michael Clark
Co-authored-by: Richard Henderson
Co-aut
riscv_set_mode to riscv_cpu_set_mode
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
linux-user/riscv/signal.c | 4 ++--
target/riscv/cpu.h| 21 ++---
target/riscv/cpu_helper.c | 10 +-
target/riscv
Francis
Signed-off-by: Michael Clark
---
hw/riscv/sifive_clint.c | 8
hw/riscv/sifive_plic.c | 4 ++--
target/riscv/cpu.h | 22 +-
target/riscv/op_helper.c | 24 +++-
4 files changed, 34 insertions(+), 24 deletions(-)
diff --git a/hw/riscv
This allows hardware and/or derived cpu instances
to override or implement new CSR operations.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/cpu.h | 18 ++
target/riscv/csr.c | 35
The mode variable only uses the lower 4-bits (M,H,S,U) so
replace the GCC specific __builtin_popcount with ctpop8.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
hw/riscv/sifive_plic.c | 4 ++--
1 file changed, 2
Add carriage return that was erroneously removed
when converting to qemu_log. Change hard coded
core number to the actual hartid.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/cpu_helper.c | 18
This patch makes op_helper.c contain only instruction
operation helpers used by translate.c and moves any
unrelated cpu helpers into cpu_helper.c. No logic is
changed by this patch.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
hw/riscv/virt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index ad03113e0f72..321fa6e8122a 100644
--- a/hw/riscv/virt.c
+++ b/hw
-off-by: Michael Clark
---
target/riscv/translate.c | 158 +++
1 file changed, 158 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index fd21b133a5a4..e488101ff56d 100644
--- a/target/riscv/translate.c
+++ b/target/riscv
Use the new CSR read/modify/write interface to implement
atomic updates to mip/sip.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/csr.c | 56 +++---
1 file
Cc: Bastian Koppelmann
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
hw/riscv/sifive_e.c | 4 ++--
hw/riscv/sifive_u.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index e4ecb7aa4bb6..159209199537 100644
--- a/hw
s are
usually written first followed by the high order
bits meaning the high order bits contained an invalid
value between the timecmp_lo and timecmp_hi update.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Co-Authored-by: Johannes Haring
Signed-off-by: Mi
s and processors that don't
implement PMP will trap on accesses to pmp* CSRs.
PMP checks are disabled in riscv_cpu_handle_mmu_fault
when the PMP CPU feature is not present.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
-
Refer to the RISC-V PSABI specification for details:
- https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
Cc: Michael Tokarev
Cc: Laurent Vivier
Cc: Richard Henderson
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
include/elf.h | 8
1 file changed, 8
Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Reported-by: Vincent Siles
Signed-off-by: Michael Clark
---
hw/riscv/sifive_plic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index 28e28d932f7c
From: Richard Henderson
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Cc: Richard Henderson
Signed-off-by: Michael Clark
Reviewed-by: Michael Clark
---
target/riscv/cpu.h | 6 +++---
target/riscv/translate.c | 10 +-
2 files changed, 8
gen methods should access state from DisasContext. Add misa
field to the DisasContext struct and remove CPURISCVState
argument from all gen methods.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Cc: Emilio G. Cota
Signed-off-by: Michael Clark
Reviewed
o consistency is
taken by flushing the translation cache on misa writes. misa_mask
is added to the CPU struct to store the original set of extensions.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/cpu.c | 2 +
Remove machine generated constraints that are not
referenced by the pseudo-instruction constraints.
Cc: Palmer Dabbelt
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
disas/riscv.c | 138
Karandikar
Cc: Bastian Koppelmann
Cc: Alistair Francis
Co-authored-by: Kito Cheng
Co-authored-by: Michael Clark
Signed-off-by: Michael Clark
---
linux-user/riscv/cpu_loop.c | 14 +-
target/riscv/cpu.h | 4
target/riscv/cpu_user.h | 3 ++-
3 files changed, 19
---
hw/riscv/sifive_u.c | 4 +++-
hw/riscv/spike.c| 6 --
hw/riscv/virt.c | 4 +++-
3 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 326b0f434cff..02721d43c474 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -
is
Signed-off-by: Michael Clark
---
hw/riscv/Makefile.objs | 1 +
hw/riscv/boot.c | 172
hw/riscv/virt.c | 67 +++
include/hw/riscv/boot.h | 30 +
4 files changed, 213 insertions(+), 57 deletions(-)
crea
to the MMU.
Michael.
On Wed, May 23, 2018 at 12:14 PM, Michael Clark wrote:
> - Inline PTE_TABLE check for better readability
> - Change access checks from ternary operator to if
> - Improve readibility of User page U mode and SUM test
> - Disallow non U mode from fetching from User p
On Fri, May 25, 2018 at 9:54 AM, Richard Henderson wrote:
> In the latest Coverity scan, it reports
>
> 405if (csrno >= CSR_MHPMCOUNTER3 && csrno <= CSR_MHPMCOUNTER31) {
> 406return 0;
> 407}
> 408#if defined(TARGET_RISCV32)
> 409if (csrno >= CSR_MHPMCOUNTER3 && csrno <= CSR_M
This patch enables mhpmcounter3h through mhpmcounter31h on RV32.
Previously the RV32 h versions (high 32-bits of 64-bit counters)
of these counters would trap with an illegal instruction instead
of returning 0 as intended.
Reported-by: Richard Henderson
Signed-off-by: Michael Clark
---
target
On Wed, May 23, 2018 at 6:44 PM, Laurent Vivier wrote:
> Le 23/05/2018 à 02:15, Michael Clark a écrit :
> > Refer to the RISC-V PSABI specification for details:
> >
> > - https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
> >
> > Cc: Michae
Refer to the RISC-V PSABI specification for details:
- https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
Cc: Michael Tokarev
Cc: Laurent Vivier
Cc: Richard Henderson
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
include/elf.h | 8
1 file changed, 8
On Fri, May 25, 2018 at 7:53 PM, Laurent Vivier wrote:
> Le 25/05/2018 à 09:22, Michael Clark a écrit :
> > Refer to the RISC-V PSABI specification for details:
> >
> > - https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
> >
> > Cc: Michae
Thanks. I was just about to log an issue in the riscv-qemu issue tracker on
GitHub.
I reproduced it on my side. The fact that it is causes QEMU user to crash
in translate.c is interesting.
I ran your program with -d in_asm and it appears to crash in thread::join
On Mon, Sep 3, 2018 at 7:58 PM, P
On Mon, Sep 3, 2018 at 8:16 PM, Pranith Kumar wrote:
> On Mon, Sep 3, 2018 at 1:07 AM Michael Clark wrote:
> >
> > Thanks. I was just about to log an issue in the riscv-qemu issue tracker
> on GitHub.
> >
> > I reproduced it on my side. The fact that it is
On Tue, Jul 10, 2018 at 9:52 AM, Alistair Francis
wrote:
> On Mon, Jul 9, 2018 at 3:00 AM, Andreas Schwab wrote:
> > What is the state of the sifive_u emulation? When I tried to boot a bbl
> > with an included kernel I get these errors:
> >
> > qemu-system-riscv64: plic: invalid register write:
On Tue, 10 Jul 2018 at 12:29 PM, Alistair Francis
wrote:
> Add build time support for the VirtIO block device. This allows us to
> attach a drive using the virtio-blk-device.
I’m not sure what has changed in master, but VirtIO block and net for both
softmmu-riscv32 and softmmu-riscv64 were prev
On Wed, Jul 18, 2018 at 8:27 AM, Alistair Francis
wrote:
> Use the new object_initialize_child() and sysbus_init_child_obj() to
> fix the issue.
>
> Signed-off-by: Alistair Francis
>
Reviewed-by: Michael Clark
> ---
> hw/riscv/sifive_e.c | 12 ++--
> 1 fi
On Wed, Jul 18, 2018 at 8:28 AM, Alistair Francis
wrote:
> Use the new object_initialize_child() and sysbus_init_child_obj() to
> fix the issue.
>
> Signed-off-by: Alistair Francis
>
Reviewed-by: Michael Clark
> ---
> hw/riscv/riscv_hart.c | 7 +++
> 1 file cha
On Wed, Jul 18, 2018 at 8:28 AM, Alistair Francis
wrote:
> Use the new object_initialize_child() and sysbus_init_child_obj() to
> fix the issue.
>
> Signed-off-by: Alistair Francis
>
Reviewed-by: Michael Clark
> ---
> hw/riscv/virt.c | 5 ++---
> 1 file cha
On Wed, Jul 18, 2018 at 8:28 AM, Alistair Francis
wrote:
> Use the new object_initialize_child() and sysbus_init_child_obj() to
> fix the issue.
>
> Signed-off-by: Alistair Francis
>
Reviewed-by: Michael Clark
> ---
> hw/riscv/spike.c | 10 --
> 1 file cha
On Wed, Jul 18, 2018 at 8:28 AM, Alistair Francis
wrote:
> Use the new object_initialize_child() and sysbus_init_child_obj() to
> fix the issue.
>
> Signed-off-by: Alistair Francis
>
Reviewed-by: Michael Clark
> ---
> hw/riscv/sifive_u.c | 15 +++
> 1 fi
ealized that riscv32 use it too so I'll correct with
> > riscv*-softmmu.
>
> Using "riscv*-softmmu":
>
Indeed.
We had this fix in our tree before one of the rebases against upstream:
https://github.com/riscv/riscv-qemu/commit/90cdfb86e81c54c1df42412b10b86fd83a6dee82
It must have somehow got dropped when we forward ported to QEMU master in
December 2017. My apologies.
Reviewed-by: Philippe Mathieu-Daudé
>
Reviewed-by: Michael Clark
>> fdt_required=yes
> >> ;;
> >> esac
> >>
> >
>
On Thu, Apr 19, 2018 at 9:28 PM, Zong Li wrote:
> 2018-04-19 12:43 GMT+08:00 Michael Clark :
> > Hi Zong,
> >
> >> On 19/04/2018, at 2:40 PM, Zong Li wrote:
> >>
> >> Hi all,
> >>
> >> For BBL part, in fp_init at machine/minit.
On Fri, Apr 20, 2018 at 12:05 PM, Michael Clark wrote:
>
>
> On Thu, Apr 19, 2018 at 9:28 PM, Zong Li wrote:
>
>> 2018-04-19 12:43 GMT+08:00 Michael Clark :
>> > Hi Zong,
>> >
>> >> On 19/04/2018, at 2:40 PM, Zong Li wrote:
>> >>
&
On Fri, Apr 20, 2018 at 12:12 PM, Andrew Waterman wrote:
>
>
> On Thu, Apr 19, 2018 at 5:11 PM, Michael Clark wrote:
>
>>
>>
>> On Fri, Apr 20, 2018 at 12:05 PM, Michael Clark wrote:
>>
>>>
>>>
>>> On Thu, Apr 19, 2018 at 9:28
- (prio 0, i/o): system
> -000f (prio 1, i/o): riscv.htif.uart
> -00011fff (prio 0, ram): riscv.spike.bootrom
> 0200-0200 (prio 0, i/o): riscv.sifive.clint
>
table walker
v1
* Initial post merge cleanup patch series
Michael Clark (33):
RISC-V: Replace hardcoded constants with enum values
RISC-V: Make virt board description match spike
RISC-V: Use ROM base address and size from memmap
RISC-V: Remove identity_translate from load_elf
RISC-V
The RISC-V device-tree code has a number of hard-coded
constants and this change moves them into header enums.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
---
hw/riscv/sifive_clint.c | 9
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
---
include/hw/riscv/virt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index
Another case of replacing hard coded constants, this time
referring to the definition in the virt machine's memmap.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
---
hw/riscv/virt.c
This makes 'qemu-system-riscv64 -machine help' output more tidy
and consistent.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
---
hw/riscv/virt.c | 2 +-
1 file changed, 1 insertion(+),
Pointless indirection. Other ports use EM_ constants directly.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
---
hw/riscv/sifive_e.c | 2 +-
hw/riscv/sifive_u.c | 2 +-
hw/riscv/spike.c| 2
PTE X flag and mstatus.mxr
- Use memory_region_is_ram in pte update
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/cpu_bits.h | 2 --
target/riscv/helper.c | 64
When load_elf is called with NULL as an argument to the
address translate callback, it does an identity translation.
This commit removes the redundant identity_translate callback.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed
This was added to help debug issues using -d in_asm. It is
useful to see the instruction bytes, as one can detect if
one is trying to execute ASCII or device-tree magic.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by
: Michael Clark
---
target/riscv/op_helper.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 828f20c..b81b9b6 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -213,17
are mutually exclusive, as the E extension
will be added to the RISC-V port in the future.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/cpu.c | 2 +-
target/riscv/cpu.h | 1 +
2 files changed, 2 insertions
plete unnecessary.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
---
hw/riscv/riscv_hart.c | 6 --
hw/riscv/sifive_e.c | 25 -
hw/riscv/sifive_u.c
more complex
trap handling code).
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/op_helper.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv
This commit is intended to improve readability.
There is no change to the logic.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/helper.c | 34 --
1 file changed, 12 insertions
ses generate
illegal instructions when the privileged ISA <= v1.9.1
- Makes mscounteren and mucounteren CSR accesses generate
illegal instructions when the privileged ISA >= v1.10
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Mich
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Signed-off-by: Michael Clark
Signed-off-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
---
include/hw/riscv/spike.h | 4 ++--
include/hw/riscv/virt.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/hw/riscv
Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/helper.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/riscv/helper.c b/target/riscv/helper.c
index 459fc97..3b57e13 100644
--- a/target/riscv/helper.c
+++ b/target/riscv/helper.c
instructions will return the instruction count.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/op_helper.c | 24
target/riscv/translate.c | 2 ++
2 files changed, 22 insertions(+), 4
From: Richard Henderson
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Cc: Richard Henderson
Signed-off-by: Michael Clark
---
target/riscv/cpu.h | 6 +++---
target/riscv/translate.c | 10 +-
2 files changed, 8 insertions(+), 8 deletions
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 808eab7..c3a029a 100644
--- a/target
her paging mode and page table bit definitions.
* Move together interrupt and exception cause definitions.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/cpu_bit
Francis
Signed-off-by: Michael Clark
---
hw/riscv/sifive_clint.c | 8
hw/riscv/sifive_plic.c | 4 ++--
target/riscv/cpu.h | 8 +++-
target/riscv/op_helper.c | 23 ++-
4 files changed, 23 insertions(+), 20 deletions(-)
diff --git a/hw/riscv/sifive_clint.c b
Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
hw/riscv/sifive_e.c | 20 +++-
hw/riscv/sifive_u.c | 46 ++-
hw/riscv/spike.c| 64
tatus.FS so the bug in the first
spin of this patch has been fixed in a prior commit.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Cc: Richard Henderson
Signed-off-by: Michael Clark
Co-authored-by: Richard Henderson
Co-authored-by: Michael Clark
---
s and processors that don't
implement PMP will trap on accesses to pmp* CSRs.
PMP checks are disabled in riscv_cpu_handle_mmu_fault
when the PMP CPU feature is not present.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
-
Add carriage return that was erroneously removed
when converting to qemu_log. Change hard coded
core number to the actual hartid.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/cpu_helper.c | 18
This allows hardware and/or derived cpu instances
to override or implement new CSR operations.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/cpu.h | 18 ++
target/riscv/csr.c | 35
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9871e6f..f3f131b 100644
--- a/targ
riscv_set_mode to riscv_cpu_set_mode
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
linux-user/signal.c | 4 ++--
target/riscv/cpu.h| 21 ++---
target/riscv/cpu_helper.c | 10 +-
target/riscv
) fields is to drop writes to unsupported bits.
Cc: Sagar Karandikar
Cc: Bastian Koppelmann
Cc: Palmer Dabbelt
Cc: Alistair Francis
Signed-off-by: Michael Clark
---
target/riscv/op_helper.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/target/riscv
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