From: Mateja Marjanovic
Add support for DSPRAM (Data Scratch Pad RAM). It still needs
some minor fixing, but the structure is right.
Signed-off-by: Mateja Marjanovic
---
default-configs/mips-softmmu-common.mak | 1 +
hw/mips/cps.c | 28 +-
hw/misc
From: Mateja Marjanovic
This patch is a merge of Yongbok Kim's DSPRAM implementation
with the upstream, with some of Philippe Mathieu-Daude's comments.
It still needs some fixing (work in progress).
Mateja Marjanovic (1):
target/mips: Add implementation of DSPRAM
default-co
On 8.6.19. 07:32, Aleksandar Markovic wrote:
On Jun 6, 2019 3:49 PM, "Mateja Marjanovic"
mailto:mateja.marjano...@rt-rk.com>> wrote:
>
> From: Mateja Marjanovic <mailto:mateja.marjano...@rt-rk.com>>
>
> Add support for DSPRAM (Data Scratch Pad RAM). It
From: Mateja Marjanovic
Wrong type of NaN was generated by maddf and msubf insturctions
when the arguments were inf, zero, nan or zero, inf, nan
respectively.
Signed-off-by: Mateja Marjanovic
---
fpu/softfloat-specialize.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
From: Mateja Marjanovic
Wrong type of NaN was generated by maddf and msubf insturctions
when the arguments were inf, zero, nan or zero, inf, nan
respectively.
Mateja Marjanovic (1):
target/mips: Fix minor bug in FPU
fpu/softfloat-specialize.h | 2 +-
1 file changed, 1 insertion(+), 1
From: Mateja Marjanovic
Optimize set of MSA instructions ILVOD, using directly
tcg registers and performing logic on them insted of
using helpers.
Performance measurement is done by executing the
instructions large number of times on a computer
with Intel Core i7-3770 CPU @ 3.40GHz×8
From: Mateja Marjanovic
Optimize set of MSA instructions ILVEV, using directly
tcg registers and performing logic on them insted of
using helpers.
Performance measurement is done by executing the
instructions large number of times on a computer
with Intel Core i7-3770 CPU @ 3.40GHz×8
From: Mateja Marjanovic
Optimize set of MSA instructions ILVEV and ILVOD,
using directly tcg registers and performing logic
on them insted of using helpers.
Mateja Marjanovic (2):
target/mips: Optimize ILVOD. MSA instructions
target/mips: Optimize ILVEV. MSA instructions
target/mips
From: Mateja Marjanovic
This series optimizes the support for certain MSA instructions.
v2:
-Fixed indentation in two places
-Fixed bugs for the cases when the destination register and
one of the source registers are the same
Mateja Marjanovic (4):
target/mips: Optimize support for MSA
From: Mateja Marjanovic
Optimize support for MSA instructions ILVL.B, ILVL.H, ILVL.W, and
ILVL.D.
Optimization is done by eliminating loops, and explicitly assigning
desired values to individual data elements. Performance measurement
is done by executing the instructions large number of times
From: Mateja Marjanovic
Optimize support for MSA instructions ILVOD.B, ILVOD.H, ILVOD.W, and
ILVOD.D.
Optimization is done by eliminating loops, and explicitly assigning
desired values to individual data elements. Performance measurement
is done by executing the instructions large number of
From: Mateja Marjanovic
Optimize support for MSA instructions ILVEV.B, ILVEV.H, ILVEV.W, and
ILVEV.D.
Optimization is done by eliminating loops, and explicitly assigning
desired values to individual data elements. Performance measurement
is done by executing the instructions large number of
From: Mateja Marjanovic
Optimize support for MSA instructions ILVR.B, ILVR.H, ILVR.W, and
ILVR.D.
Optimization is done by eliminating loops, and explicitly assigning
desired values to individual data elements. Performance measurement
is done by executing the instructions large number of times
From: Mateja Marjanovic
Add emulation of MMI instruction PCPYUD. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic
Reviewed-by: Aleksandar Rikalo
---
target/mips/translate.c | 43
From: Mateja Marjanovic
This series adds emulation of PCPYH, PCPYLD, and PCPYUD MMI
instructions.
v3:
- Added MMI instructions PEXEH, PEXEW, PEXTLB, PEXTLH, PEXTLW,
PEXTUB, PEXTUH, and PEXTUW
- Minor bugs fixed from previous patches
v2:
- The patch for PCPYH is split into two patches
From: Mateja Marjanovic
Add emulation of MMI instruction PEXTUH. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic
---
target/mips/translate.c | 70 -
1 file
Add emulation of MMI instruction PCPYLD. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic
Reviewed-by: Aleksandar Rikalo
---
target/mips/translate.c | 43 ++-
1 file
From: Mateja Marjanovic
Add emulation of MMI instruction PEXTLH. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic
---
target/mips/translate.c | 70 -
1 file
From: Mateja Marjanovic
Add emulation of MMI instruction PEXTLB. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic
---
target/mips/translate.c | 96 -
1 file
From: Mateja Marjanovic
Add emulation of MMI instruction PEXCW. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic
---
target/mips/translate.c | 73 -
1 file
From: Mateja Marjanovic
Add emulation of MMI instruction PEXTUW. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic
---
target/mips/translate.c | 58 -
1 file
From: Mateja Marjanovic
Add emulation of MMI instruction PCPYH. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic
Reviewed-by: Aleksandar Rikalo
---
target/mips/translate.c | 66
From: Mateja Marjanovic
Add emulation of MMI instruction PEXEH. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic
---
target/mips/translate.c | 75 -
1 file
From: Mateja Marjanovic
Add emulation of MMI instruction PEXTLW. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic
---
target/mips/translate.c | 57 -
1 file
From: Mateja Marjanovic
Add emulation of MMI instruction PEXTUB. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic
---
target/mips/translate.c | 96 -
1 file
From: Mateja Marjanovic
Add emulation of MMI instruction PEXCH. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic
---
target/mips/translate.c | 97 -
1 file
From: Mateja Marjanovic
Add emulation of MMI instruction PEXEW. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic
---
target/mips/translate.c | 65 -
1 file
From: Mateja Marjanovic
Eliminate loops for better performance.
Signed-off-by: Mateja Marjanovic
---
target/mips/msa_helper.c | 43 ++-
1 file changed, 30 insertions(+), 13 deletions(-)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
From: Mateja Marjanovic
Eliminate loops for better performance.
Regression tests are also included.
Mateja Marjanovic (2):
target/mips: Improve performance for MSA binary operations
target/mips: Tests for binary integer MSA instruction (add, adds,
hadd...)
target/mips/msa_helper.c
From: Mateja Marjanovic
These are regression tests for MSA integer binary operations.
Mateja Marjanovic (5):
target/mips: Add tests for a variety of MSA integer average
instructions
target/mips: Add tests for a variety of MSA integer divide
instructions
target/mips: Add tests for
From: Mateja Marjanovic
Add tests for a variety of MSA integer dot product instructions.
Signed-off-by: Mateja Marjanovic
---
.../ase/msa/int-dot-product/test_msa_dotp_s_d.c| 151 +
.../ase/msa/int-dot-product/test_msa_dotp_s_h.c| 151 +
.../ase
From: Mateja Marjanovic
Add tests for a variety of MSA integer multiply instructions.
Signed-off-by: Mateja Marjanovic
---
.../user/ase/msa/int-multiply/test_msa_mul_q_h.c | 151 +
.../user/ase/msa/int-multiply/test_msa_mul_q_w.c | 151 +
.../user
From: Mateja Marjanovic
Add tests for a variety of MSA integer divide instructions.
Signed-off-by: Mateja Marjanovic
---
.../user/ase/msa/int-divide/test_msa_div_s_b.c | 151 +
.../user/ase/msa/int-divide/test_msa_div_s_d.c | 151 +
.../user/ase
From: Mateja Marjanovic
Add tests for a variety of MSA integer average instructions.
Signed-off-by: Mateja Marjanovic
---
.../user/ase/msa/int-average/test_msa_ave_s_b.c| 151 +
.../user/ase/msa/int-average/test_msa_ave_s_d.c| 151 +
.../user
From: Mateja Marjanovic
In case of dividing integers by zero, the result is unpredictable [1],
but according to the hardware, the result is not zero, but the dividend.
[1] MIPS® Architecture for Programmers
Volume IV-j: The MIPS64® SIMD
Architecture Module, Revision 1.12
Signed-off-by
From: Mateja Marjanovic
In case of dividing integers by zero, the result is unpredictable [1],
but according to the hardware, the result is 1 or -1, depending on
the sign of the dividend.
[1] MIPS® Architecture for Programmers
Volume IV-j: The MIPS64® SIMD
Architecture Module, Revision
From: Mateja Marjanovic
Integer division by zero in MSA insturctions results in unpredictable
behaviour, but according to the hardware, it depends on the sign of
the dividend, or always returns the same value.
Mateja Marjanovic (2):
target/mips: DIV_. MSA insturctions fixed
target/mips
On 1.4.19. 19:53, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH v3 0/5] Add support for MSA instructions on a big endian host
"Add" -> "Fix"
Big endian host support should have worked from the moment MSA
support is added to QEMU.
I will change it
On 1.4.19. 19:30, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH 2/2] target/mips: MOD_. MSA insturctions fixed
From: Mateja Marjanovic
In case of dividing integers by zero, the result is unpredictable [1],
but according to the hardware, the result is not zero, but the
On 1.4.19. 19:43, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH 0/2] target/mips: Integer division by zero in MSA insturctions
The title look incomplete and uninformative: it mentions "the division by zero"
- but what is done in this case? Is this an impleme
On 1.4.19. 19:28, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH 1/2] target/mips: DIV_. MSA insturctions fixed
"insturctions" -> "instructions". Try to find a spell checking tool that will
help
you avoid such cases in the future, especially sin
On 1.4.19. 19:56, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH v3 1/5] target/mips: MSA instructions ld, big endian host fix
Start the title with the imperative, such as "target/mips: Fix..."
Use full instruction names, as explained in previous reviews.
On 1.4.19. 20:03, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH v3 5/5] target/mips: Different approach toward INSERT MSA
instr. and big endian fix
"Different approach toward..." -> "Refactor and fix INSERT.
instructions"
Same goes for this
On 1.4.19. 20:01, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH v3 3/5] target/mips: Different approach toward COPY_S MSA
instr. and big endian fix
"Different approach toward..." -> "Refactor and fix COPY_S.
instructions"
I will change that
On 1.4.19. 19:58, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH v3 2/5] target/mips: MSA instructions st, big endian host fix
From: Mateja Marjanovic
Fix the case when the host is running on a big endian machine,
and change the approach toward st instruction helpers
On 1.4.19. 20:02, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH v3 4/5] target/mips: Different approach toward COPY_U MSA
instr. and big endian fix
From: Mateja Marjanovic
"Different approach toward..." -> "Refactor and fix COPY_U. instructions&quo
From: Mateja Marjanovic
The behaviour when executing DIV_. and MOD_.
differs on a referent hardware (FPGA MIPS 64 r6, little endian) and on
QEMU, when the divisor is equal to zero. That is not a real bug, because
the behaviour in that case is unpredictable (references in commit
messages).
v2
From: Mateja Marjanovic
MSA instructions DIV_. when dividing by zero,
didn't return the same value when executed on a referent hardware
(FPGA MIPS 64 r6, little endian) and when executed on QEMU, which
is not a real bug, because the result when dividing by zero is
UNPREDICTABLE [1] (pag
From: Mateja Marjanovic
MSA instructions MOD_. when dividing by zero,
didn't return the same value when executed on a referent hardware
(FPGA MIPS 64 r6, little endian) and when executed on QEMU, which
is not a real bug, because the result when dividing by zero is
UNPREDICTABLE [1] (pag
From: Mateja Marjanovic
The old version of the helper for the COPY_U. MSA instructions
has been replaced with four helpers that don't use switch, and change
the endianness of the given index, when executed on a big endian host.
Signed-off-by: Mateja Marjanovic
---
target/mips/hel
From: Mateja Marjanovic
Fix the case when the host is a big endian machine, and change
the approach toward LD. instruction helpers.
Signed-off-by: Mateja Marjanovic
---
target/mips/op_helper.c | 188 ++--
1 file changed, 168 insertions(+), 20
From: Mateja Marjanovic
The old version of the helper for the COPY_S. MSA instructions
has been replaced with four helpers that don't use switch, and change
the endianness of the given index, when executed on a big endian host.
Signed-off-by: Mateja Marjanovic
---
target/mips/hel
From: Mateja Marjanovic
Fix support for MSA instructions while executing QEMU on a
machine that uses big endian MIPS CPU. This is achieved by
changing the implementation of helpers for MSA instructions
ST., LD., INSERT. (and D on MIPS64),
COPY_S. (and D on MIPS64) and COPY_U. (and W
on MIPS64
From: Mateja Marjanovic
Fix the case when the host is a big endian machine, and change
the approach toward ST. instruction helpers.
Signed-off-by: Mateja Marjanovic
---
target/mips/op_helper.c | 188 ++--
1 file changed, 168 insertions(+), 20
From: Mateja Marjanovic
The old version of the helper for the INSERT. MSA instructions
has been replaced with four helpers that don't use switch, and change
the endianness of the given index, when executed on a big endian host.
Signed-off-by: Mateja Marjanovic
---
target/mips/hel
From: Mateja Marjanovic
Optimize set of MSA instructions ILVOD, using directly
tcg registers and performing logic on them instead of
using helpers.
instr|| before|| after
==
ilvod.b || 117.50 ms || 24.99 ms
ilvod.h || 93.16 ms || 24.27
From: Mateja Marjanovic
Optimize MSA instructions ILVEV. and ILVOD.,
using directly tcg registers and performing logic on
them insted of using helpers.
v5:
- Use tcg_gen_deposit function.
- Added performance number for no-deposit and
with-deposit cases of ILVEV.W.
- Minor changes in
From: Mateja Marjanovic
Optimize set of MSA instructions ILVEV, using directly
tcg registers and performing logic on them instead of
using helpers.
In the following table, the first column is the performance
before this patch. The second represents the performance,
after converting from helpers
On 2.4.19. 17:08, Philippe Mathieu-Daudé wrote:
Hi Mateja,
On 4/2/19 2:11 PM, Mateja Marjanovic wrote:
From: Mateja Marjanovic
MSA instructions DIV_. when dividing by zero,
didn't return the same value when executed on a referent hardware
(FPGA MIPS 64 r6, little endian) and when exe
On 2.4.19. 20:37, Philippe Mathieu-Daudé wrote:
On 4/2/19 7:07 PM, Aleksandar Markovic wrote:
From: Philippe Mathieu-Daudé
Subject: Re: [Qemu-devel] [PATCH v5 2/2] target/mips: Optimize ILVEV.
MSA instructions
Hi Mateja,
On 4/2/19 5:15 PM, Mateja Marjanovic wrote:
From: Mateja Marjanovic
On 2.4.19. 20:51, Aleksandar Markovic wrote:
+/*
+ * [MSA] ILVEV.D wd, ws, wt
+ *
+ * Vector Interleave Even (Double data elements)
+ *
+ */
Double -> Doubleword
I will change it in v6.
On 2.4.19. 22:50, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH v4 5/5] target/mips: Refactor and fix INSERT.
instructions
From: Mateja Marjanovic
The old version of the helper for the INSERT. MSA instructions
has been replaced with four helpers that don't use s
On 3.4.19. 01:25, Aleksandar Markovic wrote:
On Apr 2, 2019 5:20 PM, "Mateja Marjanovic"
mailto:mateja.marjano...@rt-rk.com>> wrote:
>
> From: Mateja Marjanovic <mailto:mateja.marjano...@rt-rk.com>>
>
> Optimize set of MSA instructions ILVEV, using
From: Mateja Marjanovic
Optimized ILVR. instructions, using a hybrid
approach. For byte data elements, use a helper with an
unrolled loop (much better performance), for halfword,
word and doubleword data elements use directly tcg
registers and logic performed on them.
Performance measurement is
From: Mateja Marjanovic
Optimized ILVL. instructions, using a hybrid
approach. For byte data elements, use a helper with an
unrolled loop (much better performance), for halfword,
word and doubleword data elements use directly tcg
registers and logic performed on them.
Performance measurement is
From: Mateja Marjanovic
Optimize set of MSA instructions ILVOD., using
directly tcg registers and performing logic on them instead
of using helpers.
In the following table, the first column is the performance
before this patch. The second represents the performance,
after converting from
From: Mateja Marjanovic
Optimize set of MSA instructions ILVEV., using
directly tcg registers and performing logic on them
instead of using helpers.
In the following table, the first column is the performance
before this patch. The second represents the performance,
after converting from
From: Mateja Marjanovic
Optimize MSA instructions ILVEV., ILVOD.,
ILVL. and ILVR. using the hybrid approach,
MSA helpers in some cases and directly tcg registers in other
cases, so the performance would be better.
v6:
- Add ILVL. and ILVR. MSA instructions
with mixed approaches (with
On 13.4.19. 18:05, Aleksandar Markovic wrote:
On Thu, Apr 4, 2019 at 3:16 PM Mateja Marjanovic
wrote:
From: Mateja Marjanovic
Optimized ILVR. instructions, using a hybrid
Optimized -> Optimize
approach. For byte data elements, use a helper with an
unrolled loop (much better performa
On 13.4.19. 18:05, Aleksandar Markovic wrote:
On Thu, Apr 4, 2019 at 3:18 PM Mateja Marjanovic
wrote:
From: Mateja Marjanovic
Optimize set of MSA instructions ILVEV., using
directly tcg registers and performing logic on them
instead of using helpers.
In the following table, the first
On 2.6.19. 09:06, Aleksandar Markovic wrote:
On Jun 1, 2019 4:16 PM, "Aleksandar Markovic" <mailto:amarko...@wavecomp.com>> wrote:
>
> > From: Mateja Marjanovic <mailto:mateja.marjano...@rt-rk.com>>
> > Sent: Monday, March 4, 2019 5:51 PM
>
Mateja Marjanovic writes:
From: Mateja Marjanovic
Eliminate loops for better performance.
Have you done any measurements of the bellow loop unrolling? Because
this is something that maybe we can achieve and let the compiler make
the choice.
I know that Mateja did extensive performance
Add emulation of MMI instruction PCPYLD. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic
---
target/mips/translate.c | 42 +-
1 file changed, 41 insertions(+), 1 deletion
From: Mateja Marjanovic
This series adds emulation of PCPYH, PCPYLD, and PCPYUD MMI
instructions.
Mateja Marjanovic (3):
target/mips: Add emulation of MMI instruction PCPYH
target/mips: Add emulation of MMI instruction PCPYLD
target/mips: Add emulation of MMI instruction PCPYUD
target
Add emulation of MMI instruction PCPYH. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic
---
target/mips/translate.c | 115 ++--
1 file changed, 112 insertions(+), 3
From: Mateja Marjanovic
Add emulation of MMI instruction PCPYUD. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic
---
target/mips/translate.c | 42 +-
1 file changed, 41
Add emulation of MMI instruction PCPYLD. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic
Reviewed-by: Aleksandar Rikalo
---
target/mips/translate.c | 43 ++-
1 file
From: Mateja Marjanovic
This series adds emulation of PCPYH, PCPYLD, and PCPYUD MMI
instructions.
v2:
- The patch for PCPYH is split into two patches
- Cleaned up handler for PCPYH
- Fixed bugs and cleaned up in handler for PCPYLD
- Fixed bugs and cleaned up in handler for PCPYUD
From: Mateja Marjanovic
Set up MMI code to be compiled only for TARGET_MIPS64. This is
needed so that GPRs are 64 bit, and combined with MMI registers,
they will form full 128 bit registers.
Signed-off-by: Mateja Marjanovic
Reviewed-by: Aleksandar Rikalo
---
target/mips/translate.c | 43
From: Mateja Marjanovic
Add emulation of MMI instruction PCPYH. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic
Reviewed-by: Aleksandar Rikalo
---
target/mips/translate.c | 66
From: Mateja Marjanovic
Add emulation of MMI instruction PCPYUD. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic
Reviewed-by: Aleksandar Rikalo
---
target/mips/translate.c | 43
From: Mateja Marjanovic
Add emulation of MMI instruction PEXCH. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic
---
target/mips/translate.c | 97 -
1 file
From: Mateja Marjanovic
Add emulation of MMI instruction PEXCW. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic
---
target/mips/translate.c | 73 -
1 file
From: Mateja Marjanovic
Optimize support for MSA instructions ILVL.B, ILVL.H, ILVL.W, and
ILVL.D.
Optimization is done by eliminating loops, and explicitly assigning
desired values to individual data elements. Performance measurement
is done by executing the instructions large number of times
From: Mateja Marjanovic
Optimize support for MSA instructions ILVEV.B, ILVEV.H, ILVEV.W, and
ILVEV.D.
Optimization is done by eliminating loops, and explicitly assigning
desired values to individual data elements. Performance measurement
is done by executing the instructions large number of
From: Mateja Marjanovic
This series optimizes the support for certain MSA instructions.
Mateja Marjanovic (4):
target/mips: Optimize support for MSA instructions ILVEV.
target/mips: Optimize support for MSA instructions ILVOD.
target/mips: Optimize support for MSA instructions ILVL
From: Mateja Marjanovic
Optimize support for MSA instructions ILVR.B, ILVR.H, ILVR.W, and
ILVR.D.
Optimization is done by eliminating loops, and explicitly assigning
desired values to individual data elements. Performance measurement
is done by executing the instructions large number of times
From: Mateja Marjanovic
Optimize support for MSA instructions ILVOD.B, ILVOD.H, ILVOD.W, and
ILVOD.D.
Optimization is done by eliminating loops, and explicitly assigning
desired values to individual data elements. Performance measurement
is done by executing the instructions large number of
On 16.4.19. 23:20, Aleksandar Markovic wrote:
From: Mateja Marjanovic
+void helper_msa_ilvr_b(CPUMIPSState *env, uint32_t wd,
+ uint32_t ws, uint32_t wt)
+{
+wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+wr_t *pws = &(env->active_fpu.fpr[ws].wr);
Hello Philippe,
Sorry for replying you so late.
On 4.4.19. 15:42, Philippe Mathieu-Daudé wrote:
Hi Mateja,
On 4/4/19 3:14 PM, Mateja Marjanovic wrote:
From: Mateja Marjanovic
Optimize set of MSA instructions ILVEV., using
directly tcg registers and performing logic on them
instead of using
From: Mateja Marjanovic
Optimize set of MSA instructions ILVOD., using
directly tcg registers and performing logic on them instead
of using helpers.
In the following table, the first column is the performance
before this patch. The second represents the performance
after converting from helpers
From: Mateja Marjanovic
Optimize ILVL. instructions, using a hybrid
approach. For byte data elements, use a helper with an
unrolled loop (having much better performance than
direct tcg translation), for halfword, word and
doubleword data elements use directly tcg registers
and logic performed on
From: Mateja Marjanovic
Optimize and refactor MSA instructions ILVEV.,
ILVOD., ILVL. and ILVR..
v7:
- Use tcg constants, instead of uint64_t constants in
ILVEV. and ILVOD. instructions.
- Refactor gen_ilvod_b and gen_ilvod_h functions. Use
the shared function gen_ilvod_bh, which has two
From: Mateja Marjanovic
Optimize ILVR. instructions, using a hybrid
approach. For byte data elements, use a helper with an
unrolled loop (having much better performance than
direct tcg translation), for halfword, word and
doubleword data elements use directly tcg registers
and logic performed on
From: Mateja Marjanovic
The implementation for ILVOD.D and ILVL.D instructions
is equivalent, so use a single handler for both of them.
Suggested-by: Aleksandar Markovic
Signed-off-by: Mateja Marjanovic
---
target/mips/translate.c | 27 ++-
1 file changed, 10
From: Mateja Marjanovic
Optimize set of MSA instructions ILVEV., using
directly tcg registers and performing logic on them
instead of using helpers.
In the following table, the first column is the performance
before this patch. The second represents the performance
after converting from helpers
>From 55e222d8139e3dd034069fb512b83fd2541ec067 Mon Sep 17 00:00:00 2001
From: Mateja Marjanovic
Date: Wed, 17 Apr 2019 14:50:55 +0200
Subject: [PATCH v7 5/6] target/mips: Merge implementation of ILVEV.D and ILVR.D
The implementation for ILVEV.D and ILVR.D instructions
is equivalent, so us
On 17.4.19. 18:41, Aleksandar Markovic wrote:
From: Mateja Marjanovic
Subject: [PATCH] target/mips: Amend tests for MSA binary integer operations
Amend tests for certain MSA binary integer instructions
(for example DIV_S.B) by appending two missing test cases
to complete standard battery of
On 17.4.19. 22:22, Aleksandar Markovic wrote:
From: Aleksandar Markovic
Subject: Re: [PATCH] target/mips: Amend tests for MSA binary integer operations
From: Mateja Marjanovic
Subject: [PATCH] target/mips: Amend tests for MSA binary integer operations
Amend tests for certain MSA binary
From: Mateja Marjanovic
Optimize set of MSA instructions ILVEV., using
directly tcg registers and performing logic on them
instead of using helpers.
In the following table, the first column is the performance
before this patch. The second represents the performance
after converting from helpers
1 - 100 of 155 matches
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