From: Rob Herring
Add support for ahci on sysbus.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Reviewed-by: Andreas Färber
---
Changes from v10-v13
None
Changes from v9
Changed typedef struct names to CamelCase
Changes from v7, v8
None
Changes from v5, v6
From: Rob Herring
This adds very basic support for the xgmac ethernet core. Missing things
include:
- statistics counters
- WoL support
- rx checksum offload
- chained descriptors (only linear descriptor ring)
- broadcast and multicast handling
Signed-off-by: Rob Herring
Signed-off-by: Mark
From: Peter Maydell
Support passing a board ID value to the kernel in r1
that is more than 16 bits wide. This is needed to pass
the '-1 == invalid' value for boards which only support
device tree booting.
Signed-off-by: Peter Maydell
Tested-by: Mark Langsdorf
---
Changes from v13
From: Rob Herring
Adds support for Calxeda's Highbank SoC.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v13
Removed no_vga parameter
Really reverted board_id to -1
Changes from v12
Reverted board_id to -1. Added comments clarifying why
Long term, the config_base_register will be a QDM parameter. In the
meantime, models that use it need to be able to preserve it across
cpu_reset() calls.
Signed-off-by: Mark Langsdorf
---
Changes from v13
Make save/restore unconditional
Changes from v1-v12
Skipped
target-arm
Create two functions, write_secondary_boot() and secondary_cpu_reset_hook(),
to allow platforms more control of how secondary CPUs are brought up. The
new functions default to NULL and aren't called unless they are populated
so there are no changes to existing platform models.
Signed-off-by:
This patch series adds support for the Calxeda Highbank SoC.
Makefile.target |2 +
hw/arm-misc.h | 17 ++
hw/arm_boot.c | 65 ++--
hw/highbank.c | 330
hw/ide/ahci.c | 44 ++
hw/xgmac.c | 421 +++
Signed-off-by: Mark Langsdorf
---
MAINTAINERS |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 173e893..bdc254f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -237,6 +237,11 @@ M: Peter Maydell
S: Maintained
F: hw/versatilepb.c
Signed-off-by: Mark Langsdorf
---
Changes from v1
Put entry in alphabetical order
Added maintainership of hw/xgmac
MAINTAINERS |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 173e893..74ee059 100644
--- a/MAINTAINERS
This is a collection of patches that make minor fixes to
the models for various ARM devices.
--Mark Langsdorf
Calxeda, Inc.
From: juha.riihim...@nokia.com
Conflicts:
target-arm/cpu.h
target-arm/helper.c
Signed-off-by: Mark Langsdorf
---
target-arm/cpu.h |4 +
target-arm/helper.c | 556
+-
target-arm/machine.c |6 +
3 files changed
From: Rob Herring
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
hw/arm_gic.c | 10 --
1 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index 9b52119..5974c2f 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -274,7 +274,7
From: Rob Herring
Use AHCIState instead of AHCIPCIState so the function can be used for
non-PCI based AHCI controllers.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
hw/ide/ahci.c | 14 +++---
hw/ide/ich.c |4 ++--
2 files changed, 9 insertions(+), 9 deletions
From: Rob Herring
Add support for ahci on sysbus.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
hw/ide/ahci.c | 35 +++
1 files changed, 35 insertions(+), 0 deletions(-)
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 135d0ee..8b56509
From: Rob Herring
This is just a dummy device for ARM L2 cache controllers.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Makefile.target |2 +-
hw/arm_l2x0.c | 109
+++
2 files changed, 110 insertions(+), 1
This adds very basic support for xgmac block. Missing things include:
- statistics counters
- WoL support
- rx checksum offload
- chained descriptors (only linear descriptor ring)
- broadcast and multicast handling
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Makefile.target
Use qdev properties to allow board modelers to set the frequencies
for the sp804 timer. Each of the sp804's timers can have an
individual frequency or they share the frequency by default.
The timers default to 1MHz.
Signed-off-by: Mark Langsdorf
---
hw/arm_timer.c |
From: Rob Herring
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Conflicts:
target-arm/cpu.h
target-arm/helper.c
---
target-arm/cpu.h|1 +
target-arm/helper.c |7 +++
2 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/target-arm/cpu.h b
From: Rob Herring
Add power control and non-secure access ctrl registers
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
hw/a9mpcore.c | 26 --
1 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/hw/a9mpcore.c b/hw/a9mpcore.c
index cd2985f
On 12/20/2011 01:58 PM, Peter Maydell wrote:
> On 20 December 2011 19:11, Mark Langsdorf wrote:
>> From: Rob Herring
>>
>> Signed-off-by: Rob Herring
>> Signed-off-by: Mark Langsdorf
>> ---
>> hw/arm_gic.c | 10 --
>> 1 files changed, 8 i
On 12/20/2011 01:48 PM, Peter Maydell wrote:
> On 20 December 2011 19:10, Mark Langsdorf wrote:
>> diff --git a/target-arm/helper.c b/target-arm/helper.c
>> index 816c4c4..37110bc 100644
>> --- a/target-arm/helper.c
>> +++ b/target-arm/helper.c
>> @@ -2197,6 +21
On 12/20/2011 02:24 PM, Peter Maydell wrote:
> On 20 December 2011 19:15, Mark Langsdorf wrote:
>> This adds very basic support for xgmac block. Missing things include:
>>
>> - statistics counters
>> - WoL support
>> - rx checksum offload
>> - chained d
From: Rob Herring
Implement handling for the RAZ/WI gic security registers.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v1
Moved handling back inside the 0-0x100 block
Added more clarifying comments
hw/arm_gic.c |6 ++
1 files changed, 6
Use qdev properties to allow board modelers to set the frequencies
for the sp804 timer. Each of the sp804's timers can have an
individual frequency. The timers default to 1MHz.
Signed-off-by: Mark Langsdorf
---
Changes from v1
Simplified multiple timer frequency handling
Re
This is a collection of fixes and additions to the models for various ARM
devices. These changes are needed to support the forthcoming Calxeda
Highbank SoC model.
Makefile.target |2 +
hw/a9mpcore.c | 36 -
hw/arm_gic.c|6 +
hw/arm_l2x0.c | 173 +++
From: Rob Herring
Add support for ahci on sysbus.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
hw/ide/ahci.c | 35 +++
1 files changed, 35 insertions(+), 0 deletions(-)
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 135d0ee..8b56509 100644
This adds very basic support for XG-mac ethernet core from Synopsis and
others. Missing things include:
- statistics counters
- WoL support
- rx checksum offload
- chained descriptors (only linear descriptor ring)
- broadcast and multicast handling
Signed-off-by: Rob Herring
Signed-off-by: Mark
From: Rob Herring
Add power control and non-secure access ctrl registers
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v1:
Added VMState support
Checked alignment of writes to the power control register
hw/a9mpcore.c | 34
From: Rob Herring
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
hw/a9mpcore.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/hw/a9mpcore.c b/hw/a9mpcore.c
index 875ae98..93b0498 100644
--- a/hw/a9mpcore.c
+++ b/hw/a9mpcore.c
@@ -13,7 +13,7
Add a cp15 config_base_register that currently defaults to 0.
After the QOM CPU support is added, the value will be properly
set to the periphal base value.
Signed-off-by: Mark Langsdorf
---
Changes from v1
renamed the register
added comments about how it will change when QOM
From: Rob Herring
Use AHCIState instead of AHCIPCIState so the function can be used for
non-PCI based AHCI controllers.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
hw/ide/ahci.c | 14 +++---
hw/ide/ich.c |4 ++--
2 files changed, 9 insertions(+), 9 deletions
From: Rob Herring
This is just a dummy device for ARM L2 cache controllers, based on the
pl310. The cache type parameter can be defined by a property value
and has a meaningful default.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v1
Corrected formatting
This is a collection of fixes and additions to the models for various ARM
devices. These changes are needed to support the forthcoming Calxeda
Highbank SoC model.
Makefile.target |2 +
hw/a9mpcore.c | 45 +-
hw/arm11mpcore.c|2 +-
hw/arm_gic.c| 46 ---
hw
Add a cp15 config_base_register that currently defaults to 0.
After the QOM CPU support is added, the value will be properly
set to the periphal base value.
Signed-off-by: Mark Langsdorf
---
Changes from v2
Added test against op2
hanges from v1
renamed the register
added
From: Rob Herring
Add support for ahci on sysbus.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v1, v2
Corrected indentation of PlatAHCIState members
Made plat_ahci_info into a single structure, not a list
hw/ide/ahci.c | 31
From: Rob Herring
Implement handling for the RAZ/WI gic security registers.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Reviewed-by: Peter Maydell
---
Changes from v2
None
Changes from v1
Moved handling back inside the 0-0x100 block
Added more clarifying
Increase the maximum number of GIC interrupts for a9mp to 192, and
create a configurable property defaulting to 96 so that device
modelers can set the value appropriately for their SoC.
Signed-off-by: Mark Langsdorf
---
Changes from v2
Skipped
Changes from v1
Increase the number
From: Rob Herring
This is just a dummy device for ARM L2 cache controllers, based on the
pl310. The cache type parameter can be defined by a property value
and has a meaningful default.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v2
Reformatted a couple
From: Rob Herring
Add power control register to a9mpcore
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v2:
Better handling of byte and halfword writes to the power register
Correct handling of VMState versions
Improved commit message
Changes
Use qdev properties to allow board modelers to set the frequencies
for the sp804 timer. Each of the sp804's timers can have an
individual frequency. The timers default to 1MHz.
Signed-off-by: Mark Langsdorf
---
Changes from v2
Comment correctly describes behavior of prope
From: Rob Herring
Use AHCIState instead of AHCIPCIState so the function can be used for
non-PCI based AHCI controllers.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v1, v2
None
hw/ide/ahci.c | 14 +++---
hw/ide/ich.c |4 ++--
2 files
This adds very basic support for XG-mac ethernet core from Synopsis and
others. Missing things include:
- statistics counters
- WoL support
- rx checksum offload
- chained descriptors (only linear descriptor ring)
- broadcast and multicast handling
Signed-off-by: Rob Herring
Signed-off-by: Mark
On 12/27/2011 03:59 PM, Peter Maydell wrote:
> On 27 December 2011 20:13, Mark Langsdorf wrote:
>> Increase the maximum number of GIC interrupts for a9mp to 192, and
>> create a configurable property defaulting to 96 so that device
>> modelers can set the value approp
On 12/27/2011 04:54 PM, Peter Maydell wrote:
> On 27 December 2011 20:13, Mark Langsdorf wrote:
>> From: Rob Herring
>>
>> Use AHCIState instead of AHCIPCIState so the function can be used for
>> non-PCI based AHCI controllers.
>>
>> Signed-off-by: Rob He
This is a collection of fixes and additions to the models for various
ARM devices. These changes are needed to support the forthcoming
Calxeda Highbank SoC model.
Makefile.target |2 +
hw/a9mpcore.c | 43 +-
hw/arm11mpcore.c| 14 +-
hw/arm_gic.c| 63 +---
From: Rob Herring
Add power control register to a9mpcore
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Reviewed-by: Peter Maydell
---
Changes from v3
None
Changes from v2:
Better handling of byte and halfword writes to the power register
Correct handling of
appropriately.
Set the maximum theoretically number of GIC interrupts to 1020 and
update the save/restore code to only use the appropriate number for
each SoC.
Signed-off-by: Mark Langsdorf
---
Changes from v3
Increase maximum number of GIC interrupts to 1020
Remove SoC/implementation
From: Rob Herring
Implement handling for the RAZ/WI gic security registers.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Reviewed-by: Peter Maydell
---
Changes from v2, v3
None
Changes from v1
Moved handling back inside the 0-0x100 block
Added more
Use qdev properties to allow board modelers to set the frequencies
for the sp804 timer. Each of the sp804's timers can have an
individual frequency. The timers default to 1MHz.
Signed-off-by: Mark Langsdorf
Reviewed-by: Peter Maydell
---
Changes from v3
None
Changes fr
This adds very basic support for XG-mac ethernet core from Synopsis and
others. Missing things include:
- statistics counters
- WoL support
- rx checksum offload
- chained descriptors (only linear descriptor ring)
- broadcast and multicast handling
Signed-off-by: Rob Herring
Signed-off-by: Mark
From: Rob Herring
This is just a dummy device for ARM L2 cache controllers, based on the
pl310. The cache type parameter can be defined by a property value
and has a meaningful default.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v3
Changed default value
Add a cp15 config_base_register that currently defaults to 0.
After the QOM CPU support is added, the value will be properly
set to the periphal base value.
Signed-off-by: Mark Langsdorf
Reviewed-by: Peter Maydell
---
Changes from v3
None
Changes from v2
Added test against op2
Use qdev properties to allow board modelers to set the frequencies
for the sp804 timer. Each of the sp804's timers can have an
individual frequency. The timers default to 1MHz.
Signed-off-by: Mark Langsdorf
Reviewed-by: Peter Maydell
Reviewed-by: Andreas Färber
---
Changes from v
appropriately.
Set the maximum theoretically number of GIC interrupts to 1020 and
update the save/restore code to only use the appropriate number for
each SoC.
Signed-off-by: Mark Langsdorf
---
Changes from v4
None
Changes from v3
Increase maximum number of GIC interrupts to 1020
From: Rob Herring
Implement handling for the RAZ/WI gic security registers.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Reviewed-by: Peter Maydell
---
Changes from v2, v3, v4
None
Changes from v1
Moved handling back inside the 0-0x100 block
Added more
This adds very basic support for XG-mac ethernet core from Synopsis and
others. Missing things include:
- statistics counters
- WoL support
- rx checksum offload
- chained descriptors (only linear descriptor ring)
- broadcast and multicast handling
Signed-off-by: Rob Herring
Signed-off-by: Mark
From: Rob Herring
Add power control register to a9mpcore
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Reviewed-by: Peter Maydell
---
Changes from v3, v4
None
Changes from v2:
Better handling of byte and halfword writes to the power register
Correct
This is a collection of fixes and additions to the models for various
ARM devices. These changes are needed to support the forthcoming
Calxeda Highbank SoC model.
Makefile.target |2 +
hw/a9mpcore.c | 43 +-
hw/arm11mpcore.c| 14 +-
hw/arm_gic.c| 63 +---
Add a cp15 config_base_register that currently defaults to 0.
After the QOM CPU support is added, the value will be properly
set to the periphal base value.
Signed-off-by: Mark Langsdorf
Reviewed-by: Peter Maydell
---
Changes from v3, v4
None
Changes from v2
Added test against
From: Rob Herring
This is just a dummy device for ARM L2 cache controllers, based on the
pl310. The cache type parameter can be defined by a property value
and has a meaningful default.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v4
Handling cache_type
On 01/04/2012 08:32 AM, Peter Maydell wrote:
> On 29 December 2011 16:19, Mark Langsdorf wrote:
>> Add a cp15 config_base_register that currently defaults to 0.
>> After the QOM CPU support is added, the value will be properly
>> set to the periphal base value.
>>
>&
Add dummy register support for the cp15, CRn=c15 registers.
config_base_register and power_control_register currently
default to 0, but may have improved support after the QOM
CPU patches are finished.
Signed-off-by: Mark Langsdorf
---
Changes from v5
Added handling for all c15 registers
On 01/04/2012 11:50 AM, Peter Maydell wrote:
> On 4 January 2012 16:53, Mark Langsdorf wrote:
>> +} else if ((op1 == 0) && (op2 == 0)) {
>> +/* power_control should be set to maximum latency. Again,
>> + default
Add dummy register support for the cp15, CRn=c15 registers.
config_base_register and power_control_register currently
default to 0, but may have improved support after the QOM
CPU patches are finished.
Signed-off-by: Mark Langsdorf
---
Changes from v6
Added the diagnostic registers
Add dummy register support for the cp15, CRn=c15 registers and
for c1 SCR.
config_base_register and power_control_register currently
default to 0, but may have improved support after the QOM
CPU patches are finished.
Signed-off-by: Mark Langsdorf
---
Changes from v7
Formatted improved
On 01/04/2012 06:22 PM, Peter Maydell wrote:
> On 5 January 2012 00:14, Mark Langsdorf wrote:
>> Add dummy register support for the cp15, CRn=c15 registers and
>> for c1 SCR.
>
> Can you drop the SCR code, please? This needs to be done properly
> as part of trust
Add dummy register support for the cp15, CRn=c15 registers.
config_base_register and power_control_register currently
default to 0, but may have improved support after the QOM
CPU patches are finished.
Signed-off-by: Mark Langsdorf
---
Changes from v8
Removed c1_scr
Changes from v7
From: Rob Herring
Add support for ahci on sysbus.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v1, v2
Corrected indentation of PlatAHCIState members
Made plat_ahci_info into a single structure, not a list
hw/ide/ahci.c | 31
From: Rob Herring
Use AHCIState instead of AHCIPCIState so the function can be used for
non-PCI based AHCI controllers.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v1, v2
None
hw/ide/ahci.c | 14 +++---
hw/ide/ich.c |4 ++--
2 files
On 01/05/2012 08:26 AM, Alexander Graf wrote:
>
> On 05.01.2012, at 15:16, Andreas Färber wrote:
>
>> Am 05.01.2012 14:52, schrieb Mark Langsdorf:
>>> From: Rob Herring
>>>
>>> Add support for ahci on sysbus.
>>>
>>> S
On 01/05/2012 09:33 AM, Peter Maydell wrote:
> On 5 January 2012 13:16, Mark Langsdorf wrote:
>> Add dummy register support for the cp15, CRn=c15 registers.
>>
>> config_base_register and power_control_register currently
>> default to 0, but may have improved support a
model requires c1_scr, which Peter says is part of
Trustzone. I may have missed something, though.
--Mark Langsdorf
Calxeda, Inc.
This patch series adds support for the Calxeda Highbank SoC.
It depends on my previous patch series "various ARM fixes for
Calxeda Highbank" and "ahci: convert ahci_reset to use AHCIState".
Some of the patches are carried voer from "Various ARM fixes
for Calxeda Highbank" and were reviewed but not
From: Rob Herring
Add support for ahci on sysbus.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v3
Renamed plat-ahci to sysbus-ahci
Changes from v1, v2
Corrected indentation of PlatAHCIState members
Made plat_ahci_info into a single
This adds very basic support for XG-mac ethernet core from Synopsis and
others. Missing things include:
- statistics counters
- WoL support
- rx checksum offload
- chained descriptors (only linear descriptor ring)
- broadcast and multicast handling
Signed-off-by: Rob Herring
Signed-off-by: Mark
From: Rob Herring
Adds support for Calxeda's Highbank SoC.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Makefile.target |1 +
hw/highbank.c | 227 +++
2 files changed, 228 insertions(+), 0 deletions(-)
create
appropriately.
Set the maximum theoretically number of GIC interrupts to 1020 and
update the save/restore code to only use the appropriate number for
each SoC.
Signed-off-by: Mark Langsdorf
---
Changes from v4, v5
None
Changes from v3
Increase maximum number of GIC interrupts to 1020
From: Rob Herring
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
target-arm/cpu.h |3 ++-
target-arm/helper.c |9 +
target-arm/machine.c |2 ++
3 files changed, 13 insertions(+), 1 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index
On 01/06/2012 10:29 AM, Peter Maydell wrote:
> On 5 January 2012 20:02, Mark Langsdorf wrote:
>> From: Rob Herring
>>
>> Adds support for Calxeda's Highbank SoC.
>
> Is there a test kernel image/etc we can use to confirm that this all works?
The 3.2 kernel shoul
On 01/06/2012 11:04 AM, Peter Maydell wrote:
> On 6 January 2012 16:58, Mark Langsdorf wrote:
>> On 01/06/2012 10:29 AM, Peter Maydell wrote:
>>>> +sysram = g_new(MemoryRegion, 1);
>>>> +memory_region_init_ram(sysram, "highbank.sysram", 0x8
On 01/06/2012 10:29 AM, Peter Maydell wrote:
> On 5 January 2012 20:02, Mark Langsdorf wrote:
>> +static void hb_regs_write(void *opaque, target_phys_addr_t offset,
>> + uint64_t value, unsigned size)
>> +{
>> +uint32_t *regs = opaque;
>&
This patch series adds support for the Calxeda Highbank SoC.
It depends on my previous patch series "various ARM fixes for
Calxeda Highbank" and "ahci: convert ahci_reset to use AHCIState".
Some of the patches are carried voer from "Various ARM fixes
for Calxeda Highbank" and were reviewed but not
From: Rob Herring
Add support for ahci on sysbus.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v3
Renamed plat-ahci to sysbus-ahci
Changes from v1, v2
Corrected indentation of PlatAHCIState members
Made plat_ahci_info into a single
Signed-off-by: Mark Langsdorf
---
hw/arm_timer.c |3 ---
1 files changed, 0 insertions(+), 3 deletions(-)
diff --git a/hw/arm_timer.c b/hw/arm_timer.c
index 60e1c63..15d493f 100644
--- a/hw/arm_timer.c
+++ b/hw/arm_timer.c
@@ -272,11 +272,8 @@ static int sp804_init(SysBusDevice *dev
From: Rob Herring
Adds support for Calxeda's Highbank SoC.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v1
Restructed the loading of sysram.bin and made it more clearly optional
Made the regs structure into a proper qdev/sysbus o
From: Rob Herring
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
target-arm/cpu.h |3 ++-
target-arm/helper.c |9 +
target-arm/machine.c |2 ++
3 files changed, 13 insertions(+), 1 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index
This adds very basic support for XG-mac ethernet core from Synopsis and
others. Missing things include:
- statistics counters
- WoL support
- rx checksum offload
- chained descriptors (only linear descriptor ring)
- broadcast and multicast handling
Signed-off-by: Rob Herring
Signed-off-by: Mark
appropriately.
Set the maximum theoretically number of GIC interrupts to 1020 and
update the save/restore code to only use the appropriate number for
each SoC.
Signed-off-by: Mark Langsdorf
---
Changes from v5
Clarify the commit message
Rename GIC_NIRQ to GIC_MAXIRQ and change usage
From: Rob Herring
Add support for ahci on sysbus.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Reviewed-by: Andreas Färber
---
Changes from v7
None
Changes from v5, v6
Skipped
Changes from v4
replaced all references to Plat|plat_ with sysbus_
made
From: Rob Herring
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Reviewed-by: Peter Maydell
---
Changes from v7
None
Changes from v1, v2, v3, v4, v5, v6
Skipped
target-arm/cpu.h |3 ++-
target-arm/helper.c |9 +
target-arm/machine.c |2
This adds very basic support for XG-mac ethernet core from Synopsis and
others. Missing things include:
- statistics counters
- WoL support
- rx checksum offload
- chained descriptors (only linear descriptor ring)
- broadcast and multicast handling
Signed-off-by: Rob Herring
Signed-off-by: Mark
From: Rob Herring
Adds support for Calxeda's Highbank SoC.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v7
None
Changes from v3, v4, v5, v6
Skipped
Changes from v2
Created a reset function for highbank_regs
Handled creation of
The current comment says that the arm_timers are restricted to between
32 KHz and 1 MHz, but sp804 TRM does not specify those limits.
Signed-off-by: Mark Langsdorf
Reviewed-by: Andreas Färber
---
Changes from v7
None
Changes from v2, v3, v4, v5, v6
Skipped
Changes from v1
This patch series adds support for the Calxeda Highbank SoC.
It depends on my previous patch series "various ARM fixes for
Calxeda Highbank" and "ahci: convert ahci_reset to use AHCIState".
Some of the patches are carried voer from "Various ARM fixes
for Calxeda Highbank" and were reviewed but not
appropriately.
Set the maximum theoretically number of GIC interrupts to 1020 and
update the save/restore code to only use the appropriate number for
each SoC.
Signed-off-by: Mark Langsdorf
---
Changes from v7
Removed unnecessary vmstate_register
Changes from v6
Removed trailing
appropriately.
Set the maximum theoretically number of GIC interrupts to 1020 and
update the save/restore code to only use the appropriate number for
each SoC.
Signed-off-by: Mark Langsdorf
---
Changes from v5
Clarify the commit message
Rename GIC_NIRQ to GIC_MAXIRQ and change usage
From: Rob Herring
Add support for ahci on sysbus.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v4
replaced all references to Plat|plat_ with sysbus_
made the number of ports into a qdev property
added dummy migration support
Changes from v3
The current comment says that the arm_timers are restricted to between
32 KHz and 1 MHz, but sp804 TRM does not specify those limits.
Signed-off-by: Mark Langsdorf
Reviewed-by: Andreas Färber
---
Changes from v7, v8
None
Changes from v2, v3, v4, v5, v6
Skipped
Changes from v1
From: Rob Herring
Add support for ahci on sysbus.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Reviewed-by: Andreas Färber
---
Changes from v7, v8
None
Changes from v5, v6
Skipped
Changes from v4
replaced all references to Plat|plat_ with sysbus_
This patch series adds support for the Calxeda Highbank SoC.
It depends on my previous patch series "various ARM fixes for
Calxeda Highbank" and "ahci: convert ahci_reset to use AHCIState".
Some of the patches are carried over from "Various ARM fixes
for Calxeda Highbank" and were reviewed but not
1 - 100 of 172 matches
Mail list logo
