[PATCH v5 02/15] target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c

From: Bruno Larsen Move REQUIRE_ALTIVEC to translate.c and rename it to REQUIRE_VECTOR. Signed-off-by: Bruno Larsen Signed-off-by: Matheus Ferst Signed-off-by: Fernando Valle Signed-off-by: Luis Pires Reviewed-by: Richard Henderson Acked-by: David Gibson --- target/ppc/translate.c

[PATCH v5 11/15] target/ppc: Move dcmp{u, o}[q], dts{tex, tsf, tsfi}[q] to decodetree

Significance Quad dtstsfi: DFP Test Significance Immediate dtstsfiq: DFP Test Significance Immediate Quad Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 20 target/ppc/helper.h | 20 target/ppc/insn32.decode

[PATCH v5 05/15] host-utils: Introduce mulu128

Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/qemu/host-utils.h | 36 1 file changed, 36 insertions(+) diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index a3a7ced78d..ca979dc6cc 100644 --- a/include/qemu/host

[PATCH v5 03/15] target/ppc: Introduce REQUIRE_FPU

From: Fernando Valle Signed-off-by: Fernando Valle Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- target/ppc/translate.c | 8 1 file changed, 8 insertions(+) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c2fafebd1c..48a484eef6 100644 --- a/target

[PATCH v5 15/15] target/ppc: Move ddedpd[q], denbcd[q], dscli[q], dscri[q] to decodetree

Significand Right Immediate dscriq: DFP Shift Significand Right Immediate Quad Also deleted dfp-ops.c.inc, now that all PPC DFP instructions were moved to decodetree. Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c

[PATCH v5 08/15] target/ppc: Do not update nip on DFP instructions

Before moving the existing DFP instructions to decodetree, drop the nip update that shouldn't be done for these instructions. Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- target/ppc/translate/dfp-impl.c.inc | 8 1 file changed, 8 deletions(-) diff --git a/targe

[PATCH v5 06/15] libdecnumber: Introduce decNumberIntegralToInt128

This will be used to implement PowerPC's dctfixqq. Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/libdecnumber/decNumber.h | 2 + include/libdecnumber/decNumberLocal.h | 2 +- libdecnumber/decContext.c | 7 +- libdecnumber/decNumber.c

[PATCH v5 00/15] target/ppc: DFP instructions using decodetree

decNumberIntegralToInt128 Changes in v2: - Renamed abs64() to uabs64() Bruno Larsen (1): target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c Fernando Valle (1): target/ppc: Introduce REQUIRE_FPU Luis Pires (13): libdecnumber: introduce decNumberFrom[U]Int128 target/ppc: Implement DCFFIXQ

[PATCH v5 10/15] target/ppc: Move d{add, sub, mul, div, iex}[q] to decodetree

-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 20 +-- target/ppc/helper.h | 20 +-- target/ppc/insn32.decode| 31 ++-- target/ppc/translate/dfp-impl.c.inc | 56

[PATCH v5 01/15] libdecnumber: introduce decNumberFrom[U]Int128

This will be used to implement PowerPC's dcffixqq. Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/libdecnumber/decNumber.h | 2 ++ libdecnumber/decNumber.c | 36 2 files changed, 38 insertions(+) diff --git a/include/libdecn

[PATCH v5 07/15] target/ppc: Implement DCTFIXQQ

Implement the following PowerISA v3.1 instruction: dctfixqq: DFP Convert To Fixed Quadword Quad Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 52 + target/ppc/helper.h | 1 + target/ppc/insn32

[PATCH v5 04/15] target/ppc: Implement DCFFIXQQ

Implement the following PowerISA v3.1 instruction: dcffixqq: DFP Convert From Fixed Quadword Quad Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 12 target/ppc/helper.h | 1 + target/ppc/insn32.decode

[PATCH v5 12/15] target/ppc: Move dquai[q], drint{x, n}[q] to decodetree

Without Inexact Quad Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 12 +++ target/ppc/helper.h | 12 +++ target/ppc/insn32.decode| 23 + target/ppc/translate/dfp

[PATCH v5 13/15] target/ppc: Move dqua[q], drrnd[q] to decodetree

Move the following instructions to decodetree: dqua: DFP Quantize dquaq: DFP Quantize Quad drrnd: DFP Reround drrndq: DFP Reround Quad Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 8 ++--- target

[PATCH v5 09/15] target/ppc: Move dtstdc[q]/dtstdg[q] to decodetree

Move the following instructions to decodetree: dtstdc: DFP Test Data Class dtstdcq: DFP Test Data Class Quad dtstdg: DFP Test Data Group dtstdgq: DFP Test Data Group Quad Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c

[PATCH v5 14/15] target/ppc: Move dct{dp, qpq}, dr{sp, dpq}, dc{f, t}fix[q], dxex[q] to decodetree

Convert To Fixed Quad dxex:DFP Extract Biased Exponent dxexq: DFP Extract Biased Exponent Quad Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 20 +-- target/ppc/helper.h | 20

[PATCH v4 00/19] target/ppc: DFP instructions using decodetree

line' from times_* functions in ppc/translate.c - Used uadd64_overflow in mulu128 - Removed unnecessary 'else' from decNumberIntegralToInt128 Changes in v2: - Renamed abs64() to uabs64() Bruno Larsen (1): target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c Fernando Valle (1)

[PATCH v4 02/19] host-utils: move udiv_qrnnd() to host-utils

Move udiv_qrnnd() from include/fpu/softfloat-macros.h to host-utils, so it can be reused by divu128(). Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/fpu/softfloat-macros.h | 82 -- include/qemu/host-utils.h | 81

[PATCH v4 08/19] target/ppc: Implement DCFFIXQQ

Implement the following PowerISA v3.1 instruction: dcffixqq: DFP Convert From Fixed Quadword Quad Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 12 target/ppc/helper.h | 1 + target/ppc/insn32.decode

[PATCH v4 03/19] host-utils: add 128-bit quotient support to divu128/divs128

These will be used to implement new decimal floating point instructions from Power ISA 3.1. The remainder is now returned directly by divu128/divs128, freeing up phigh to receive the high 64 bits of the quotient. Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/hw/clock.h

[PATCH v4 01/19] host-utils: move checks out of divu128/divs128

In preparation for changing the divu128/divs128 implementations to allow for quotients larger than 64 bits, move the div-by-zero and overflow checks to the callers. Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/hw/clock.h| 5 +++-- include/qemu/host-utils.h | 36

[PATCH v4 04/19] host-utils: add unit tests for divu128/divs128

Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- tests/unit/meson.build | 1 + tests/unit/test-div128.c | 197 +++ 2 files changed, 198 insertions(+) create mode 100644 tests/unit/test-div128.c diff --git a/tests/unit/meson.build b/tests

[PATCH v4 13/19] target/ppc: Move dtstdc[q]/dtstdg[q] to decodetree

Move the following instructions to decodetree: dtstdc: DFP Test Data Class dtstdcq: DFP Test Data Class Quad dtstdg: DFP Test Data Group dtstdgq: DFP Test Data Group Quad Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c

[PATCH v4 12/19] target/ppc: Do not update nip on DFP instructions

Before moving the existing DFP instructions to decodetree, drop the nip update that shouldn't be done for these instructions. Signed-off-by: Luis Pires --- target/ppc/translate/dfp-impl.c.inc | 8 1 file changed, 8 deletions(-) diff --git a/target/ppc/translate/dfp-impl.c.i

[PATCH v4 14/19] target/ppc: Move d{add, sub, mul, div, iex}[q] to decodetree

-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 20 +-- target/ppc/helper.h | 20 +-- target/ppc/insn32.decode| 31 ++-- target/ppc/translate/dfp-impl.c.inc | 56

[PATCH v4 05/19] libdecnumber: introduce decNumberFrom[U]Int128

This will be used to implement PowerPC's dcffixqq. Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/libdecnumber/decNumber.h | 2 ++ libdecnumber/decNumber.c | 36 2 files changed, 38 insertions(+) diff --git a/include/libdecn

[PATCH v4 16/19] target/ppc: Move dquai[q], drint{x, n}[q] to decodetree

Without Inexact Quad Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 12 +++ target/ppc/helper.h | 12 +++ target/ppc/insn32.decode| 23 + target/ppc/translate/dfp

[PATCH v4 15/19] target/ppc: Move dcmp{u, o}[q], dts{tex, tsf, tsfi}[q] to decodetree

Significance Quad dtstsfi: DFP Test Significance Immediate dtstsfiq: DFP Test Significance Immediate Quad Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 20 target/ppc/helper.h | 20 target/ppc/insn32.decode

[PATCH v4 06/19] target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c

From: Bruno Larsen Move REQUIRE_ALTIVEC to translate.c and rename it to REQUIRE_VECTOR. Signed-off-by: Bruno Larsen Signed-off-by: Matheus Ferst Signed-off-by: Fernando Valle Signed-off-by: Luis Pires Reviewed-by: Richard Henderson Acked-by: David Gibson --- target/ppc/translate.c

[PATCH v4 07/19] target/ppc: Introduce REQUIRE_FPU

From: Fernando Valle Signed-off-by: Fernando Valle Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- target/ppc/translate.c | 8 1 file changed, 8 insertions(+) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c2fafebd1c..48a484eef6 100644 --- a/target

[PATCH v4 09/19] host-utils: Introduce mulu128

Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/qemu/host-utils.h | 36 1 file changed, 36 insertions(+) diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index a3a7ced78d..ca979dc6cc 100644 --- a/include/qemu/host

[PATCH v4 10/19] libdecnumber: Introduce decNumberIntegralToInt128

This will be used to implement PowerPC's dctfixqq. Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- include/libdecnumber/decNumber.h | 2 + include/libdecnumber/decNumberLocal.h | 2 +- libdecnumber/decContext.c | 7 +- libdecnumber/decNumber.c

[PATCH v4 11/19] target/ppc: Implement DCTFIXQQ

Implement the following PowerISA v3.1 instruction: dctfixqq: DFP Convert To Fixed Quadword Quad Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 52 + target/ppc/helper.h | 1 + target/ppc/insn32

[PATCH v4 17/19] target/ppc: Move dqua[q], drrnd[q] to decodetree

Move the following instructions to decodetree: dqua: DFP Quantize dquaq: DFP Quantize Quad drrnd: DFP Reround drrndq: DFP Reround Quad Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 8 ++--- target

[PATCH v4 18/19] target/ppc: Move dct{dp, qpq}, dr{sp, dpq}, dc{f, t}fix[q], dxex[q] to decodetree

Convert To Fixed Quad dxex:DFP Extract Biased Exponent dxexq: DFP Extract Biased Exponent Quad Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 20 +-- target/ppc/helper.h | 20

[PATCH v4 19/19] target/ppc: Move ddedpd[q], denbcd[q], dscli[q], dscri[q] to decodetree

Significand Right Immediate dscriq: DFP Shift Significand Right Immediate Quad Also deleted dfp-ops.c.inc, now that all PPC DFP instructions were moved to decodetree. Signed-off-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c

[PATCH] decodetree: Allow custom var width load functions

used by the PowerPC decodetree code. Signed-off-by: Luis Pires --- scripts/decodetree.py | 18 +++--- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/scripts/decodetree.py b/scripts/decodetree.py index fef5eeaf42..c88dbdb4c3 100644 --- a/scripts/decodetree.py +++ b

[PATCH] decodetree: Allow empty input files for var width

This was broken when varinsnwidth was specified. Signed-off-by: Luis Pires --- scripts/decodetree.py | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/scripts/decodetree.py b/scripts/decodetree.py index 3450a2a08d..fef5eeaf42 100644 --- a/scripts/decodetree.py

[PATCH 1/5] decodetree: Add support for 64-bit instructions

Allow '64' to be specified for the instruction width command line params and use the appropriate insn/field data types, mask, extract and deposit functions in that case. This will be used to implement the new 64-bit Power ISA 3.1 instructions. Signed-off-by: Luis Pires ---

[PATCH 2/5] decodetree: Fix empty input files for varinsnwidth

Decodetree would throw an error when the input file was empty and --varinsnwidth was specified. Signed-off-by: Luis Pires --- scripts/decodetree.py | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/scripts/decodetree.py b/scripts/decodetree.py index 4e18f52a65

[PATCH 4/5] target/ppc: Base changes to allow 32/64-bit insns

prefixed instruction cross a 64-byte boundary. Signed-off-by: Luis Pires --- target/ppc/cpu.h | 1 + target/ppc/meson.build | 5 ++ target/ppc/ppc.decode | 18 target/ppc/translate.c | 191 - 4 files changed, 174 insertions(+), 41

[PATCH 0/5] Base for adding PowerPC 64-bit instructions

- and 64-bit instructions to be decoded using decodetree, and finishes by adding the implementation for 2 simple instructions to demonstrate the new approach: - addi (replacing the legacy implementation) - paddi (new) Luis Pires (5): decodetree: Add support for 64-bit instructions decodetree

[PATCH 5/5] target/ppc: Implement paddi and replace addi insns

This implements the Power ISA 3.1 prefixed (64-bit) paddi instruction, while also replacing the legacy addi implementation. Both using the decode tree. Signed-off-by: Luis Pires Signed-off-by: Matheus Ferst --- target/ppc/ppc.decode | 8 +++ target/ppc/translate.c

[PATCH 3/5] decodetree: Allow custom var width load functions

used by the PowerPC decodetree code. Signed-off-by: Luis Pires --- scripts/decodetree.py | 18 +++--- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/scripts/decodetree.py b/scripts/decodetree.py index 935b2964e0..a62b8d8d76 100644 --- a/scripts/decodetree.py +++ b

[PATCH] docs/devel: Explain in more detail the TB chaining mechanisms

Signed-off-by: Luis Pires --- Being new to QEMU, I went through the code to try to understand how lookup_and_goto_ptr, goto_tb and exit_tb work, and when each should be used. Thought I'd share what I learned by documenting it, as it might be useful to other people starting to work on TCG

[PATCH 1/2] docs/devel: Add a single top-level header to MTTCG's doc

Without a single top-level header in the .rst file, the index ended up linking to all of the top-level headers separately. Now the index links to the top-level header at the beginning of the document and any inner headers are correctly linked as sub-items in the index. Signed-off-by: Luis Pires

[PATCH RESEND 1/1] docs/devel: Add a single top-level header to MTTCG's doc

Without a single top-level header in the .rst file, the index ended up linking to all of the top-level headers separately. Now the index links to the top-level header at the beginning of the document and any inner headers are correctly linked as sub-items in the index. Signed-off-by: Luis Pires

[PATCH v2] docs/devel: Explain in more detail the TB chaining mechanisms

Signed-off-by: Luis Pires --- v2: - s/outer execution loop/main loop - Mention re-evaluation of cpu_exec_interrupt() - Changed wording on lookup_and_goto_ptr() - Added more details to step 2 of goto+tb + exit_tb - Added details about when goto_tb + exit_tb cannot be used docs/devel/tcg.rst

[PATCH v3] docs/devel: Explain in more detail the TB chaining mechanisms

Signed-off-by: Luis Pires --- v3: - Dropped "most common" from the sentence introducing the chaining mechanisms - Changed wording about using the TB address returned by exit_tb v2: - s/outer execution loop/main loop - Mention re-evaluation of cpu_exec_interrupt() - Changed

[PATCH] target/ppc: fix single-step exception regression

. Signed-off-by: Luis Pires Reported-by: Matheus Ferst --- target/ppc/translate.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index ea200f9637..0dd04696a6 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c

[PATCH v2] target/ppc: fix single-step exception regression

. Signed-off-by: Luis Pires Reported-by: Matheus Ferst --- v2: - Removed incorrect nip update from ppc_tr_tb_stop() target/ppc/translate.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index ea200f9637..14a0bb7168 100644

[PATCH v2 00/15] Base for adding PowerPC 64-bit instructions

/stores - Added check for prefixed insn support in cpu flags This code contains contributions from Richard Henderson, Matheus Ferst and myself. Luis Pires (2): decodetree: Add support for 64-bit instructions target/ppc: Check cpu flags for prefixed insn support Richard Henderson (13): target

[PATCH v2 02/15] target/ppc: Add cia field to DisasContext

From: Richard Henderson Signed-off-by: Richard Henderson --- target/ppc/translate.c | 34 ++ 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 0984ce637b..ee25badba2 100644 --- a/target/ppc/trans

[PATCH v2 01/15] decodetree: Add support for 64-bit instructions

ned-off-by: Luis Pires Message-Id: Signed-off-by: Richard Henderson --- docs/devel/decodetree.rst | 5 +++-- scripts/decodetree.py | 26 +- 2 files changed, 24 insertions(+), 7 deletions(-) diff --git a/docs/devel/decodetree.rst b/docs/devel/decodetree.rst index

[PATCH v2 04/15] target/ppc: Move DISAS_NORETURN setting into gen_exception*

From: Richard Henderson There are other valid settings for is_jmp besides DISAS_NEXT and DISAS_NORETURN, so eliminating that dichotomy from ppc_tr_translate_insn is helpful. Signed-off-by: Richard Henderson Signed-off-by: Luis Pires --- target/ppc/translate.c | 65

[PATCH v2 06/15] target/ppc: Mark helper_raise_exception* as noreturn

From: Richard Henderson Signed-off-by: Richard Henderson --- target/ppc/helper.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 6a4dccf70c..af5b3586d1 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -1,5 +1,5

[PATCH v2 03/15] target/ppc: Split out decode_legacy

From: Richard Henderson Signed-off-by: Richard Henderson --- target/ppc/translate.c | 115 +++-- 1 file changed, 64 insertions(+), 51 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index ee25badba2..ebe5afe7ae 100644 --- a/target/p

[PATCH v2 07/15] target/ppc: Use translator_loop_temp_check

From: Richard Henderson The special logging is unnecessary. It will have been done immediately before in the log file. Signed-off-by: Richard Henderson --- target/ppc/translate.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/trans

[PATCH v2 05/15] target/ppc: Tidy exception vs exit_tb

From: Richard Henderson We do not need to emit an exit_tb after an exception, as the latter will exit via longjmp. Signed-off-by: Richard Henderson --- target/ppc/translate.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/transla

[PATCH v2 08/15] target/ppc: Add infrastructure for prefixed insns

From: Richard Henderson Signed-off-by: Richard Henderson Signed-off-by: Luis Pires --- target/ppc/cpu.h | 1 + target/ppc/insn32.decode | 18 + target/ppc/insn64.decode | 18 + target/ppc/meson.build

[PATCH v2 10/15] target/ppc: Implement PNOP

From: Richard Henderson Signed-off-by: Richard Henderson --- target/ppc/insn64.decode | 5 + target/ppc/translate/fixedpoint-impl.c.inc | 12 2 files changed, 17 insertions(+) diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode index 68ed2cbff8.

[PATCH v2 11/15] target/ppc: Move D/DS/X-form integer loads to decodetree

From: Richard Henderson These are all connected by macros in the legacy decoding. Signed-off-by: Richard Henderson Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode | 37 target/ppc/translate.c | 136 ++- target/ppc/translate/fix

[PATCH v2 09/15] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI

From: Richard Henderson Signed-off-by: Richard Henderson --- target/ppc/insn32.decode | 8 + target/ppc/insn64.decode | 14 target/ppc/translate.c | 29 --- target/ppc/translate/fixedpoint-impl.c.inc | 42

[PATCH v2 14/15] target/ppc: Implement prefixed integer store instructions

From: Richard Henderson Signed-off-by: Richard Henderson --- target/ppc/insn64.decode | 12 target/ppc/translate/fixedpoint-impl.c.inc | 20 2 files changed, 32 insertions(+) diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode in

[PATCH v2 12/15] target/ppc: Implement prefixed integer load instructions

From: Richard Henderson Signed-off-by: Richard Henderson --- target/ppc/insn64.decode | 15 ++ target/ppc/translate/fixedpoint-impl.c.inc | 60 ++ 2 files changed, 75 insertions(+) diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode index

[PATCH v2 13/15] target/ppc: Move D/DS/X-form integer stores to decodetree

From: Richard Henderson These are all connected by macros in the legacy decoding. Signed-off-by: Richard Henderson --- target/ppc/insn32.decode | 22 ++ target/ppc/translate.c | 85 +- target/ppc/translate/fixedpoint-impl.c.inc | 84

[PATCH v2 15/15] target/ppc: Check cpu flags for prefixed insn support

Prefixed instructions were introduced in Power ISA 3.1 Signed-off-by: Luis Pires --- target/ppc/translate.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 7422ea4e13..f4802a4f08 100644 --- a/target/ppc/translate.c

[PATCH] target/ppc: fix setting of CR flags in bcdcfsq

all zero. This would happen for source values of +/-10^31, +/-10^32, etc. The new implementation fixes this and also skips the result calculation altogether in case of src overflow. Signed-off-by: Luis Pires --- target/ppc/int_helper.c | 61 - 1 file

[PATCH 00/19] target/ppc: DFP instructions using decodetree

patch series. Based-on: 20210823150235.35759-1-luis.pi...@eldorado.org.br (target/ppc: fix setting of CR flags in bcdcfsq) -- Luis Pires Instituto de Pesquisas ELDORADO Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html> Bruno Larsen (1): target/ppc: Move REQUIR

[PATCH 01/19] host-utils: Fix overflow detection in divu128()

The previous code didn't detect overflows if the high 64-bit of the dividend were equal to the 64-bit divisor. In that case, 64 bits wouldn't be enough to hold the quotient. Signed-off-by: Luis Pires --- util/host-utils.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --

[PATCH 04/19] host-utils: add 128-bit quotient support to divu128/divs128

mproved, due to the smaller number of shift-subtract iterations. Signed-off-by: Luis Pires --- include/hw/clock.h| 8 +-- include/qemu/host-utils.h | 20 -- target/ppc/int_helper.c | 13 ++-- util/host-utils.c | 128 +++--- 4 files

[PATCH 02/19] host-utils: move abs64() to host-utils

Move abs64 to host-utils so it can be reused elsewhere. Also made it inline. Signed-off-by: Luis Pires --- hw/i386/kvm/i8254.c | 5 - include/qemu/host-utils.h | 8 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/hw/i386/kvm/i8254.c b/hw/i386/kvm/i8254.c index

[PATCH 06/19] libdecnumber: introduce decNumberFrom[U]Int128

This will be used to implement PowerPC's dcffixqq. Signed-off-by: Luis Pires --- include/libdecnumber/decNumber.h | 2 ++ libdecnumber/decNumber.c | 36 2 files changed, 38 insertions(+) diff --git a/include/libdecnumber/decNumber.h b/in

[PATCH 05/19] host-utils: add unit tests for divu128/divs128

Signed-off-by: Luis Pires --- tests/unit/meson.build | 1 + tests/unit/test-div128.c | 185 +++ 2 files changed, 186 insertions(+) create mode 100644 tests/unit/test-div128.c diff --git a/tests/unit/meson.build b/tests/unit/meson.build index 5736d285b2

[PATCH 03/19] host-utils: move checks out of divu128/divs128

In preparation for changing the divu128/divs128 implementations to allow for quotients larger than 64 bits, move the div-by-zero and overflow checks to the callers. Signed-off-by: Luis Pires --- include/hw/clock.h| 5 +++-- include/qemu/host-utils.h | 36

[PATCH 12/19] target/ppc: Implement DCTFIXQQ

Implement the following PowerISA v3.1 instruction: dctfixqq: DFP Convert To Fixed Quadword Quad Signed-off-by: Luis Pires --- target/ppc/dfp_helper.c | 53 + target/ppc/helper.h | 1 + target/ppc/insn32.decode| 5 +++ target

[PATCH 08/19] target/ppc: Introduce REQUIRE_FPU

From: Fernando Valle Signed-off-by: Fernando Valle Signed-off-by: Luis Pires --- target/ppc/translate.c | 8 1 file changed, 8 insertions(+) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 4749ecdaa9..5489b4b6e0 100644 --- a/target/ppc/translate.c +++ b/target/ppc

[PATCH 07/19] target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c

From: Bruno Larsen Move REQUIRE_ALTIVEC to translate.c and rename it to REQUIRE_VECTOR. Signed-off-by: Bruno Larsen Signed-off-by: Matheus Ferst Signed-off-by: Fernando Valle Signed-off-by: Luis Pires --- target/ppc/translate.c | 8 target/ppc/translate/vector

[PATCH 15/19] target/ppc: Move dcmp{u, o}[q], dts{tex, tsf, tsfi}[q] to decodetree

Significance Quad dtstsfi: DFP Test Significance Immediate dtstsfiq: DFP Test Significance Immediate Quad Signed-off-by: Luis Pires --- target/ppc/dfp_helper.c | 20 target/ppc/helper.h | 20 target/ppc/insn32.decode| 29 +++ target

[PATCH 14/19] target/ppc: Move d{add, sub, mul, div, iex}[q] to decodetree

-by: Luis Pires --- target/ppc/dfp_helper.c | 20 +- target/ppc/helper.h | 20 +- target/ppc/insn32.decode| 31 +++- target/ppc/translate/dfp-impl.c.inc | 57 ++--- target/ppc/translate/dfp-ops.c.inc | 19

[PATCH 09/19] target/ppc: Implement DCFFIXQQ

Implement the following PowerISA v3.1 instruction: dcffixqq: DFP Convert From Fixed Quadword Quad Signed-off-by: Luis Pires --- target/ppc/dfp_helper.c | 11 +++ target/ppc/helper.h | 1 + target/ppc/insn32.decode| 8 target/ppc

[PATCH 10/19] host-utils: Introduce mulu128

Signed-off-by: Luis Pires --- include/qemu/host-utils.h | 38 ++ 1 file changed, 38 insertions(+) diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index 8e8cab9a3e..2e3b5ad989 100644 --- a/include/qemu/host-utils.h +++ b/include/qemu/host

[PATCH 16/19] target/ppc: Move dquai[q], drint{x,n}[q] to decodetree

Without Inexact Quad Signed-off-by: Luis Pires --- target/ppc/dfp_helper.c | 12 +++ target/ppc/helper.h | 12 +++ target/ppc/insn32.decode| 23 + target/ppc/translate/dfp-impl.c.inc | 52 + target/ppc/translate

[PATCH 11/19] libdecnumber: Introduce decNumberIntegralToInt128

This will be used to implement PowerPC's dctfixqq. Signed-off-by: Luis Pires --- include/libdecnumber/decNumber.h | 2 + include/libdecnumber/decNumberLocal.h | 2 +- libdecnumber/decContext.c | 7 +- libdecnumber/decNumber.c | 94 +

[PATCH 13/19] target/ppc: Move dtstdc[q]/dtstdg[q] to decodetree

Move the following instructions to decodetree: dtstdc: DFP Test Data Class dtstdcq: DFP Test Data Class Quad dtstdg: DFP Test Data Group dtstdgq: DFP Test Data Group Quad Signed-off-by: Luis Pires --- target/ppc/dfp_helper.c | 8 +++ target/ppc/helper.h | 8

[PATCH 18/19] target/ppc: Move dct{dp, qpq}, dr{sp, dpq}, dc{f, t}fix[q], dxex[q] to decodetree

Convert To Fixed Quad dxex:DFP Extract Biased Exponent dxexq: DFP Extract Biased Exponent Quad Signed-off-by: Luis Pires --- target/ppc/dfp_helper.c | 20 +-- target/ppc/helper.h | 20 +-- target/ppc/insn32.decode| 23 target

[PATCH 17/19] target/ppc: Move dqua[q], drrnd[q] to decodetree

Move the following instructions to decodetree: dqua: DFP Quantize dquaq: DFP Quantize Quad drrnd: DFP Reround drrndq: DFP Reround Quad Signed-off-by: Luis Pires --- target/ppc/dfp_helper.c | 8 ++--- target/ppc/helper.h | 8 ++--- target/ppc/insn32.decode

[PATCH 19/19] target/ppc: Move ddedpd[q], denbcd[q], dscli[q], dscri[q] to decodetree

Significand Right Immediate dscriq: DFP Shift Significand Right Immediate Quad Also deleted dfp-ops.c.inc, now that all PPC DFP instructions were moved to decodetree. Signed-off-by: Luis Pires --- target/ppc/dfp_helper.c | 16 - target/ppc/helper.h | 16

[PATCH v2 00/19] target/ppc: DFP instructions using decodetree

umberFrom[U]Int128 target/ppc: Implement DCFFIXQQ host-utils: Introduce mulu128 libdecnumber: Introduce decNumberIntegralToInt128 target/ppc: Implement DCTFIXQQ target/ppc: Move dcmp{u,o}[q],dts{tex,tsf,tsfi}[q] to decodetree -- Luis Pires Instituto de Pesquisas ELDORADO Aviso Legal -

[PATCH v2 01/19] host-utils: Fix overflow detection in divu128()

The previous code didn't detect overflows if the high 64-bit of the dividend were equal to the 64-bit divisor. In that case, 64 bits wouldn't be enough to hold the quotient. Signed-off-by: Luis Pires --- util/host-utils.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --

[PATCH v2 06/19] libdecnumber: introduce decNumberFrom[U]Int128

This will be used to implement PowerPC's dcffixqq. Signed-off-by: Luis Pires --- include/libdecnumber/decNumber.h | 2 ++ libdecnumber/decNumber.c | 36 2 files changed, 38 insertions(+) diff --git a/include/libdecnumber/decNumber.h b/in

[PATCH v2 03/19] host-utils: move checks out of divu128/divs128

In preparation for changing the divu128/divs128 implementations to allow for quotients larger than 64 bits, move the div-by-zero and overflow checks to the callers. Signed-off-by: Luis Pires --- include/hw/clock.h| 5 +++-- include/qemu/host-utils.h | 36

[PATCH v2 02/19] host-utils: move abs64() to host-utils as uabs64()

Move abs64 to host-utils as uabs64, so it can be used elsewhere. The function was renamed to uabs64 and modified to return an unsigned value. This avoids the undefined behavior for common abs implementations, where abs of the most negative value is undefined. Signed-off-by: Luis Pires --- hw

[PATCH v2 04/19] host-utils: add 128-bit quotient support to divu128/divs128

mproved, due to the smaller number of shift-subtract iterations. Signed-off-by: Luis Pires --- include/hw/clock.h| 8 +-- include/qemu/host-utils.h | 20 -- target/ppc/int_helper.c | 13 ++-- util/host-utils.c | 128 +++--- 4 files

[PATCH v2 09/19] target/ppc: Implement DCFFIXQQ

Implement the following PowerISA v3.1 instruction: dcffixqq: DFP Convert From Fixed Quadword Quad Signed-off-by: Luis Pires --- target/ppc/dfp_helper.c | 11 +++ target/ppc/helper.h | 1 + target/ppc/insn32.decode| 8 target/ppc

[PATCH v2 08/19] target/ppc: Introduce REQUIRE_FPU

From: Fernando Valle Signed-off-by: Fernando Valle Signed-off-by: Luis Pires Reviewed-by: David Gibson --- target/ppc/translate.c | 8 1 file changed, 8 insertions(+) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 4749ecdaa9..5489b4b6e0 100644 --- a/target/ppc

[PATCH v2 05/19] host-utils: add unit tests for divu128/divs128

Signed-off-by: Luis Pires --- tests/unit/meson.build | 1 + tests/unit/test-div128.c | 185 +++ 2 files changed, 186 insertions(+) create mode 100644 tests/unit/test-div128.c diff --git a/tests/unit/meson.build b/tests/unit/meson.build index 5736d285b2

[PATCH v2 10/19] host-utils: Introduce mulu128

Signed-off-by: Luis Pires --- include/qemu/host-utils.h | 38 ++ 1 file changed, 38 insertions(+) diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index 6f18b29921..9f40077083 100644 --- a/include/qemu/host-utils.h +++ b/include/qemu/host

[PATCH v2 11/19] libdecnumber: Introduce decNumberIntegralToInt128

This will be used to implement PowerPC's dctfixqq. Signed-off-by: Luis Pires --- include/libdecnumber/decNumber.h | 2 + include/libdecnumber/decNumberLocal.h | 2 +- libdecnumber/decContext.c | 7 +- libdecnumber/decNumber.c | 94 +

[PATCH v2 07/19] target/ppc: Move REQUIRE_ALTIVEC/VECTOR to translate.c

From: Bruno Larsen Move REQUIRE_ALTIVEC to translate.c and rename it to REQUIRE_VECTOR. Signed-off-by: Bruno Larsen Signed-off-by: Matheus Ferst Signed-off-by: Fernando Valle Signed-off-by: Luis Pires --- target/ppc/translate.c | 8 target/ppc/translate/vector

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