doubtful usefulness
* rebased
v2:
* addressed all comments so far from Richard and Aurelien. More detailed
changelog included in the separate patches.
* added missing zero register case for LSA, ALIGN and BITSWAP instructions
Leon Alrae (17):
target-mips: define ISA_MIPS64R6
target-mips: signal
loads / stores
- traps
- legacy accumulator instructions
- COP1X
- MIPS-3D
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
target-mips/translate.c | 64 +--
1 files changed, 56 insertions(+), 8 deletions(-)
diff --git a/target-mips
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
v2:
* move new CPU definition to a separate patch
---
target-mips/mips-defs.h | 28 +++-
1 files changed, 19 insertions(+), 9 deletions(-)
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index
The encoding of LL and SC instruction has changed in MIPS32 Release 6.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
disas/mips.c|9 -
target-mips/translate.c | 29 +++--
2 files changed, 35 insertions(+), 3 deletions(-)
diff --git
Signed-off-by: Leon Alrae
---
v3:
* use sextract32 instead of open coding the bit field extraction
* replace _i64 with _tl in DAHI, DATI and DAUI
* fix misleading LDPC comment
---
disas/mips.c| 42 +-
target-mips/translate.c | 196
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
v2:
* correct conditions to match instruction name
---
disas/mips.c|8
target-mips/translate.c | 16
2 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/disas/mips.c b/disas/mips.c
In R6 the special behaviour for data references is also specified for Kernel
and Supervisor mode. Therefore MIPS_HFLAG_UX is replaced by generic
MIPS_HFLAG_AWRAP indicating enabled 32-bit address wrapping.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
v2:
* set hflag indicating 32
The encoding of PREF, CACHE, LLD and SCD instruction changed in MIPS32R6.
Additionally, the hint codes in PREF instruction greater than or
equal to 24 generate Reserved Instruction Exception.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
disas/mips.c|4
target
functions will contain instructions which were removed in R6.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
v2:
* imm contains shifted value
---
target-mips/translate.c | 229 +--
1 files changed, 160 insertions(+), 69 deletions(-)
di
From: Yongbok Kim
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
disas/mips.c| 44 ++
target-mips/helper.h| 27 ++
target-mips/op_helper.c | 111 +
target-mips/translate.c | 206
JR has been removed in R6 and now this instruction will cause Reserved
Instruction Exception. Therefore use JALR with rd=0 which is equivalent to JR.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
hw/mips/mips_malta.c | 10 +-
1 files changed, 5 insertions(+), 5 deletions
From: Yongbok Kim
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
v3:
* bitswap: use gen_load_gpr instead of optimizing very unlikely case and
making it less readable
v2:
* have separate bitswap and dbitswap helpers and use common function
* use
Status.FR bit must be ignored on write and read as 1 when an implementation of
Release 6 of the Architecture in which a 64-bit floating point unit is
implemented.
Signed-off-by: Leon Alrae
---
v3:
* remove line modifying CP0_Status_rw_bitmask as this is done while defining
CPU
---
target-mips
Use "R6_" prefix in front of all new Multiply / Divide instructions for
easier differentiation between R6 and preR6.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
v2:
* use tcg_gen_mul_* for cases where the high part is discarded
---
disas/mips.c| 16 +++
t
returns y if |y| > |x|,
otherwise maxnum(x,y)
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
v3:
* rename abs argument to ismag
---
fpu/softfloat.c | 37 +++--
include/fpu/softfloat.h |4
2 files changed, 35 inse
From: Yongbok Kim
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
disas/mips.c|2 ++
target-mips/translate.c | 18 --
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/disas/mips.c b/disas/mips.c
index
Signed-off-by: Leon Alrae
---
v3:
* add comment to make it clear that the current definition of MIPS64R6-generic
CPU does not contain support for all MIPS64R6 features yet.
---
target-mips/translate_init.c | 30 ++
1 files changed, 30 insertions(+), 0 deletions
From: Yongbok Kim
Introduce MIPS32R6 Compact Branch instructions which do not have delay slot -
they have forbidden slot instead. However, current implementation does not
support forbidden slot yet.
Add also BC1EQZ and BC1NEZ instructions.
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
.
Signed-off-by: Leon Alrae
---
v3:
* use FOP_PROTO for new instructions and create FLOAT_RINT macro to be
consistent
* use TCG_CALL_NO_RWG_SE flag for float_class helper
---
disas/mips.c| 22 +++
target-mips/helper.h| 20 ++
target-mips/op_helper.c | 104 +++
target-mips
Also consider OPC_SPIM instruction as deleted in R6 because it is overlaping
with MIPS32R6 SDBBP.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
v2:
* check_insn_opc_removed() moved to decode_opc_special2_legacy()
---
disas/mips.c|5 ++
target-mips/translate.c | 121
Move DSP and Loongson instruction to *_legacy functions as they have been
removed in R6.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
target-mips/translate.c | 195 ---
1 files changed, 98 insertions(+), 97 deletions(-)
diff --git a
is in a branch delay slot.
Using error_code to indicate whether AdEL or TLBL was triggered during
instruction fetch, in this case BadInstr is not updated as valid instruction
word is not available.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h |6 +++
target-mips/helper.c| 44
New MIPS features depend on the access type and enum is more convenient than
using the numbers directly.
Signed-off-by: Leon Alrae
---
include/exec/cpu-common.h |6 ++
softmmu_template.h| 26 --
2 files changed, 22 insertions(+), 10 deletions(-)
diff
when the virtual address of a memory load
reference matches a TLB entry whose RI bit is set. This exception type can
only occur if the RI bit is implemented within the TLB and is enabled, this is
denoted by the PageGrain RIE bit.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h|5
support for Config4.IE == 3 only (i.e. TLBINV*
instructions operate on entire MMU).
Single TLB entry can be marked as invalid on TLB entry write by having
EntryHi.EHINV set to 1.
Signed-off-by: Leon Alrae
---
disas/mips.c |2 +
target-mips/cpu.h|7
target
On 19/06/2014 18:43, Richard Henderson wrote:
> You must update CPU_SAVE_VERSION when you change the contents of the save
> data.
>
> For extra credit, consider updating target-mips to VMStateDescription
> structure(s).
>
>
> r~
>
v2 contains updated CPU_SAVE_VERSION.
VMStateDescription str
On 20/06/2014 23:02, Aurelien Jarno wrote:
>> @@ -5198,6 +5199,12 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
>> reg, int sel)
>> gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
>> rn = "DESAVE";
>> break;
>> +case 2 ... 7:
>> +
On 19/06/2014 23:13, Aurelien Jarno wrote:
> I don't think this should implemented that way, as it would have a
> significant impact on the performances. Given we have the fault address
> (we fill EPC), we can fetch the corresponding opcode. There might be
> some code change to do for the branches,
Signed-off-by: Leon Alrae
---
target-mips/cpu.h |2 +-
target-mips/machine.c | 14 ++
2 files changed, 15 insertions(+), 1 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 656f5ca..23bb22c 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
Signed-off-by: Leon Alrae
---
target-mips/helper.c | 21 ++---
1 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 8a997e4..9871273 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -87,7 +87,7 @@ int
PageGrain needs rw bitmask which differs between MIPS architectures.
In pre-R6 if RIXI is supported, PageGrain.XIE and PageGrain.RIE are writeable,
whereas in R6 they are read-only 1.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h|4
target-mips/helper.h |5
Hi Peter,
On 08/07/2014 14:00, Peter Maydell wrote:
> On 8 July 2014 08:57, Leon Alrae wrote:
>> New MIPS features depend on the access type and enum is more convenient than
>> using the numbers directly.
>>
> Mmm, I've thought for a while it would be better to have
In Revision 3 of the architecture, the RI and XI bits were added to the TLB
to enable more secure access of memory pages. These bits (along with the Dirty
bit) allow the implementation of read-only, write-only, no-execute access
policies for mapped pages.
Signed-off-by: Leon Alrae
---
target
CP0_KScratch1-6 registers.
For Release 6, all KScratch registers are required.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h |3 +++
target-mips/translate.c | 44
2 files changed, 47 insertions(+), 0 deletions(-)
diff --git a/target-mips
Hi James,
On 08/07/2014 13:44, James Hogan wrote:
> Hi Leon,
>
> On 08/07/14 08:57, Leon Alrae wrote:
>> BadInstr Register (CP0 Register 8, Select 1)
>> The BadInstr register is a read-only register that capture the most recent
>> instruction which caused an exceptio
to
an unimplemented cp0 register (new registers only)
* updated CPU_SAVE_VERSION,
* added a patch to the series providing mmu_access_type enum.
Leon Alrae (9):
target-mips: add KScratch registers
softmmu: provide softmmu access type enum
target-mips: distinguish between data load and
On 12/06/2015 15:02, Yongbok Kim wrote:
> Refactor those instructions in order to reuse them for microMIPS32
> Release 6.
>
> Signed-off-by: Yongbok Kim
> ---
> target-mips/translate.c | 164 +-
> 1 files changed, 103 insertions(+), 61 deletions(-)
>
On 12/06/2015 15:02, Yongbok Kim wrote:
> Signal a Reserved Instruction exception for removed instruction encoding
> in microMIPS Release 6.
>
> Signed-off-by: Yongbok Kim
> ---
> target-mips/translate.c | 68
> +++
> 1 files changed, 68 insertions(
On 12/06/2015 15:02, Yongbok Kim wrote:
> add microMIPS TLBINV, TLBINVF
>
> Signed-off-by: Yongbok Kim
> ---
> target-mips/translate.c |8
> 1 files changed, 8 insertions(+), 0 deletions(-)
Reviewed-by: Leon Alrae
On 12/06/2015 15:02, Yongbok Kim wrote:
> rt, rs were swapped
>
> Signed-off-by: Yongbok Kim
> ---
> target-mips/translate.c |4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Leon Alrae
On 12/06/2015 15:02, Yongbok Kim wrote:
> The function will be also used for microMIPS Release 6.
>
> Signed-off-by: Yongbok Kim
> ---
> target-mips/translate.c | 472 +++---
> 1 files changed, 236 insertions(+), 236 deletions(-)
Reviewed-by: Leon Alrae
On 12/06/2015 15:02, Yongbok Kim wrote:
> add new microMIPS32 Release 6 Major opcode instructions
>
> Signed-off-by: Yongbok Kim
> ---
> target-mips/translate.c | 58 --
> 1 files changed, 55 insertions(+), 3 deletions(-)
>
> diff --git a/target-mip
On 12/06/2015 15:02, Yongbok Kim wrote:
> add new microMIPS32 Release 6 POOL32I/POOL32C type instructions
>
> Signed-off-by: Yongbok Kim
> ---
> target-mips/translate.c | 36
> 1 files changed, 32 insertions(+), 4 deletions(-)
>
> diff --git a/target-mips/
On 16/06/2015 15:03, Peter Maydell wrote:
> On 16 June 2015 at 13:32, Liviu Ionescu wrote:
>> would it be possible to have all the semihosting patches ready for 2.4?
>
> Yes, I agree that would be good. Is it just this 2 patch
> series, or are there others too?
Just to confirm -- the only thing
On 12/06/2015 15:02, Yongbok Kim wrote:
> +case R6_LWXS:
> +check_insn(ctx, ISA_MIPS32R6);
> +gen_ldxs(ctx, rs, rt, rd);
> +break;
According to the manual LWXS is removed, not recoded.
Otherwise,
Reviewed-by: Leon Alrae
Include linux/vfio.h after sys/ioctl.h, just like in hw/vfio/common.c.
Signed-off-by: Leon Alrae
---
CentOS 5 is one of hosts I still use. For building I already provide custom
GLib to satisfy version 2.22 dependency. However, with commit 0ea2730b QEMU
doesn't build on CentOS 5.7:
CC
> 9 & 0x3) {
Could you please add parentheses for consistency? (also in other patches in
this series)
Otherwise,
Reviewed-by: Leon Alrae
do (i.e. argv[1] contains the whole
-append), but is more intuitive from UHI user's point of view and Linux
kernel just does not care as it concatenates argv[1..n] into single cmdline
string anyway.
Signed-off-by: Leon Alrae
---
include/exec/semihost.h | 18 ++
qemu-opt
interaction between arg and -kernel/-append
v3:
* improved documentation (rephrased and used @table so that generated
doc looks nicer)
v2:
* squash clean-up related patches so renaming is not required (these
modifications are relatively simple anyway).
Leon Alrae (2):
semihosting: create
stuff from target specific semihosting
code.
Signed-off-by: Leon Alrae
Reviewed-by: Peter Maydell
---
gdbstub.c | 8
include/exec/gdbstub.h| 6 --
include/exec/semihost.h | 44
include/sysemu/sysemu.h | 1
From: "Maciej W. Rozycki"
Correct addresses passed around in semihosting to use a data type suitable
for both 32-bit and 64-bit targets.
Signed-off-by: Maciej W. Rozycki
Signed-off-by: Leon Alrae
---
include/exec/softmmu-semi.h | 13 +++--
1 file changed, 7 insertions(+), 6
s
and will unwind and forward UHI SYSCALL exceptions to the exception
vector that was installed prior to running the application.
Signed-off-by: Matthew Fortune
Signed-off-by: Leon Alrae
---
hw/mips/mips_malta.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/mips/mips_ma
x overlooked microMIPS SDBBP
* translate errno values which don't map 1:1
* update dates in the licence header
* return -1 and fake errno when lock_user() fails in write_to_file() and
read_from_file()
Leon Alrae (3):
target-mips: remove identical code in different branch
target-mips: a
if semihosting arguments are passed to indicate that the UHI
operations should be used to obtain input arguments.
Signed-off-by: Leon Alrae
---
hw/mips/mips_malta.c | 9 +-
qemu-options.hx | 10 +-
target-mips/Makefile.objs | 2 +-
target-mips/helper.h | 2 +
target-mips/mips
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 25 -
1 file changed, 4 insertions(+), 21 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 1d128ee..6fd6dd9 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
Convert only errno values which can be returned by system calls in
mips-semi.c and are not generic to all archs.
Signed-off-by: Leon Alrae
---
target-mips/mips-semi.c | 44 +---
1 file changed, 33 insertions(+), 11 deletions(-)
diff --git a/target-mips
On 19/06/2015 17:25, Yongbok Kim wrote:
> remove an unused argument from decode_micromips32_opc()
>
> Signed-off-by: Yongbok Kim
> ---
> target-mips/translate.c |5 ++---
> 1 files changed, 2 insertions(+), 3 deletions(-)
Reviewed-by: Leon Alrae
-
> 1 files changed, 99 insertions(+), 67 deletions(-)
Reviewed-by: Leon Alrae
s changed, 68 insertions(+), 0 deletions(-)
Reviewed-by: Leon Alrae
ed-off-by: Yongbok Kim
> ---
> target-mips/translate.c | 77
> +++
> 1 files changed, 44 insertions(+), 33 deletions(-)
Reviewed-by: Leon Alrae
On 19/06/2015 17:25, Yongbok Kim wrote:
> @@ -14958,8 +14966,28 @@ static void decode_micromips32_opc(CPUMIPSState
> *env, DisasContext *ctx)
> do_cop1:
> gen_cop1_ldst(ctx, mips32_op, rt, rs, imm);
> break;
> -case ADDIUPC:
> -{
> +case ADDIUPC: /* PCREL: AD
tions(-)
Reviewed-by: Leon Alrae
On 19/06/2015 17:25, Yongbok Kim wrote:
> microMIPS32 Release 6 POOL16A/ POOL16C instructions
>
> Signed-off-by: Yongbok Kim
> ---
> target-mips/translate.c | 107
> ++-
> 1 files changed, 105 insertions(+), 2 deletions(-)
Looks correct, just minor
On 19/06/2015 17:25, Yongbok Kim wrote:
> add new microMIPS32 Release 6 POOL32I/POOL32C type instructions
>
> Signed-off-by: Yongbok Kim
> ---
> target-mips/translate.c | 31 +--
> 1 files changed, 25 insertions(+), 6 deletions(-)
>
> diff --git a/target-mips/trans
On 23/06/2015 16:38, Yongbok Kim wrote:
> add new microMIPS32 Release 6 POOL32I/POOL32C type instructions
>
> Signed-off-by: Yongbok Kim
> ---
> target-mips/translate.c | 27 +--
> 1 files changed, 21 insertions(+), 6 deletions(-)
Reviewed-by: Leon Alrae
On 23/06/2015 16:38, Yongbok Kim wrote:
> microMIPS32 Release 6 POOL16A/ POOL16C instructions
>
> Signed-off-by: Yongbok Kim
> ---
> target-mips/translate.c | 122
> +--
> 1 files changed, 107 insertions(+), 15 deletions(-)
Reviewed-by: Leon Alrae
Add mips-softmmu-common.mak and include it in existing mips*-softmmu.mak
files to avoid having to repeat CONFIG defines four times.
Suggested-by: Peter Maydell
Signed-off-by: Leon Alrae
---
default-configs/mips-softmmu-common.mak | 32
default-configs/mips
Add mips-softmmu-common.mak and include it in existing mips*-softmmu.mak
files to avoid having to repeat CONFIG defines four times.
Suggested-by: Peter Maydell
Signed-off-by: Leon Alrae
---
v2:
* fixed comment line in mips-softmmu-common.mak which I had forgotten
to update
---
default
* fixed format specifiers in qemu_log_mask (use PRIx64 instead of %lx)
* create a container for CPS components as it was suggested in the GIC patch
series (Peter)
Leon Alrae (9):
hw/mips: implement generic MIPS Coherent Processing System container
hw/mips/cps: create GCR block inside CPS
Implement generic MIPS Coherent Processing System (CPS) which in this
commit just creates VPs, but it will serve as a container also for
other components like Global Configuration Registers and Cluster Power
Controller.
Signed-off-by: Leon Alrae
---
default-configs/mips-softmmu-common.mak | 1
Signed-off-by: Leon Alrae
---
hw/mips/cps.c | 23 +++
include/hw/mips/cps.h | 2 ++
2 files changed, 25 insertions(+)
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index 782aa2b..cfd808d 100644
--- a/hw/mips/cps.c
+++ b/hw/mips/cps.c
@@ -61,6 +61,8 @@ static void
CMGCR enabling to a separate patch]
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 3 ++-
target-mips/translate.c | 18 ++
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 4f3ebb9..55d3224 100644
--- a/target-mips
Remove CPUMIPSState from the write_bootloader() argument list as it
is not used in the function.
Signed-off-by: Leon Alrae
---
hw/mips/mips_malta.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index f5173c4..cbfdb78
use
the same pin numbers as before.
Signed-off-by: Leon Alrae
---
hw/mips/mips_malta.c| 60 -
target-mips/cpu.h | 1 +
target-mips/translate.c | 10 +
3 files changed, 60 insertions(+), 11 deletions(-)
diff --git a/hw/mips/mips_m
via CPC memory-mapped registers.
Signed-off-by: Leon Alrae
---
hw/mips/cps.c| 16 +
hw/misc/mips_cmgcr.c | 53
include/hw/mips/cps.h| 2 ++
include/hw/misc/mips_cmgcr.h | 10 +
4 files changed, 81
} to mips_cmgcr.{c,h},
* replaced CONFIG_MIPS_GIC with CONFIG_MIPS_CPS]
Signed-off-by: Leon Alrae
---
hw/misc/Makefile.objs| 1 +
hw/misc/mips_cmgcr.c | 106 +++
include/hw/misc/mips_cmgcr.h | 49
3 files changed, 156
Global smp_cpus is never zero (even if user provides -smp 0), thus clocks
and irqs are always initialized for each created CPU in the loop at the
beginning of mips_malta_init.
These two lines cause a leak of already allocated timer and irqs for the
first CPU - remove them.
Signed-off-by: Leon
Signed-off-by: Leon Alrae
---
hw/mips/mips_malta.c | 68 ++--
1 file changed, 39 insertions(+), 29 deletions(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index b70948d..9e8b9ce 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips
Indicate that in the MIPS64R6-generic CPU the memory-mapped
Global Configuration Register Space is implemented.
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target-mips/translate_init.c b/target-mips
on a single core:
* VP Run is a write-only register used to set each VP to the run state
* VP Stop is a write-only register used to set each VP to the suspend state
* VP Running is a read-only register indicating the run state of each VP
Signed-off-by: Leon Alrae
---
hw/misc/Makefile.objs
Hi,
I cherry-picked this patch and the other one implementing
CP0.Config3.CMGCRBase into my series for the Cluster Power Control needs:
https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg03296.html
I think all issues pointed out during the review for these two patches
have been addressed
09:14:00 +0100)
MIPS patches 2016-03-29
Changes:
* add initial MIPS CPS support
* implement ITU block
* implement MAAR
----
Leon Alrae (17):
hw/mips: implement generic MIPS Coherent Processing System container
hw/mips/cps: c
Implement generic MIPS Coherent Processing System (CPS) which in this
commit just creates VPs, but it will serve as a container also for
other components like Global Configuration Registers and Cluster Power
Controller.
Signed-off-by: Leon Alrae
---
default-configs/mips-softmmu-common.mak | 1
use
the same pin numbers as before.
Signed-off-by: Leon Alrae
---
hw/mips/mips_malta.c| 60 -
target-mips/cpu.h | 1 +
target-mips/translate.c | 10 +
3 files changed, 60 insertions(+), 11 deletions(-)
diff --git a/hw/mips/mips_m
Signed-off-by: Leon Alrae
---
hw/mips/cps.c | 23 +++
include/hw/mips/cps.h | 2 ++
2 files changed, 25 insertions(+)
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index a74df46..e77b1da 100644
--- a/hw/mips/cps.c
+++ b/hw/mips/cps.c
@@ -62,6 +62,8 @@ static void
CMGCR enabling to a separate patch]
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 3 ++-
target-mips/translate.c | 18 ++
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 4f3ebb9..55d3224 100644
--- a/target-mips
Remove CPUMIPSState from the write_bootloader() argument list as it
is not used in the function.
Signed-off-by: Leon Alrae
---
hw/mips/mips_malta.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 4ff1bb2..609f6dc
Control view is used to access the ITC Storage Cell Tags. It never causes
the issuing thread to block.
Guest can empty the FIFO cell by setting Empty bit to 1.
Signed-off-by: Leon Alrae
---
hw/misc/mips_itu.c | 104 +
1 file changed, 104
tions) not implemented.
Store Conditional support for E/F Try View (i.e. indicate failure if FIFO
is full) not implemented.
Signed-off-by: Leon Alrae
---
hw/misc/mips_itu.c | 113 +
1 file changed, 113 insertions(+)
diff --git a/hw/misc/mips_itu.c
on a single core:
* VP Run is a write-only register used to set each VP to the run state
* VP Stop is a write-only register used to set each VP to the suspend state
* VP Running is a read-only register indicating the run state of each VP
Signed-off-by: Leon Alrae
---
hw/misc/Makefile.objs
is 0. P/V Try View does not block the thread, it returns 0 in this case.
Cell's Empty and Full bits are not modified.
Trap bit (i.e. Gating Storage exceptions) not implemented.
Signed-off-by: Leon Alrae
---
hw/misc/mips_itu.c | 68 ++
1
the CACHE
instruction as NOP. But since CACHE can operate on ITC Tags new
MIPS_HFLAG_ITC_CACHE hflag is introduced to generate the helper only when
CACHE is in the ITC Access mode.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 7 +-
target-mips/helper.h| 3 +++
target-mips
} to mips_cmgcr.{c,h},
* replaced CONFIG_MIPS_GIC with CONFIG_MIPS_CPS]
Signed-off-by: Leon Alrae
---
hw/misc/Makefile.objs| 1 +
hw/misc/mips_cmgcr.c | 107 +++
include/hw/misc/mips_cmgcr.h | 49
3 files changed, 157
Global smp_cpus is never zero (even if user provides -smp 0), thus clocks
and irqs are always initialized for each created CPU in the loop at the
beginning of mips_malta_init.
These two lines cause a leak of already allocated timer and irqs for the
first CPU - remove them.
Signed-off-by: Leon
Make ITU available in the system if CPU supports multithreading
and is part of CPS.
Signed-off-by: Leon Alrae
---
hw/mips/cps.c | 32
include/hw/mips/cps.h | 2 ++
2 files changed, 34 insertions(+)
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index
Bypass View does not cause issuing thread to block and does not affect
any of the cells state bit.
Read from a FIFO cell returns the value of the oldest entry.
Store to a FIFO cell changes the value of the newest entry.
Signed-off-by: Leon Alrae
---
hw/misc/mips_itu.c | 27
via CPC memory-mapped registers.
Signed-off-by: Leon Alrae
---
hw/mips/cps.c| 16 +
hw/misc/mips_cmgcr.c | 53
include/hw/mips/cps.h| 2 ++
include/hw/misc/mips_cmgcr.h | 10 +
4 files changed, 81
Signed-off-by: Leon Alrae
---
hw/mips/mips_malta.c | 68 ++--
1 file changed, 39 insertions(+), 29 deletions(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 60e8a8d..cc32a44 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index a5b8805..65f2caf 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -17194,6 +17194,7 @@ static void
Storage contains
both types of cells then FIFOs are located before Semaphores.
Since issuing thread can get blocked on the access to a cell (in E/F
Synchronized and P/V Synchronized Views) each cell has a bitmap to track
which threads are currently blocked.
Signed-off-by: Leon Alrae
---
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