On 06/12/15 16:11, Aurelien Jarno wrote:
> cvt.s.d and cvt.d.s are FP operations and thus need to convert input
> sNaN into corresponding qNaN. Explicitely use the floatXX_maybe_silence_nan
> functions for that as the floatXX_to_floatXX functions do not do that.
>
> Cc: Leon Alra
On 18/02/16 11:51, Peter Maydell wrote:
> On 2 February 2016 at 10:49, Leon Alrae wrote:
>> On 25/01/16 17:40, Peter Maydell wrote:
>>> The r4k_tlb_t structure uses the uint_fast*_t types. Most of these
>>> uses are in bitfields and are thus pointless, because the bi
On 22/02/16 06:56, Igor R wrote:
> Here is an excerpt from r4k_map_address(), related to addresses >= 0x8000.
> Actually, it maps 0x8010 and 0xA010 to the same physical
> address. What's the idea behind that?
0x8010 is kseg0 whereas 0xA010 is kseg1, both segments are
unmapped t
ound. Try passing init= option
to kernel. See Linux Documentation/init.txt for guidance.
Therefore always indicate presence of 2008-NaN support in R6 as well as in
R5+MSA CPUs, even though this feature is not yet supported by MIPS in QEMU.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h
On 25/02/16 18:56, Igor R wrote:
> If I understand correctly, the most advanced MMU that QEMU emulates
> for MIPS is "R4000-style" MMU - i.e. a "software-managed" TLB, where
> on TLB miss QEMU just emulates exception that should be handled by the
> guest OS. So, QEMU doesn't walk through the page d
Hi,
MIPS pull request containing support for FPU and MSA in KVM and R6 VPs.
Thanks,
Leon
Cc: Peter Maydell
Cc: Aurelien Jarno
The following changes since commit 0c6940d086f39bbf725d96104abe46da87429cb6:
build: [bsd-user] Rename "syscall.h" to "target_syscall.h" in target
directories (2016
ation (Config1.FP) and so that QEMU can
save/restore the guest modifiable bits (Config5.FRE, Config5.UFR,
Config5.UFE). The FCSR/FIR registers and the floating point registers
are now saved/restored (depending on the FR mode bit).
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aur
so as not
to clobber them on migration/savevm.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien Jarno
Signed-off-by: Leon Alrae
---
target-mips/kvm.c | 106 ++
1 file changed, 106 insertions(+)
diff --git a/target
Alrae
Cc: Paolo Bonzini
Cc: Aurelien Jarno
Signed-off-by: Leon Alrae
---
target-mips/kvm.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target-mips/kvm.c b/target-mips/kvm.c
index a8b8b32..8bd7438 100644
--- a/target-mips/kvm.c
+++ b/target-mips/kvm.c
@@ -88,7 +88,6 @@ static inline int
From: James Hogan
Implement saving and restoring to KVM state of the Processor ID (PRid)
CP0 register. This allows QEMU to control the PRid exposed to the guest
instead of using the default set by KVM.
Signed-off-by: James Hogan
Reviewed-by: Leon Alrae
Cc: Paolo Bonzini
Cc: Aurelien Jarno
/EVP instructions.
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
disas/mips.c | 4 +++
target-mips/cpu.c| 9 +++
target-mips/cpu.h| 25 +++
target-mips/helper.h | 4 +++
target-mips/op_helper.c | 48
: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien Jarno
Signed-off-by: Leon Alrae
---
target-mips/kvm.c | 129 +-
1 file changed, 109 insertions(+), 20 deletions(-)
diff --git a/target-mips/kvm.c b/target-mips/kvm.c
index a1f5b60
From: James Hogan
Add KVM register access functions for the uint32_t type. This is
required for FP and MSA control registers, which are represented as
unsigned 32-bit integers.
Signed-off-by: James Hogan
Cc: Paolo Bonzini
Cc: Leon Alrae
Cc: Aurelien Jarno
Signed-off-by: Leon Alrae
Alrae
Cc: Aurelien Jarno
Signed-off-by: Leon Alrae
---
target-mips/kvm.c | 40 +++-
1 file changed, 31 insertions(+), 9 deletions(-)
diff --git a/target-mips/kvm.c b/target-mips/kvm.c
index abdd6b6..a297b5a 100644
--- a/target-mips/kvm.c
+++ b/target-mips/kvm.c
near future.
Thanks,
Leon
Leon Alrae (2):
hw/mips: add initial Cluster Power Controller support
hw/mips_malta: add CPC to the Malta board
default-configs/mips-softmmu.mak | 1 +
default-configs/mips64-softmmu.mak | 1 +
default-configs/mips64el-softmmu.mak | 1 +
default-configs/m
On Malta, after reset, only VP0 on Core0 starts the execution. Other VPs
are halted until VP0 powers them up using Cluster Power Controller.
Signed-off-by: Leon Alrae
---
hw/mips/mips_malta.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/hw/mips
on a single core:
* VP Run is a write-only register used to set each VP to the run state
* VP Stop is a write-only register used to set each VP to the suspend state
* VP Running is a read-only register indicating the run state of each VP
Signed-off-by: Leon Alrae
---
default-configs/mips
On 26/02/16 16:49, Peter Maydell wrote:
> On 26 February 2016 at 16:19, Leon Alrae wrote:
>> Cluster Power Controller (CPC) is responsible for power management in
>> multiprocessing system. It provides registers to control the power and the
>> clock frequency of the indiv
On 24/06/2015 12:04, Aurelien Jarno wrote:
>> +static void gen_align(DisasContext *ctx, int opc, int rd, int rs, int rt,
>> + int bp)
>> {
>> +TCGv t0;
>> +if (rd == 0) {
>> +/* Treat as NOP. */
>> +return;
>> +}
>> +t0 = tcg_temp_new();
>> +
On 24/06/2015 15:37, Aurelien Jarno wrote:
> On 2015-06-19 11:08, Leon Alrae wrote:
>> Signed-off-by: Leon Alrae
>> ---
>> target-mips/translate.c | 25 -
>> 1 file changed, 4 insertions(+), 21 deletions(-)
>>
>> diff --git
From: Yongbok Kim
Add microMIPS TLBINV, TLBINVF
Signed-off-by: Yongbok Kim
Reviewed-by: Aurelien Jarno
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 8
1 file changed, 8 insertions(+)
diff --git a/target-mips/translate.c b/target-mips/translate.c
s
and will unwind and forward UHI SYSCALL exceptions to the exception
vector that was installed prior to running the application.
Signed-off-by: Matthew Fortune
Signed-off-by: Leon Alrae
---
hw/mips/mips_malta.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/mips/mips_ma
Convert only errno values which can be returned by system calls in
mips-semi.c and are not generic to all archs.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
target-mips/mips-semi.c | 44 +---
1 file changed, 33 insertions(+), 11 deletions
From: Yongbok Kim
rt, rs were swapped
Signed-off-by: Yongbok Kim
Reviewed-by: Aurelien Jarno
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-mips/translate.c b/target-mips
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
target-mips/translate.c | 25 -
1 file changed, 4 insertions(+), 21 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index a2dbad5..7d9f2da 100644
--- a/target-mips/translate.c
+++ b
From: Yongbok Kim
The function will be also used for microMIPS Release 6.
Signed-off-by: Yongbok Kim
Reviewed-by: Leon Alrae
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 472
1 file changed, 236
From: "Maciej W. Rozycki"
Correct addresses passed around in semihosting to use a data type suitable
for both 32-bit and 64-bit targets.
Signed-off-by: Maciej W. Rozycki
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
include/exec/softmmu-semi.h | 13 +++--
1 fi
From: Yongbok Kim
Refactor those instructions in order to reuse them for microMIPS32
Release 6.
Rearrange gen_move_low32().
Signed-off-by: Yongbok Kim
Reviewed-by: Leon Alrae
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 166
2:26 +0100)
MIPS patches 2015-06-26
Changes:
* MIPS UHI semihosting support
* microMIPS32 R6 support
----
Leon Alrae (3):
target-mips: remove identical code in different branch
target
if semihosting arguments are passed to indicate that the UHI
operations should be used to obtain input arguments.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
hw/mips/mips_malta.c | 9 +-
qemu-options.hx | 10 +-
target-mips/Makefile.objs | 2 +-
target-mips/help
From: Yongbok Kim
Add new microMIPS32 Release 6 POOL32F instructions
Signed-off-by: Yongbok Kim
Reviewed-by: Leon Alrae
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 231 +---
1 file changed, 199 insertions
ld in
FCSR0(FIR) but do support PS data format, therefore for these cores RI will
not be signalled regardless of PS bit.
Signed-off-by: Yongbok Kim
Reviewed-by: Leon Alrae
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
target-mips/translate.c
From: Yongbok Kim
Remove an unused argument from decode_micromips32_opc()
Signed-off-by: Yongbok Kim
Reviewed-by: Leon Alrae
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target
From: Yongbok Kim
Add new microMIPS32 Release 6 Major opcode instructions
Signed-off-by: Yongbok Kim
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 62 +++--
1 file changed, 45 insertions(+), 17 deletions
From: Yongbok Kim
Add new microMIPS32 Release 6 POOL32I/POOL32C type instructions
Signed-off-by: Yongbok Kim
Reviewed-by: Leon Alrae
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 27 +--
1 file changed, 21 insertions(+), 6
From: Yongbok Kim
Add new microMIPS32 Release 6 branch and jump instructions.
Signed-off-by: Yongbok Kim
Reviewed-by: Leon Alrae
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 242
1 file changed, 202
From: Yongbok Kim
Define a new CPU definition supporting MIPS32 Release 6 ISA and
microMIPS32 Release 6 ISA.
Signed-off-by: Yongbok Kim
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 37 +
1 file changed, 37
From: Yongbok Kim
Add new microMIPS32 Release 6 pool32a/pool32axf instructions.
Signed-off-by: Yongbok Kim
Reviewed-by: Leon Alrae
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 82 +++--
1 file changed, 72
From: Yongbok Kim
Add microMIPS32 Release 6 opcode enum.
Remove RI checking for pre-R6 reserved opcode.
Signed-off-by: Yongbok Kim
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 119 +---
1 file changed, 103
From: Yongbok Kim
Signal a Reserved Instruction exception for removed instruction encoding
in microMIPS Release 6.
Signed-off-by: Yongbok Kim
Reviewed-by: Leon Alrae
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 68
From: Yongbok Kim
microMIPS32 Release 6 POOL16A/ POOL16C instructions
Signed-off-by: Yongbok Kim
Reviewed-by: Leon Alrae
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 133 ++--
1 file changed, 118 insertions
On 29/06/2015 10:11, Yongbok Kim wrote:
> Fix core configuration for MIPS64R6-generic to make it as close as
> I6400.
> I6400 core has 48-bit of Virtual Address available (SEGBITS).
> MIPS SIMD Architecture is available.
> Rearrange order of bits to match the specification.
>
> Signed-off-by: Yong
Andrew Bennett
> ---
> linux-user/main.c |4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Leon Alrae
Thanks,
Leon
Hi Serge,
On 30/06/2015 06:02, Serge Vakulenko wrote:
> Signed-off-by: Serge Vakulenko
> ---
> target-mips/op_helper.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
> index 2a9ddff..1b7caeb 100644
> --- a/target-mips/op_helper.
later
be overwritten by the (big endian) BIOS image. Correct this by operating
on the data referenced by struct Rom rather than the target memory when
the -bios argument is used.
Signed-off-by: Paul Burton
Signed-off-by: Leon Alrae
---
hw/mips/mips_malta.c |7 +--
1 files changed, 5 inserti
From: Paul Burton
This patchset fixes some bugs with MIPS malta emulation allowing the YAMON
firmware to run.
YAMON can be found at http://www.mips.com/products/system-software/yamon/
You can then boot to a YAMON prompt by passing the path to yamon-XX.bin to
the -bios argument or by writing yam
the hardware reads 0x00SS00SS. The YAMON firmware compares the
status against 32bit values expecting the mirrored value and fails
without it.
Signed-off-by: Paul Burton
Signed-off-by: Leon Alrae
---
hw/block/pflash_cfi01.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git
bug preventing them from handling a single bank of SDRAM with
the Galileo GT64120 system controller emulated by QEMU.
Signed-off-by: Paul Burton
Signed-off-by: Leon Alrae
---
hw/mips/mips_malta.c | 60 +++--
1 files changed, 57 insertions(+), 3
ated on target memory which would
later be overwritten by the BIOS image upon CPU reset if the -bios
argument was used to specify the BIOS image. This led to the written
MIPS revision being lost. Copying using rom_copy when -bios is used
fixes this issue.
Signed-off-by: Paul Burton
Signed-off-by:
From: Paul Burton
This preserves the final sector of the pflash which is used by YAMON to
hold environment variables. If the endianness of the environment data
is swapped then YAMON will fail to load environment variables from
pflash.
Signed-off-by: Paul Burton
Signed-off-by: Leon Alrae
serial number for the board and prevent it from warning that the EEPROM
data is invalid.
We already have the contents of the SPD EEPROM which are exposed via
FPGA I2C accesses, this is provided as part of the SMBUS EEPROM data
too for consistency.
Signed-off-by: Paul Burton
Signed-off-by: Leon
ping
http://patchwork.ozlabs.org/patch/255005/
On 27/06/13 08:35, Leon Alrae wrote:
> From: James Hogan
>
> The Linux kernel can be configured to use 64KB pages, but it also
> requires initrd to be page aligned. Therefore, to be safe, align the
> initrd to 64KB using a new I
ping
On 28/06/13 14:20, Leon Alrae wrote:
> ping
>
> http://patchwork.ozlabs.org/patch/251250/
> http://patchwork.ozlabs.org/patch/251254/
> http://patchwork.ozlabs.org/patch/251253/
> http://patchwork.ozlabs.org/patch/251251/
> http://patchwork.ozlabs.org
ping
On 10/07/13 16:01, Leon Alrae wrote:
> ping
>
> http://patchwork.ozlabs.org/patch/255005/
>
> On 27/06/13 08:35, Leon Alrae wrote:
>> From: James Hogan
>>
>> The Linux kernel can be configured to use 64KB pages, but it also
>> requires initrd to
From: James Hogan
The Linux kernel can be configured to use 64KB pages, but it also
requires initrd to be page aligned. Therefore, to be safe, align the
initrd to 64KB using a new INITRD_PAGE_MASK rather than
TARGET_PAGE_MASK.
Signed-off-by: James Hogan
Signed-off-by: Leon Alrae
---
hw/mips
ping
http://patchwork.ozlabs.org/patch/251250/
http://patchwork.ozlabs.org/patch/251254/
http://patchwork.ozlabs.org/patch/251253/
http://patchwork.ozlabs.org/patch/251251/
http://patchwork.ozlabs.org/patch/251252/
http://patchwork.ozlabs.org/patch/251249/
On 14/06/13 08:30, Leon Alrae wrote
On 05/10/15 13:48, Yongbok Kim wrote:
> Add more register numbers for RDHWR
Could the commit message say which registers exactly this patch is adding?
> Add check_hwrena() to simplify access control checkings.
> Add RDHWR support to microMIPS R6
>
> Signed-off-by: Yongbok Kim
> ---
> @@ -1357,
On 05/10/15 14:45, Yongbok Kim wrote:
> Set Config5.XNP for R6 cores to indicate the extended LL/SC family
> of instructions NOT present.
>
> Signed-off-by: Yongbok Kim
> ---
> target-mips/translate_init.c |4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Leon Alrae
t didn't update the PC initialisation for KVM to use
> ram_low_size. Fix that now.
>
> Fixes: 71c199c81d29 ("mips_malta: provide ememsize env variable to kernels")
> Signed-off-by: James Hogan
> Cc: Paul Burton
> Cc: Leon Alrae
> Cc: Aurelien Jarno
> ---
>
On 16/10/15 00:52, Yongbok Kim wrote:
> Physical base address for the memory-mapped Coherency Manager Global
> Configuration Register space.
> The MIPS default location for the GCR_BASE address is 0x1FBF_8.
> This register only exists if Config3 CMGCR is set to one.
>
> Signed-off-by: Yongbok Kim
On 11/10/15 21:30, Aurelien Jarno wrote:
> (sorry for the late answer)
>
> On 2015-08-26 14:12, Petar Jovanovic wrote:
>> From: Petar Jovanovic
>>
>> Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither
>> they require any particular mode for its FPU. This patch removes the
Oops my email client dropped Aurelien's email from CC for some reason...
(adding back)
On 19/10/15 17:40, Leon Alrae wrote:
> On 11/10/15 21:30, Aurelien Jarno wrote:
>> (sorry for the late answer)
>>
>> On 2015-08-26 14:12, Petar Jovanovic wrote:
>>> From: Pe
On 16/10/15 00:52, Yongbok Kim wrote:
> The Global Interrupt Controller (GIC) is responsible for mapping each
> internal and external interrupt to the correct location for servicing.
>
> Limitations:
> Level triggering only
> No User-Mode Visible Section
> GIC CounterHi not implemented (Countbits
On 16/10/15 00:52, Yongbok Kim wrote:
> /*
> * We have a circular dependency problem: pci_bus depends on isa_irq,
> * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
> @@ -1155,7 +1218,11 @@ void mips_malta_init(MachineState *machine)
>
> /* Interrupt control
On 10/07/2015 12:10, Yongbok Kim wrote:
> Correct computation of vector offsets for EXCP_EXT_INTERRUPT.
> For instance, if Cause.IV is 0 the vector offset should be 0x180.
>
> Simplify the finding vector number logic for the Vectored Interrupts.
I think this message would be much better if it was
Signed-off-by: Leon Alrae
---
hw/net/dp8393x.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
index 93d6a47..0f45146 100644
--- a/hw/net/dp8393x.c
+++ b/hw/net/dp8393x.c
@@ -643,11 +643,6 @@ static int dp8393x_receive_filter(dp8393xState *s, const
uint8_t
-by: Leon Alrae
---
hw/net/dp8393x.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
index 0f45146..ab607e4 100644
--- a/hw/net/dp8393x.c
+++ b/hw/net/dp8393x.c
@@ -831,6 +831,7 @@ static void dp8393x_realize(DeviceState *dev
Reported-by: Peter Maydell
Signed-off-by: Leon Alrae
---
target-mips/machine.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target-mips/machine.c b/target-mips/machine.c
index 8fa755c..b15c43a 100644
--- a/target-mips/machine.c
+++ b/target-mips/machine.c
@@ -153,6
ning on FreeBSD
Hervé Poussineau (3):
net/dp8393x: disable user creation
net/dp8393x: remove check of runt packets
net/dp8393x: do not use memory_region_init_rom_device with NULL
Leon Alrae (1):
target-mips: fix passing incompatible pointer type in mac
From: Hervé Poussineau
Netcard needs an address space to write data to, which can't be specified
on command line.
This fixes a crash when user starts QEMU with "-device dp8393x"
Signed-off-by: Hervé Poussineau
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
hw/ne
From: Yongbok Kim
Correct computation of vector offsets for EXCP_EXT_INTERRUPT.
For instance, if Cause.IV is 0 the vector offset should be 0x180.
Simplify the finding vector number logic for the Vectored Interrupts.
Signed-off-by: Yongbok Kim
Reviewed-by: Leon Alrae
[leon.al...@imgtec.com
In semihosting mode the SDBBP 1 instructions should trigger UHI syscall,
but in QEMU this does not happen for recently added microMIPS R6.
Consequently bare metal microMIPS R6 programs supporting UHI will not run.
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 10 +++---
1 file
On 03/08/2015 23:09, Aurelien Jarno wrote:
>>> Should we try to get this one into 2.4, if not already too late?
>>
>> Perhaps. Otherwise via stable after the fact.
>
> Ok. Leon, do you have other pending patches for 2.4/2.4.1? The
> semihosting microMIPS R6 one maybe?
Yes, it would be good also
a, not code, as
> translation failed to stop after a break insn.
>
> Signed-off-by: Richard Henderson
> ---
> target-mips/translate.c | 45 +
> 1 file changed, 25 insertions(+), 20 deletions(-)
Reviewed-by: Leon Alrae
I'll send out
In semihosting mode the SDBBP 1 instructions should trigger UHI syscall,
but in QEMU this does not happen for recently added microMIPS R6.
Consequently bare metal microMIPS R6 programs supporting UHI will not run.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
target-mips
break insn.
Signed-off-by: Richard Henderson
Reviewed-by: Aurelien Jarno
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 45 +
1 file changed, 25 insertions(+), 20 deletions(-)
diff --git a/target-mips/translate.c b
:15
+0100)
MIPS patches 2015-08-04
Changes:
* fix semihosting for microMIPS R6
* fix an abort when booting mips64 kernel with --enable-tcg-debug
----
Leon Alrae (1):
target
On 10/07/2015 10:57, Pavel Dovgalyuk wrote:
> @@ -2364,14 +2363,12 @@ static void gen_st_cond (DisasContext *ctx, uint32_t
> opc, int rt,
> #if defined(TARGET_MIPS64)
> case OPC_SCD:
> case R6_OPC_SCD:
> -save_cpu_state(ctx, 1);
> op_st_scd(t1, t0, rt, ctx);
>
Hi,
First target-mips pull request for 2.5 consisting of patches sent during
2.4 freeze.
Thanks,
Leon
Cc: Peter Maydell
Cc: Aurelien Jarno
The following changes since commit ca0e5d8b0d065a95d0f9042f71b2ace45b015596:
Open 2.5 development tree (2015-08-11 23:15:55 +0100)
are available in th
: Yongbok Kim
[leon.al...@imgtec.com: correct cache line sizes and LLAddr shift]
Signed-off-by: Leon Alrae
---
target-mips/cpu.h| 2 +-
target-mips/translate_init.c | 53
2 files changed, 30 insertions(+), 25 deletions(-)
diff --git a/target
a and boncop structs and into whatever lies beyond.
Signed-off-by: Peter Maydell
Acked-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
hw/pci-host/bonito.c | 16
1 file changed, 16 insertions(+)
diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
index 3a731fe..4139a2c 1
From: Richard Henderson
There are now no unconditional uses of qemu_log in the subdirectory.
Signed-off-by: Richard Henderson
Reviewed-by: Aurelien Jarno
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/helper.c| 30 +++---
target-mips
tion less, and it avoids a 32/64-bit constant
loading which can take a few instructions on RISC hosts.
Cc: Leon Alrae
Signed-off-by: Aurelien Jarno
Reviewed-by: Richard Henderson
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 14 ++
1 file changed, 6
target-mips/helper.h | 10 +++-
> target-mips/op_helper.c | 136 ++---
> target-mips/translate.c | 66 ++++++---
> target-mips/translate_init.c |2 +-
> 6 files changed, 150 insertions(+), 88 deletions(-)
>
Extend EntryLo0, EntryLo1, LLAddr and TagLo from 32 to 64 bits in MIPS32.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 14 +++---
target-mips/machine.c | 20 ++--
target-mips/op_helper.c | 8
target-mips/translate.c | 5 +++--
4 files changed, 24
Since PFNX is now supported the bits 31:30 have to be cleared.
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index c931eda..0ca610c 100644
--- a/target-mips
PABITS are not hardcoded to 36 bits and we do not model 59 PABITS (which is
the architectural limit) in QEMU.
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index
comments in patch #6 (James)
Leon Alrae (7):
target-mips: extend selected CP0 registers to 64-bits in MIPS32
target-mips: support Page Frame Number Extension field
target-mips: add CP0.PageGrain.ELPA support
target-mips: add MTHC0 and MFHC0 instructions
target-mips: correct MFC0 for CP0
Enable XPA in MIPS32R5-generic and LPA in MIPS64R6-generic.
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 05a02eb..836b7bf 100644
Update tlb->PFN to contain PFN concatenated with PFNX. PFNX is 0 if large
physical address is not supported.
Signed-off-by: Leon Alrae
---
target-mips/op_helper.c | 32 ++--
1 file changed, 26 insertions(+), 6 deletions(-)
diff --git a/target-mips/op_helper.
.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 27 +--
target-mips/machine.c | 1 +
target-mips/mips-defs.h | 4 ++--
target-mips/op_helper.c | 19 ---
target-mips/translate.c | 3 ++-
5 files changed, 42 insertions(+), 12 deletions(-)
dif
and XI, which were shifted to bits
63:62 by MTC0 to EntryLo0 or EntryLo1. Therefore creating separate
functions for EntryLo0 and EntryLo1.
Signed-off-by: Leon Alrae
---
disas/mips.c| 2 +
target-mips/cpu.h | 1 +
target-mips/translate.c | 229
On 26/05/2015 17:03, Leon Alrae wrote:
> v4:
> * add semihosting_get_cmdline() and update arm-semi.c to support new option
> * for backward compatibility use -kernel/-append to initialize
> semihosting.argv
> * update qemu doc to describe the interaction between arg and -kernel/-ap
ERETNC is identical to ERET except that an ERETNC will not clear the LLbit
that is set by execution of an LL instruction, and thus when placed between
an LL and SC sequence, will never cause the SC to fail.
Presence of ERETNC is denoted by the Config5.LLB.
Signed-off-by: Leon Alrae
---
disas
On 04/06/15 23:14, Aurelien Jarno wrote:
> If you change the size of these registers, you have to adjust the
> corresponding MFC0 function for MIPS32, as the tcg_gen_ld_tl() function
> will point to the wrong side of the field on big endian hosts.
I'll fix it, thanks for pointing this out.
Leon
On 05/06/15 10:42, Aurelien Jarno wrote:
> On 2015-06-04 17:00, Leon Alrae wrote:
>> ERETNC is identical to ERET except that an ERETNC will not clear the LLbit
>> that is set by execution of an LL instruction, and thus when placed between
>> an LL and SC sequence, will never
On 05/06/15 16:23, Peter Maydell wrote:
> On 26 May 2015 at 17:03, Leon Alrae wrote:
>> --- a/target-arm/arm-semi.c
>> +++ b/target-arm/arm-semi.c
>> @@ -27,6 +27,7 @@
>> #include
>>
>> #include "cpu.h"
>> +#include "exec/
.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 27 +--
target-mips/machine.c | 1 +
target-mips/mips-defs.h | 4 ++--
target-mips/op_helper.c | 19 ---
target-mips/translate.c | 3 ++-
5 files changed, 42 insertions(+), 12 deletions(-)
dif
Extend EntryLo0, EntryLo1, LLAddr and TagLo from 32 to 64 bits in MIPS32.
Introduce gen_move_low32() function which moves low 32 bits from 64-bit
temp to GPR; it sign extends 32-bit value on MIPS64 and truncates on
MIPS32.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 14
CP0.EntryLo bits 31:30 have to be cleared.
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index fe6bc16..668e02d 100644
--- a/target-mips/translate.c
+++ b
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