rce_sig_fault. (I have a pending patch set to convert all
other instances;
hopefully that can be merged soon...)
I'll send v2 with a Based-on
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
Aviso Legal - Disclaimer
and RI */
TCGv t0 = tcg_temp_new();
@@ -5419,9 +5325,7 @@ static void gen_mtmsr(DisasContext *ctx)
CHK_SV;
#if !defined(CONFIG_USER_ONLY)
-if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
-gen_io_start();
-}
+gen_icount_io_start(ctx);
if (ctx->opcode & 0x0001) {
/* L=1 form only updates EE and RI */
TCGv t0 = tcg_temp_new();
Sorry, I somehow changed the author by mistake, which must be
From: Richard Henderson
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software Júnior
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
as 0 - indicating the logical block size
> equals the physical block size.
>
> This is identical to commit 3da023b5827543ee4c022986ea2ad9d1274410b2
> but applied to virtio-blk (instead of virtio-scsi).
Reviewed-by: Martin K. Petersen
--
Martin K. Petersen Oracle Linux Engineering
Hi Eric,
On 10/18/2018 03:30 PM, Eric Auger wrote:
This is a header update against kvmarm next branch
git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm kvmarm/next
to get the KVM_ARM_GET_MAX_VM_PHYS_SHIFT ioctl. This allows to retrieve
the IPA address range KVM supports.
Signed-off-
On 07/04/2018 09:24 AM, Auger Eric wrote:
+ *
+ * We have a magic formula for the Magic_N below.
+ *
+ * Magic_N(PAGE_SIZE, Entry_Level) = 64 - ((PAGE_SHIFT - 3) *
Number of levels)
[0] ^^^
+ *
+ * where number of levels = (4 - Entry_Level).
^^^ Doesn't this help make it clear ? Using th
Hi Will,
On 07/04/2018 03:22 PM, Will Deacon wrote:
On Fri, Jun 29, 2018 at 12:15:44PM +0100, Suzuki K Poulose wrote:
diff --git a/arm/kvm.c b/arm/kvm.c
index 5701d41..b1969be 100644
--- a/arm/kvm.c
+++ b/arm/kvm.c
@@ -11,6 +11,8 @@
#include
#include
+unsigned long kvm_arm_type
On 07/04/2018 04:51 PM, Will Deacon wrote:
Hi Suzuki,
On Fri, Jun 29, 2018 at 12:15:35PM +0100, Suzuki K Poulose wrote:
Allow specifying the physical address size for a new VM via
the kvm_type argument for KVM_CREATE_VM ioctl. This allows
us to finalise the stage2 page table format as early as
29, 2018 at 12:15:42PM +0100, Suzuki K Poulose wrote:
Add an option to specify the physical address size used by this
VM.
Signed-off-by: Suzuki K Poulose
---
arm/aarch64/include/kvm/kvm-config-arch.h | 5 -
arm/include/arm-common/kvm-config-arch.h | 1 +
2 files changed, 5 insertions
On 04/07/18 23:03, Suzuki K Poulose wrote:
On 07/04/2018 04:51 PM, Will Deacon wrote:
Hi Suzuki,
On Fri, Jun 29, 2018 at 12:15:35PM +0100, Suzuki K Poulose wrote:
Allow specifying the physical address size for a new VM via
the kvm_type argument for KVM_CREATE_VM ioctl. This allows
us to
On 07/06/2018 04:09 PM, Marc Zyngier wrote:
On 06/07/18 14:49, Suzuki K Poulose wrote:
On 04/07/18 23:03, Suzuki K Poulose wrote:
On 07/04/2018 04:51 PM, Will Deacon wrote:
Hi Suzuki,
On Fri, Jun 29, 2018 at 12:15:35PM +0100, Suzuki K Poulose wrote:
Allow specifying the physical address
On 09/07/18 14:37, Dave Martin wrote:
On Mon, Jul 09, 2018 at 01:29:42PM +0100, Marc Zyngier wrote:
On 09/07/18 12:23, Dave Martin wrote:
On Fri, Jul 06, 2018 at 05:39:00PM +0100, Suzuki K Poulose wrote:
On 07/06/2018 04:09 PM, Marc Zyngier wrote:
On 06/07/18 14:49, Suzuki K Poulose wrote
On 10/07/18 18:03, Dave Martin wrote:
On Tue, Jul 10, 2018 at 05:38:39PM +0100, Suzuki K Poulose wrote:
On 09/07/18 14:37, Dave Martin wrote:
On Mon, Jul 09, 2018 at 01:29:42PM +0100, Marc Zyngier wrote:
On 09/07/18 12:23, Dave Martin wrote:
[...]
Wedging arguments into a few bits in the
o PFN check patches and address comments.
Kristina Martsenko (1):
vgic: Add support for 52bit guest physical address
Suzuki K Poulose (19):
virtio: mmio-v1: Validate queue PFN
virtio: pci-legacy: Validate queue pfn
arm64: Add a helper for PARange to physical shift conversion
kvm: arm64: Cle
, rather than silently breaking
the devices.
Cc: "Michael S. Tsirkin"
Cc: Jason Wang
Cc: Marc Zyngier
Cc: Christoffer Dall
Cc: Peter Maydel
Cc: Jean-Philippe Brucker
Signed-off-by: Suzuki K Poulose
---
Changes since v2:
- Change errno to -E2BIG
---
drivers/virtio/virtio_m
it
is about to move its place. Having this helper keeps the code
movement cleaner.
Cc: Catalin Marinas
Cc: Marc Zyngier
Cc: James Morse
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
Changes since V2:
- Split the patch
- Limit the physical shift only for values unrecognized
Use the new helper for converting the parange to the physical shift.
Also, add the missing definitions for the VTCR_EL2 register fields
and use them instead of hard coding numbers.
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
Changes since V2
- Part 2 of the split
This patch is a reverse engineered
implementation to calculate the 'x' at runtime for a given ipa and
number of page table levels. See patch for more details.
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
Changes since V2:
- Part 1 of spilt from
On a 4-level page table pgd entry can be empty, unlike a 3-level
page table. Remove the spurious WARN_ON() in stage_get_pud().
Cc: Marc Zyngier
Acked-by: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
virt/kvm/arm/mmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
, rather than silently breaking
the devices.
Cc: "Michael S. Tsirkin"
Cc: Jason Wang
Cc: Marc Zyngier
Cc: Christoffer Dall
Cc: Peter Maydel
Cc: Jean-Philippe Brucker
Signed-off-by: Suzuki K Poulose
---
Changes since v2:
- Change errno to -E2BIG
---
drivers/virtio/virtio_pci_leg
So far we have only supported 3 level page table with fixed IPA of 40bits.
Fix stage2_flush_memslot() to accommodate for 4 level tables.
Cc: Marc Zyngier
Acked-by: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
virt/kvm/arm/mmu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion
do the right thing with the
future changes.
Cc: Christoffer Dall
Cc: Marc Zyngier
Signed-off-by: Suzuki K Poulose
---
Changes since v2:
- New patch
---
arch/arm64/include/asm/kvm_hyp.h | 6 ++
arch/arm64/kvm/hyp/switch.c | 2 +-
arch/arm64/kvm/hyp/tlb.c | 4 ++--
3 files
about
to make it dynamic, we need to calculate the SL0 at runtime
per VM. This patch adds a helper to comput the value of SL0 for
a given IPA.
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
Changes since v2:
- Part 2 of split from VTCR & VTTBR dynamic configura
to the top, before including the asm/stage2_pgtable.h to avoid a forward
declaration.
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
Changes since V2
- Restrict the stage2 page table to allow reusing the host page table
helpers for now, until we get stage1 independ
S2_PGD_SIZE. Also, moves
some of the definitions dependent on kvm instance to asm/kvm_mmu.h
for arm32. In that process drop the _AC() specifier constants
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
Changes since V2:
- Update commit description abuot the movement to asm
the stage2 page table.
Cc: Christoffer Dall
Cc: Marc Zyngier
Cc: Peter Maydel
Signed-off-by: Suzuki K Poulose
---
Changes since V2:
- Bump the ioctl number
---
Documentation/virtual/kvm/api.txt | 15 +++
arch/arm/include/asm/kvm_mmu.h| 5 +
arch/arm64/include/asm
Signed-off-by: Kristina Martsenko
[ Macro clean ups, fix PROPBASER and PENDBASER accesses ]
Signed-off-by: Suzuki K Poulose
---
include/linux/irqchip/arm-gic-v3.h | 5 +
virt/kvm/arm/vgic/vgic-its.c | 36 ++--
virt/kvm/arm/vgic/vgic-mmio-v3.c | 2 --
3
Abstract the allocation of stage2 entry level tables for
given VM, so that later we can choose to fall back to the
normal page table levels (i.e, avoid entry level table
concatenation) on arm64.
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
Changes since V2:
- New
) in the bits[7:0]
of the type field and can encode more information in the future if
required. The IPA size is still capped at 40bits.
Cc: Marc Zyngier
Cc: Christoffer Dall
Cc: Peter Maydel
Cc: Paolo Bonzini
Cc: Radim Krčmář
Signed-off-by: Suzuki K Poulose
---
arch/arm/include/asm/kvm_mmu.h
aults in stage1.
Cc: Marc Zyngier
Cc: Kristina Martsenko
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/kvm_arm.h | 7 +++
arch/arm64/kvm/hyp/switch.c | 2 +-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/kvm_arm
o the guest.
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
Change since V2:
- Load VTCR for TLB operations
---
arch/arm64/include/asm/kvm_arm.h | 19 +--
arch/arm64/include/asm/kvm_asm.h | 2 +-
arch/arm64/include/asm/kvm_host.h | 9 ++---
arch/
We use concatenated entry level page tables (upto 16tables) for
stage2. If we don't have sufficient contiguous pages (e.g, 16 * 64K),
fallback to the normal page table format, by going one level
deeper if permitted.
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
--
Add an option to specify the physical address size used by this
VM.
Signed-off-by: Suzuki K Poulose
---
arm/aarch64/include/kvm/kvm-config-arch.h | 5 -
arm/include/arm-common/kvm-config-arch.h | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arm/aarch64/include/kvm/kvm
Specify the physical size for the VM encoded in the vm type.
Signed-off-by: Suzuki K Poulose
---
arm/include/arm-common/kvm-arch.h | 6 +-
arm/kvm.c | 22 ++
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/arm/include/arm-common
arm64.
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
arch/arm64/include/asm/kvm_host.h | 14 --
arch/arm64/include/asm/kvm_hyp.h| 3 +--
arch/arm64/include/asm/kvm_mmu.h| 20 ++--
arch/arm64/include/asm
code, which would need substantial
changes. We could purse the solution independently and
switch the page table code once we have it ready.
Cc: Catalin Marinas
Cc: Marc Zyngier
Cc: Christoffer Dall
Signed-off-by: Suzuki K Poulose
---
Changes since V2:
- Restrict the IPA size to limit the number o
Allow architectures to perform initialisation based on the
KVM device fd ioctls, even before the VM is created.
Signed-off-by: Suzuki K Poulose
---
include/kvm/kvm.h | 4
kvm.c | 2 ++
2 files changed, 6 insertions(+)
diff --git a/include/kvm/kvm.h b/include/kvm/kvm.h
index
If the guest wants to use a larger physical address space place
the RAM at upper half of the address space. Otherwise, it uses the
default layout.
Signed-off-by: Suzuki K Poulose
---
arm/aarch32/include/kvm/kvm-arch.h | 6 --
arm/aarch64/include/kvm/kvm-arch.h | 15 ---
arm
On 02/07/18 11:12, Marc Zyngier wrote:
On 29/06/18 12:15, Suzuki K Poulose wrote:
Right now the stage2 page table for a VM is hard coded, assuming
an IPA of 40bits. As we are about to add support for per VM IPA,
prepare the stage2 page table helpers to accept the kvm instance
to make the right
On 29/06/18 12:15, Suzuki K Poulose wrote:
So far we had a static stage2 page table handling code, based on a
fixed IPA of 40bits. As we prepare for a configurable IPA size per
VM, make our stage2 page table code dynamic, to do the right thing
for a given VM. We ensure the existing condition is
Hi Eric,
On 02/07/18 11:51, Auger Eric wrote:
Hi Suzuki,
On 06/29/2018 01:15 PM, Suzuki K Poulose wrote:
Right now the stage2 page table for a VM is hard coded, assuming
an IPA of 40bits. As we are about to add support for per VM IPA,
prepare the stage2 page table helpers to accept the kvm
Hi Eric,
On 02/07/18 13:14, Auger Eric wrote:
Hi Suzuki,
On 06/29/2018 01:15 PM, Suzuki K Poulose wrote:
So far we had a static stage2 page table handling code, based on a
fixed IPA of 40bits. As we prepare for a configurable IPA size per
VM, make our stage2 page table code dynamic, to do
On 02/07/18 14:13, Marc Zyngier wrote:
On 29/06/18 12:15, Suzuki K Poulose wrote:
Allow specifying the physical address size for a new VM via
the kvm_type argument for KVM_CREATE_VM ioctl. This allows
us to finalise the stage2 page table format as early as possible
and hence perform the right
Hi Marc,
On 02/07/18 14:32, Marc Zyngier wrote:
On 29/06/18 12:15, Suzuki K Poulose wrote:
Now that we can manage the stage2 page table per VM, switch the
configuration details to per VM instance. We keep track of the
IPA bits, number of page table levels and the VTCR bits (which
depends on
On 02/07/18 14:50, Marc Zyngier wrote:
On 29/06/18 12:15, Suzuki K Poulose wrote:
So far we have restricted the IPA size of the VM to the default
value (40bits). Now that we can manage the IPA size per VM and
support dynamic stage2 page tables, allow VMs to have larger IPA.
This is done by
Hi Michael,
On 06/29/2018 06:42 PM, Michael S. Tsirkin wrote:
On Fri, Jun 29, 2018 at 12:15:21PM +0100, Suzuki K Poulose wrote:
virtio-mmio with virtio-v1 uses a 32bit PFN for the queue.
If the queue pfn is too large to fit in 32bits, which
we could hit on arm64 systems with 52bit physical
On 02/07/18 13:16, Marc Zyngier wrote:
On 29/06/18 12:15, Suzuki K Poulose wrote:
We set VTCR_EL2 very early during the stage2 init and don't
touch it ever. This is fine as we had a fixed IPA size. This
patch changes the behavior to set the VTCR for a given VM,
depending on its stage2
Hi Eric,
On 02/07/18 15:41, Auger Eric wrote:
Hi Suzuki,
On 06/29/2018 01:15 PM, Suzuki K Poulose wrote:
On arm64 VTTBR_EL2:BADDR holds the base address for the stage2
translation table. The Arm ARM mandates that the bits BADDR[x-1:0]
should be 0, where 'x' is defined for a given IP
On 03/07/18 13:47, Andrew Jones wrote:
This infrastructure already is used in hw/ppc/spapr.c
Whould it be better if we would pass something like kvm-type=48bGPA?
Otherwise I can decode another virt machine option (min_vm_phys_shift)
in kvm_type callback.
Yes, this is what I'm thinking. I don't
Hi,
are there any updates on this issue?
I'm using qemu 2.11.1 and I believe I'm experiencing the same problem explained
by Duane.
I'm unable to debug with gdb 32-bit kernel code using qemu-system-x86_64. GDB
complains that the target architecture is x86_64, even if VM's CPU is currently
runnin
On Fri, 19 Mar 2021 19:17:58 +0530 Alistair Francis
wrote
> On Sun, Mar 14, 2021 at 5:11 AM Vijai Kumar K wrote:
> >
> > Connect one shakti uart to the shakti_c machine.
> >
> > Signed-off-by: Vijai Kumar K
> > ---
>
Drop the unused fdt pointer in riscv_setup_rom_reset_vec API.
Signed-off-by: Vijai Kumar K
---
hw/riscv/boot.c | 2 +-
hw/riscv/spike.c| 2 +-
hw/riscv/virt.c | 2 +-
include/hw/riscv/boot.h | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/riscv
On Fri, 19 Mar 2021 19:14:31 +0530 Alistair Francis
wrote
> On Sun, Mar 14, 2021 at 5:14 AM Vijai Kumar K wrote:
> >
> > This is the initial implementation of Shakti UART.
> >
> > TX tested and works fine. RX is untested.
> >
On Fri, 19 Mar 2021 19:09:17 +0530 Alistair Francis
wrote
> On Sun, Mar 14, 2021 at 5:10 AM Vijai Kumar K wrote:
> >
> > C-Class is a member of the SHAKTI family of processors from Indian
> > Institute of Technology - Madras(IIT-M).
> > It i
Connect one shakti uart to the shakti_c machine.
Signed-off-by: Vijai Kumar K
---
hw/riscv/shakti_c.c | 8
include/hw/riscv/shakti_c.h | 2 ++
2 files changed, 10 insertions(+)
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index 45d0eedabd..6174136ffa 100644
--- a/hw
C-Class is a member of the SHAKTI family of processors from IIT-M.
It is an extremely configurable and commercial-grade 5-stage in-order
core supporting the standard RV64GCSUN ISA extensions.
Signed-off-by: Vijai Kumar K
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
2 files changed
sifive_u_cpu_init routine for shakti
- Error out when an unsupported CPU is specified
- Addressed formatting changes pointed out in review
Vijai Kumar K (4):
target/riscv: Add Shakti C class CPU
riscv: Add initial support for Shakti C machine
hw/char: Add Shakti UART emulation
hw/riscv: Connect
This is the initial implementation of Shakti UART.
Signed-off-by: Vijai Kumar K
---
MAINTAINERS | 2 +
hw/char/meson.build | 1 +
hw/char/shakti_uart.c | 185 ++
hw/char/trace-events | 4 +
include/hw/char
Add support for emulating Shakti reference platform based on C-class
running on arty-100T board.
https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst
Signed-off-by: Vijai Kumar K
---
MAINTAINERS | 7 +
default-configs/devices/riscv64
On Wed, 31 Mar 2021 21:05:47 +0530 Alistair Francis
wrote
> On Sun, Mar 21, 2021 at 1:09 AM Vijai Kumar K wrote:
> >
> > Add support for emulating Shakti reference platform based on C-class
> > running on arty-100T board.
> >
> > https
On Thu, 01 Apr 2021 22:51:42 +0530 Alistair Francis
wrote
> On Thu, Apr 1, 2021 at 1:18 PM Vijai Kumar K wrote:
> >
> >
> >
> >
> > On Wed, 31 Mar 2021 21:05:47 +0530 Alistair Francis
> > wrote
> >
> &g
C-Class is a member of the SHAKTI family of processors from IIT-M.
It is an extremely configurable and commercial-grade 5-stage in-order
core supporting the standard RV64GCSUN ISA extensions.
Signed-off-by: Vijai Kumar K
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
2 files changed
Connect one shakti uart to the shakti_c machine.
Signed-off-by: Vijai Kumar K
---
hw/riscv/shakti_c.c | 8
include/hw/riscv/shakti_c.h | 2 ++
2 files changed, 10 insertions(+)
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index c8205d3f22..e207fa83dd 100644
--- a/hw
Add support for emulating Shakti reference platform based on C-class
running on arty-100T board.
https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst
Signed-off-by: Vijai Kumar K
---
MAINTAINERS | 7 +
default-configs/devices/riscv64
This is the initial implementation of Shakti UART.
Signed-off-by: Vijai Kumar K
---
MAINTAINERS | 2 +
hw/char/meson.build | 1 +
hw/char/shakti_uart.c | 185 ++
hw/char/trace-events | 4 +
include/hw/char
shakti
- Error out when an unsupported CPU is specified
- Addressed formatting changes pointed out in review
Vijai Kumar K (4):
target/riscv: Add Shakti C class CPU
riscv: Add initial support for Shakti C machine
hw/char: Add Shakti UART emulation
hw/riscv: Connect Shakti UART to Shakti
On Fri, 02 Apr 2021 18:35:04 +0530 Alistair Francis
wrote
> On Thu, Apr 1, 2021 at 2:15 PM Vijai Kumar K wrote:
> >
> > Connect one shakti uart to the shakti_c machine.
> >
> > Signed-off-by: Vijai Kumar K
>
> In future can you plea
On Sat, 03 Apr 2021 01:35:25 +0530 Alistair Francis
wrote
> On Thu, Apr 1, 2021 at 2:15 PM Vijai Kumar K wrote:
> >
> > Changes in v3:
> > - Drop SHAKTI_C_DEBUG register
> >
> > Changes in v2:
> > - Moved CPU additi
Add documentation for Shakti C reference platform.
Signed-off-by: Vijai Kumar K
---
docs/system/riscv/shakti-c.rst | 82 ++
1 file changed, 82 insertions(+)
create mode 100644 docs/system/riscv/shakti-c.rst
diff --git a/docs/system/riscv/shakti-c.rst b/docs
Connect one shakti uart to the shakti_c machine.
Signed-off-by: Vijai Kumar K
---
hw/riscv/shakti_c.c | 7 +++
include/hw/riscv/shakti_c.h | 2 ++
2 files changed, 9 insertions(+)
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index e96436a3bf..07cc42a380 100644
--- a/hw
arty-100T
platform.
https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst
Signed-off-by: Vijai Kumar K
---
MAINTAINERS | 7 +
default-configs/devices/riscv64-softmmu.mak | 1 +
hw/riscv/Kconfig| 10 ++
hw
[3] https://gitlab.com/shaktiproject/uncore/devices/-/tree/master/uart_v2
Vijai Kumar K (3):
riscv: Add initial support for Shakti C class
hw/char: Add Shakti UART emulation
hw/riscv: Connect Shakti UART to Shakti platform
MAINTAINERS | 9 +
default-configs
This is the initial implementation of Shakti UART.
TX tested and works fine. RX is untested.
Signed-off-by: Vijai Kumar K
---
MAINTAINERS | 2 +
hw/char/meson.build | 1 +
hw/char/shakti_uart.c | 204 ++
hw/char/trace
ntional. Should we change it
anyway?
--
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software Júnior
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
On 24/05/2021 15:51, Richard Henderson wrote:
On 5/21/21 10:25 AM, Matheus K. Ferst wrote:
On 18/05/2021 07:12, Richard Henderson wrote:
On 5/17/21 3:50 PM, matheus.fe...@eldorado.org.br wrote:
+ if(a->l && (ctx->insns_flags & PPC_64B)) {
Space after IF.
> If I
I guess this is fine with movcond, but perhaps slightly better with
tcg_gen_setcondi_tl(cond, rt, temp, 0);
if (neg) {
tcg_gen_neg_tl(rt, rt);
}
TCG isn't the most optimizing of compilers...
r~
And also looks cleaner, I'll apply that too.
--
Matheus K. Ferst
Insti
~
If I remove it, the build for ppc will fail, because cpu_gpr is declared
as TCGv, and the helper uses i64 to match {get,set}_cpu_vsr{l,h}.
REQUIRE_64BIT makes the helper call unreachable for ppc, but it's a
runtime check. At build time, the compiler will check the types anyway,
and give
g/ppc64{,le}/Makefile.target. Would it be Mr. Gibson?
Uh... sorta? I also don't know much about what's going on here, but
I'm probably maintainer by default.
So, should I update MAINTAINERS in this series?
--
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldor
ce.
We could do something like:
> ppc64*-|ppc64le-*)
> container_hosts=x86_64
> container_image=debian-powerpc-test-cross
> container_cross_cc=${target%%-*}-linux-gnu-gcc-10
> container_cross_cc=powerpc${container_cross_cc#ppc}
But I think it's kind of ugly to repeat container_cross_cc line. If we do
that, we can bring ppc-* too, but another line would be needed to handle
ppc64abi32-*...
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Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software Júnior
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
On 20/04/2021 11:58, Richard Henderson wrote:
On 4/19/21 6:33 PM, matheus.fe...@eldorado.org.br wrote:
+#include
+#include
+
+int main(void)
+{
Oh, also, there's nothing in here that requires stdio.h.
r~
Forgot to remove. Will be fixed in the next version.
Thanks,
Matheus K.
uild}.docker
debian-ppc64{el-cross,le-crossbuild}.docker
debian-s390x-cross{,build}.docker
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Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software Júnior
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
Use "+r" for in/out argument.
r~
Fixed, thanks!
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software Júnior
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
iner:
+powerpc-test-debian-cross-container:
<<: *container_job_definition
stage: containers-layer2
needs: ['amd64-debian10-container']
Should this be debian11?
Yes, I'll send a new version.
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http:
sad part of this kind of approach is that it would leave us
with, eg.
arg_LBZX and arg_LBZUX instead of a single arg_X, making it harder to put
multiple insns under the same implementation.
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software
forwarded their arguments to a third method that does the real
work. Is this kind of approach desirable? We initially achieved this by
using const_elt to set r=0 for addi, which is not particularly nice, but
we can look for other solutions.
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDOR
ave set NORETURN. */
-g_assert_not_reached();
-}
-}
}
static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
You removed the uses, but left the field.
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software Júnior
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
_addi_tl(cpu_gpr[a->rt], cpu_gpr[a->ra], si);
+} else {
+tcg_gen_movi_tl(cpu_gpr[a->rt], si);
+}
+return true;
+}
I'd also keep this as in the last version, where trans_ADDI is called.
Thanks,
Matheus K. Ferst
Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/>
Analista de Software Júnior
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
On 30/04/2021 11:31, Richard Henderson wrote:
On 4/30/21 7:05 AM, Matheus K. Ferst wrote:
+ADDI 01 10 0--.-- .. \
+ 001110 . . @PLS_D
I'm not sure about this. It's a bit surprising to find ADDI here
On 30/04/2021 15:43, Richard Henderson wrote:
On 4/30/21 11:02 AM, Matheus K. Ferst wrote:
But in this case ADDI probably doesn't use PLS_D. You could use
static bool trans_PADDI(DisasContext *ctx, arg_PLS_D *a) { arg_D
d; if (!resolve_PLS_D(ctx, &d, a)) { return false; } return
t
+return true;
+}
+
The only difference between those two is tcg_gen_addi_tl/tcg_gen_movi_tl
and tcg_gen_add_tl/tcg_gen_mov_tl. We could do this in a single method
if we tcg_const_tl(a->si) in do_ldst_D. I'm not sure about the costs
involved, and we'd need to tcg_temp_fre
On 30/04/2021 21:50, Richard Henderson wrote:
On 4/30/21 4:54 PM, Matheus K. Ferst wrote:
The only difference between those two is
tcg_gen_addi_tl/tcg_gen_movi_tl and tcg_gen_add_tl/tcg_gen_mov_tl. We
could do this in a single method if we tcg_const_tl(a->si) in
do_ldst_D. I'm not su
Am Mittwoch, 20. Januar 2021, 22:12:30 EET schrieb Andreas K. Hüttel:
> > This patch just passes the waitid status directly back to the guest.
>
> This works at least as well as the previous versions, so ++ from me.
>
> Will do more testing over the next days to see if it maybe
This is the (statically linked) binary resulting from the source; with
it the problem can be demonstrated "standalone", without any other rv32
libraries or a complete chroot, just running the binary with qemu-
riscv32.
Generated with
(riscv-ilp32 chroot) farino /tmp # gcc -static -o wait-test-sho
I can confirm that the same binary works fine with qemu system
emulation:
(riscv-ilp32 qemu) (none) /tmp # ./wait-test-short
(riscv-ilp32 qemu) (none) /tmp #
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Here's the (abbreviated) output of strace'ing qemu:
farino ~ # strace -f /usr/bin/qemu-riscv32
/chroot/riscv-ilp32/tmp/wait-test-short
execve("/usr/bin/qemu-riscv32", ["/usr/bin/qemu-riscv32",
"/chroot/riscv-ilp32/tmp/wait-tes"...], 0x7ffd95fb1330 /* 40 vars */) = 0
[...]
[pid 16569] uname({sy
Here's qemu's own strace log:
farino ~ # /usr/bin/qemu-riscv32 -strace /chroot/riscv-ilp32/tmp/wait-test-short
10123 brk(NULL) = 0x00073000
10123 brk(0x00073880) = 0x00073880
10123 uname(0x407ffed8) = 0
10123 readlinkat(AT_FDCWD,"/proc/self/exe",0x407feff0,4096) = 39
10123 brk(0x00094880) = 0x0009
Thanks a lot! Will test and post the result on monday when I'm back
home.
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https://bugs.launchpad.net/bugs/1906193
Title:
riscv32 user mode emulation: fork return values broken
Status
After applying this patch on top of qemu-5.2.0, I can confirm that it
fixes the problem.
Thank you!!
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https://bugs.launchpad.net/bugs/1906193
Title:
riscv32 user mode emulation: fork
Just as a general remark, while this specific problem seems to be
solved, there may still be issues surrounding waitid().
(With this patch applied, in a rather complex environment I see bash
processes hanging in an infinite loop, with waitid involved. I am
working on isolating the problem and prov
I'm still seeing this with qemu 5.2.0
armv7a-softfp-linux-gnueabi-gcc -O2 -pipe -march=armv7-a -mfpu=vfpv3-d16
-mfloat-abi=softfp -Wl,-O1 -Wl,--as-needed glibc-test.c -o glibc-test
Allocating guest commpage: Operation not permitted
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ttps://bugs.launchpad.net/qemu/+bug/1906193
> Signed-off-by: Alistair Francis
Tested-by: Andreas K. Hüttel
> ---
> linux-user/signal.c | 26 --
> 1 file changed, 24 insertions(+), 2 deletions(-)
>
> diff --git a/linux-user/signal.c b/linux-user/signal.
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