On Fri, Aug 2, 2019 at 1:41 AM Aarushi Mehta wrote:
> diff --git a/MAINTAINERS b/MAINTAINERS
> index d6de200453..be688fcd5e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2530,6 +2530,13 @@ F: block/file-posix.c
> F: block/file-win32.c
> F: block/win32-aio.c
>
> +Linux io_uring
> +M: Aarus
On Fri, Aug 2, 2019 at 1:41 AM Aarushi Mehta wrote:
> +int bdrv_parse_aio(const char *mode, int *flags)
> +{
> +if (!strcmp(mode, "threads")) {
> +/* do nothing, default */
> +} else if (!strcmp(mode, "native")) {
> +*flags |= BDRV_O_NATIVE_AIO;
This 'if' should be covered
On Wed, Aug 7, 2019 at 2:06 PM Aarushi Mehta wrote:
>
>
>
> On Wed, 7 Aug, 2019, 17:15 Julia Suvorova, wrote:
>>
>> On Fri, Aug 2, 2019 at 1:41 AM Aarushi Mehta wrote:
>> > +int bdrv_parse_aio(const char *mode, int *flags)
>> > +{
>> > +if (!strcmp(mode, "threads")) {
>> > +/* do not
v3:
* Refactoring moved to a separate patch [Daniel]
* "websock" option renamed to "websocket" [Stefan]
* Added documentation [Daniel]
v2:
* Fixed initialization order [Daniel]
* Function arguments refactoring [Paolo]
* Added test [Stefan]
* Added meaningful error messag
New option "websocket" added to allow using WebSocket protocol for
chardev socket backend.
Example:
-chardev socket,websocket,server,id=...
Signed-off-by: Julia Suvorova
---
chardev/char-socket.c | 64 ++-
chardev/char.c| 8 +-
qapi/char.j
Upcoming websocket support requires additional parameters in function
headers that are already overloaded. This patch replaces the bunch of
parameters with a single structure pointer.
Signed-off-by: Julia Suvorova
---
chardev/char-socket.c | 55 +++
1 file
Test order:
Creating server websocket chardev
Creating usual tcp chardev client
Sending handshake message from client
Receiving handshake reply
Sending ping frame with "hello" payload
Receiving pong reply
Sending binary data "world"
Checking the received data on serv
This series adds support for the nRF51 SoC UART, that used in
BBC Micro:bit board, and QTest for it.
v3:
* serial_hd() moved to the board code
* sysbus_init_child_obj() used for initialization
* qemu_chr_fe_accept_input() called after byte popping
v2:
* Suspend/Enable functionalit
New mini-kernel test for nRF51 SoC UART.
Signed-off-by: Julia Suvorova
Acked-by: Thomas Huth
Reviewed-by: Stefan Hajnoczi
---
tests/boot-serial-test.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c
index f865822e32..
Not implemented: CTS/NCTS, PSEL*.
Signed-off-by: Julia Suvorova
---
hw/char/Makefile.objs| 1 +
hw/char/nrf51_uart.c | 330 +++
hw/char/trace-events | 4 +
include/hw/char/nrf51_uart.h | 78 +
4 files changed, 413 insertions(+)
Wire up nRF51 UART in the corresponding SoC.
Signed-off-by: Julia Suvorova
---
hw/arm/microbit.c | 2 ++
hw/arm/nrf51_soc.c | 20
include/hw/arm/nrf51_soc.h | 3 +++
3 files changed, 25 insertions(+)
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
inde
On 31.10.2018 00:25, Steffen Görtz wrote:
Adds a header that provides definitions that are used
across nRF51 peripherals
Signed-off-by: Steffen Görtz
---
hw/arm/nrf51_soc.c | 33 ++-
include/hw/arm/nrf51.h | 44
in
Some functional tests for:
Basic reception/transmittion
Suspending
INTEN* registers
Based-on: <20181031002526.14262-1-cont...@steffen-goertz.de>
Signed-off-by: Julia Suvorova
---
This patch was part of nRF51 UART patchset, but wasn't included in the latest
revision. Due to upcoming lo
On 05.11.2018 15:24, Alex Bennée wrote:
Julia Suvorova via Qemu-devel writes:
Some functional tests for:
Basic reception/transmittion
Suspending
INTEN* registers
Based-on: <20181031002526.14262-1-cont...@steffen-goertz.de>
Signed-off-by: Julia Suvorova
---
This pat
On 05.11.2018 19:16, Philippe Mathieu-Daudé wrote:
Hi Julia,
On 5/11/18 11:45, Julia Suvorova via Qemu-devel wrote:
Some functional tests for:
Basic reception/transmittion
Suspending
INTEN* registers
Based-on: <20181031002526.14262-1-cont...@steffen-goertz.de>
Signed-
If the memory is set using a file, and PC is specified on the command
line, it will be overwritten with the value 'entry'. This is not only
illogical, but also incorrect, because the load_ * functions do not take
into account the specifics of the ARM-M PC.
Signed-off-by: Julia Suvorova
---
hw/co
On 16.01.2019 0:51, Alistair Francis wrote:
On Tue, Jan 15, 2019 at 7:04 AM Julia Suvorova via Qemu-devel
wrote:
If the memory is set using a file, and PC is specified on the command
line, it will be overwritten with the value 'entry'. This is not only
illogical, but also incorrec
On 17.01.2019 13:13, Stefan Hajnoczi wrote:
On Wed, Jan 16, 2019 at 10:05:58PM +0300, Julia Suvorova via Qemu-devel wrote:
On 16.01.2019 0:51, Alistair Francis wrote:
On Tue, Jan 15, 2019 at 7:04 AM Julia Suvorova via Qemu-devel
wrote:
If the memory is set using a file, and PC is specified
v4:
* Replace sprintf with g_strdup_printf [Peter]
* Move socket connection to qtest library [Peter]
* Use memcmp instead of strcmp [Stefan]
* Remove using global_qtest [Thomas]
v3:
* Fix directory leak [Stefan]
Based-on: <20190110094020.18354-1-stefa...@redhat.com>
Julia Suvo
Some functional tests for:
Basic reception/transmittion
Suspending
INTEN* registers
Signed-off-by: Julia Suvorova
---
tests/microbit-test.c | 84 +++
1 file changed, 84 insertions(+)
diff --git a/tests/microbit-test.c b/tests/microbit-test.c
i
Run qtest with a socket that connects QEMU chardev and test code.
Signed-off-by: Julia Suvorova
---
tests/libqtest.c | 26 ++
tests/libqtest.h | 11 +++
2 files changed, 37 insertions(+)
diff --git a/tests/libqtest.c b/tests/libqtest.c
index 55750dd68d..3a015cfe1
Using of global_qtest is not required here. Let's replace functions like
readl() with the corresponding qtest_* counterparts.
Signed-off-by: Julia Suvorova
---
tests/microbit-test.c | 247 ++
1 file changed, 129 insertions(+), 118 deletions(-)
diff --git
On 10.01.2019 12:48, Thomas Huth wrote:
On 2019-01-10 10:40, Stefan Hajnoczi wrote:
This test verifies that we read back the expected I2C WHO_AM_I register
values for the accelerometer/magnetometer.
Signed-off-by: Stefan Hajnoczi
---
tests/microbit-test.c | 44
New option "websock" added to allow using websocket protocol for
chardev socket backend.
Example:
-chardev socket,websock,id=...
Signed-off-by: Julia Suvorova
---
chardev/char-socket.c | 124 +++---
chardev/char.c| 8 ++-
qapi/char.json|
Test order:
Creating server websocket chardev
Creating usual tcp chardev client
Sending handshake message from client
Receiving handshake reply
Sending ping frame with "hello" payload
Receiving pong reply
Sending binary data "world"
Checking the received data on serv
v2:
* Fixed initialization order [Daniel]
* Function arguments refactoring [Paolo]
* Added test [Stefan]
* Added meaningful error message [Stefan]
* Added "websock:" URI prefix support
Julia Suvorova (2):
chardev: Add websocket support
tests/test-char: Check websocket chard
On 28.08.2018 13:09, Daniel P. Berrangé wrote:
On Tue, Aug 28, 2018 at 01:04:41PM +0300, Julia Suvorova wrote:
On 28.08.2018 12:02, Daniel P. Berrangé wrote:
On Mon, Aug 27, 2018 at 09:41:02PM +0300, Julia Suvorova wrote:
New option "websock" added to allow using websocket protocol for
chardev
On 28.08.2018 12:02, Daniel P. Berrangé wrote:
On Mon, Aug 27, 2018 at 09:41:02PM +0300, Julia Suvorova wrote:
New option "websock" added to allow using websocket protocol for
chardev socket backend.
Example:
-chardev socket,websock,id=...
Signed-off-by: Julia Suvorova
---
chardev/char-
Handle SCS reserved registers listed in ARMv6-M ARM D3.6.1.
All reserved registers are RAZ/WI.
Signed-off-by: Julia Suvorova
---
hw/intc/armv7m_nvic.c | 69 +++
1 file changed, 57 insertions(+), 12 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc
Check that reserved SCS registers return 0 at read,
and writes are ignored.
Based-on: <20180627143815.1829-1-j...@jms.id.au>
Based-on: <20180630091343.14391-1-stefa...@redhat.com>
Signed-off-by: Julia Suvorova
---
Test will work if Joel's patches will use ARMv6-M.
tests/Makefile.include
Julia Suvorova (2):
nvic: Handle ARMv6-M SCS reserved registers
tests: Add ARMv6-M reserved register test
hw/intc/armv7m_nvic.c | 69 +--
tests/Makefile.include| 2 +
tests/tcg/arm/test-reserved-reg.c | 60 +++
3 fil
MSR handling is the only place where CONTROL.nPRIV is modified.
Signed-off-by: Julia Suvorova
---
target/arm/helper.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 5ee229eb35..83cca554ad 100644
--- a/target/arm/helper.c
On 05.07.2018 13:33, Peter Maydell wrote:
On 4 July 2018 at 21:36, Julia Suvorova wrote:
MSR handling is the only place where CONTROL.nPRIV is modified.
Signed-off-by: Julia Suvorova
---
target/arm/helper.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/ar
On 05.07.2018 13:54, Peter Maydell wrote:
On 4 July 2018 at 20:58, Julia Suvorova wrote:
Handle SCS reserved registers listed in ARMv6-M ARM D3.6.1.
All reserved registers are RAZ/WI.
Signed-off-by: Julia Suvorova
---
hw/intc/armv7m_nvic.c | 69 +++
v2:
* Use ARM_FEATURE_M_MAIN instead of ARM_FEATURE_V7 in most cases
* Remove CPUID registers check
* Use bad_offset instead of return
* Misc style fixes
Julia Suvorova (2):
nvic: Handle ARMv6-M SCS reserved registers
tests: Add ARMv6-M reserved register test
hw/intc/armv7m_n
Handle SCS reserved registers listed in ARMv6-M ARM D3.6.1.
All reserved registers are RAZ/WI. ARM_FEATURE_M_MAIN is used for the
checks, because these registers are reserved in ARMv8-M Baseline too.
Signed-off-by: Julia Suvorova
---
hw/intc/armv7m_nvic.c | 51 +++
Check that reserved SCS registers return 0 at read,
and writes are ignored.
Based-on: <20180627143815.1829-1-j...@jms.id.au>
Based-on: <20180630091343.14391-1-stefa...@redhat.com>
Signed-off-by: Julia Suvorova
---
Test will work if Joel's patches will use ARMv6-M.
tests/Makefile.include
On 06.07.2018 00:50, Julia Suvorova wrote:
v2:
* Use ARM_FEATURE_M_MAIN instead of ARM_FEATURE_V7 in most cases
* Remove CPUID registers check
* Use bad_offset instead of return
* Misc style fixes
Julia Suvorova (2):
nvic: Handle ARMv6-M SCS reserved registers
tests: Ad
Check that reserved SCS registers return 0 at read,
and writes are ignored.
Based-on: <20180627143815.1829-1-j...@jms.id.au>
Based-on: <20180630091343.14391-1-stefa...@redhat.com>
Signed-off-by: Julia Suvorova
---
Test will work if Joel's patches will use ARMv6-M.
tests/Makefile.include
Handle SCS reserved registers listed in ARMv6-M ARM D3.6.1.
All reserved registers are RAZ/WI. ARM_FEATURE_M_MAIN is used for the
checks, because these registers are reserved in ARMv8-M Baseline too.
Signed-off-by: Julia Suvorova
---
hw/intc/armv7m_nvic.c | 51 +++
v3:
* Fix indents
v2:
* Use ARM_FEATURE_M_MAIN instead of ARM_FEATURE_V7 in most cases
* Remove CPUID registers check
* Use bad_offset instead of return
* Misc style fixes
Julia Suvorova (2):
nvic: Handle ARMv6-M SCS reserved registers
tests: Add ARMv6-M reserved register t
MSR handling is the only place where CONTROL.nPRIV is modified.
Signed-off-by: Julia Suvorova
---
v2:
* Add the check in the CONTROL_NS case
target/arm/helper.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 5
The differences from ARMv7-M NVIC are:
* ARMv6-M only supports up to 32 external interrupts
(configurable feature already). The ICTR is reserved.
* Active Bit Register is reserved.
* ARMv6-M supports 4 priority levels against 256 in ARMv7-M.
Signed-off-by: Julia Suvorova
---
hw/intc/arm
Forbid stack alignment change. (CCR)
Reserve FAULTMASK, BASEPRI registers.
Report any fault as HardFault. Disable MemManage, BusFault and
UsageFault, so they always escalated to HardFault. (SHCSR)
Signed-off-by: Julia Suvorova
---
This is the last cortex-m0 patch.
hw/intc/armv7m_nvic.c | 10 +++
On 17.07.2018 16:09, Peter Maydell wrote:
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index a914ce4e8c..3788cb773d 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -220,6 +220,11 @@ static void arm_cpu_reset(CPUState *s)
env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
On 17.07.2018 16:49, Peter Maydell wrote:
On 17 July 2018 at 14:42, Julia Suvorova wrote:
On 17.07.2018 16:09, Peter Maydell wrote:
This should be outside the "if v8" if(), because you also want it for v6M
(giving you the v6M CCR value of STKALIGN and UNALIGN_TRP set and all
other bits clear).
Forbid stack alignment change. (CCR)
Reserve FAULTMASK, BASEPRI registers.
Report any fault as a HardFault. Disable MemManage, BusFault and
UsageFault, so they always escalated to HardFault. (SHCSR)
Signed-off-by: Julia Suvorova
---
v2:
* Changed CCR reset value
hw/intc/armv7m_nvic.c | 10 +
On 17.07.2018 15:58, Peter Maydell wrote:
On 10 July 2018 at 16:33, Julia Suvorova wrote:
The differences from ARMv7-M NVIC are:
* ARMv6-M only supports up to 32 external interrupts
(configurable feature already). The ICTR is reserved.
* Active Bit Register is reserved.
* ARMv6-M s
The differences from ARMv7-M NVIC are:
* ARMv6-M only supports up to 32 external interrupts
(configurable feature already). The ICTR is reserved.
* Active Bit Register is reserved.
* ARMv6-M supports 4 priority levels against 256 in ARMv7-M.
Signed-off-by: Julia Suvorova
---
v2:
* Ad
On 19.07.2018 19:25, Peter Maydell wrote:
On 19 July 2018 at 13:16, Julia Suvorova wrote:
The differences from ARMv7-M NVIC are:
* ARMv6-M only supports up to 32 external interrupts
(configurable feature already). The ICTR is reserved.
* Active Bit Register is reserved.
* ARMv6-M s
Basic implementation of nRF51 SoC UART.
Description could be found here:
http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
The following features are not yet implemented:
Control with SUSPEND/START*/STOP*
CTS/NCTS flow control
Mapping registers to pins
Signed-off-by: Julia Suvo
nRF51 SoC implementation is intended for the BBC Micro:bit board,
which has 256 KB flash and 16 KB RAM.
Added FICR defines.
Signed-off-by: Julia Suvorova
---
hw/arm/nrf51_soc.c | 12 +++-
include/hw/arm/nrf51_soc.h | 1 +
2 files changed, 8 insertions(+), 5 deletions(-)
diff --
This series adds basic support for the nRF51 SoC UART, that used in
BBC Micro:bit board, and QTest for it.
Based-on: <20180503090532.3113-1-j...@jms.id.au>
Julia Suvorova (3):
hw/arm/nrf51_soc: Fix compilation and memory regions
hw/char/nrf51_uart: Implement nRF51 SoC UART
tests/boot-serial
New mini-kernel test for nRF51 SoC UART.
Signed-off-by: Julia Suvorova
---
tests/boot-serial-test.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c
index 4d6815c3e0..e6dbc8a293 100644
--- a/tests/boot-serial-test.c
+++ b/tests/
On 31.05.2018 12:42, Stefan Hajnoczi wrote:
> On Wed, May 30, 2018 at 01:03:37AM +0300, Julia Suvorova wrote:
>> The following features are not yet implemented:
>> Control with SUSPEND/START*/STOP*
>
> This is probably worth implementing for completeness. Just rx_enabled
> and tx_enabled boo
On 01.06.2018 13:44, Stefan Hajnoczi wrote:
On Fri, Jun 1, 2018 at 11:41 AM, Stefan Hajnoczi wrote:
On Thu, May 31, 2018 at 2:58 PM, sundeep subbaraya
wrote:
On Wed, May 30, 2018 at 3:33 AM, Julia Suvorova via Qemu-devel
wrote:
+static uint64_t uart_read(void *opaque, hwaddr addr, unsigned
On 26.07.2018 05:36, Joel Stanley wrote:
The nRF51 is a Cortex-M0 microcontroller with an on-board radio module,
plus other common ARM SoC peripherals.
http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
This defines a basic model of the CPU and memory, with no peripherals
implemented at t
On 30.07.2018 17:02, Joel Stanley wrote:
On 26 July 2018 at 20:31, Julia Suvorova wrote:
+++ b/hw/arm/nrf51_soc.c
+static void nrf51_soc_init(Object *obj)
+{
+NRF51State *s = NRF51_SOC(obj);
+
+memory_region_init(&s->container, obj, "nrf51-container",
UINT64_MAX);
+
+object_init
On 08.08.2018 12:09, Stefan Hajnoczi wrote:
On Mon, Aug 6, 2018 at 11:01 AM, Steffen Görtz
wrote:
+#define PAGE_SIZE 1024
+#define FLASH_SIZE (256 * PAGE_SIZE)
+#define FLASH_BASE 0x
+#define UICR_BASE 0x10001000
+#define UICR_SIZE 0x100
+
This series adds support for the nRF51 SoC UART, that used in
BBC Micro:bit board, and QTest for it.
v2:
* Suspend/Enable functionality added
* Connection to SoC moved to a separate patch
* Added QTest for checking reception functionality
* Mini-kernel test changed to fit current i
Not implemented: CTS/NCTS, PSEL*.
Signed-off-by: Julia Suvorova
---
hw/char/Makefile.objs| 1 +
hw/char/nrf51_uart.c | 329 +++
hw/char/trace-events | 4 +
include/hw/char/nrf51_uart.h | 78 +
4 files changed, 412 insertions(+)
Wire up nRF51 UART in the corresponding SoC using in-place init/realize.
Based-on: <20180803052137.10602-1-j...@jms.id.au>
Signed-off-by: Julia Suvorova
---
hw/arm/nrf51_soc.c | 20
include/hw/arm/nrf51_soc.h | 3 +++
2 files changed, 23 insertions(+)
diff --git a
Some functional tests for:
Basic reception/transmittion
Suspending
INTEN* registers
Based-on: <20180806100114.21410-6-cont...@steffen-goertz.de>
Signed-off-by: Julia Suvorova
---
tests/microbit-test.c | 106 --
1 file changed, 103 insertions(+
New mini-kernel test for nRF51 SoC UART.
Signed-off-by: Julia Suvorova
---
tests/boot-serial-test.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c
index 952a2e7ead..19714c3f87 100644
--- a/tests/boot-serial-test.c
+++
Some devices (like nvic in armv7m) are not accessable through
address_space_memory, therefore can not be tested with qtest.
Signed-off-by: Julia Suvorova
---
qtest.c | 39 ++-
1 file changed, 26 insertions(+), 13 deletions(-)
diff --git a/qtest.c b/qtest.c
in
On 10.08.2018 09:02, Stefan Hajnoczi wrote:
On Wed, Aug 8, 2018 at 10:07 PM, Julia Suvorova wrote:
+static uint64_t uart_read(void *opaque, hwaddr addr, unsigned int size)
+{
+NRF51UARTState *s = NRF51_UART(opaque);
+uint64_t r;
+
+if (!s->enabled) {
+return 0;
+}
+
+
Fixup some typos in the comments.
Signed-off-by: Julia Suvorova
---
include/chardev/char-fe.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/chardev/char-fe.h b/include/chardev/char-fe.h
index 71cd069478..c67271f1ba 100644
--- a/include/chardev/char-fe.h
+
New option "websock" added to allow using websocket protocol for
chardev socket backend.
Example:
-chardev socket,websock,id=...
Signed-off-by: Julia Suvorova
---
chardev/char-socket.c | 75 ---
chardev/char.c| 3 ++
qapi/char.json| 3
On 13.08.2018 12:47, Stefan Hajnoczi wrote:
On Mon, Aug 13, 2018 at 10:08 AM Julia Suvorova wrote:
On 10.08.2018 09:02, Stefan Hajnoczi wrote:
On Wed, Aug 8, 2018 at 10:07 PM, Julia Suvorova wrote:
+static uint64_t uart_read(void *opaque, hwaddr addr, unsigned int size)
+{
+NRF51UARTStat
On 13.08.2018 15:02, Paolo Bonzini wrote:
Thanks Julia, just a few cleanups to simplify the prototypes of some
functions.
Thanks for the review, I'll do the refactoring.
Best regards, Julia Suvorova.
On 13.08.2018 15:21, Daniel P. Berrangé wrote:
On Mon, Aug 13, 2018 at 01:20:37PM +0300, Julia Suvorova via Qemu-devel wrote:
New option "websock" added to allow using websocket protocol for
chardev socket backend.
Example:
-chardev socket,websock,id=...
Signed-off-by: Juli
On 21.08.2018 14:43, Steffen Görtz wrote:
Hi Peter,
+
+static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size)
+{
+qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
+ __func__, addr, size);
+return 1;
+}
+
+static void clock_write(void *opaque, h
On 17.06.2018 19:33, Peter Maydell wrote:
On 17 June 2018 at 06:36, Richard Henderson
wrote:
On 06/15/2018 12:55 AM, Peter Maydell wrote:
+uint32_t armv6m_insn[] = {0xf3808000 /* msr */, 0xf3b08040 /* dsb */,
+ 0xf3b08050 /* dmb */, 0xf3b08060 /* isb */,
+
The arrays were made static, "if" was simplified because V7M and V8M
define V6 feature.
Signed-off-by: Julia Suvorova
---
target/arm/translate.c | 27 +--
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index
Unlike ARMv7-M, ARMv6-M only supports naturally aligned memory accesses
for 16-bit halfword and 32-bit word accesses using the LDR, LDRH,
LDRSH, STR and STRH instructions.
Signed-off-by: Julia Suvorova
---
target/arm/translate.c | 18 --
1 file changed, 16 insertions(+), 2 deleti
This feature is intended to distinguish ARMv8-M variants: Baseline and
Mainline. ARMv7-M compatibility requires the Main Extension. ARMv6-M
compatibility is provided by all ARMv8-M implementations.
Signed-off-by: Julia Suvorova
---
target/arm/cpu.c | 3 +++
target/arm/cpu.h | 1 +
2 files change
Unlike ARMv7-M, ARMv6-M and ARMv8-M Baseline only supports naturally
aligned memory accesses for load/store instructions.
Signed-off-by: Julia Suvorova
---
target/arm/translate.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/targ
v2:
* Added feature bit for the Main Extention
* Alignment patch is modified to use ARM_FEATURE_M_MAIN
Julia Suvorova (2):
target/arm: Introduce ARM_FEATURE_M_MAIN
target/arm: Strict alignment for ARMv6-M and ARMv8-M Baseline
target/arm/cpu.c | 3 +++
target/arm/cpu.h |
ARMv6-M supports 6 Thumb2 instructions. This patch checks for these
instructions and allows their execution.
Like Thumb2 cores, ARMv6-M always interprets BL instruction as 32-bit.
This patch is required for future Cortex-M0 support.
Signed-off-by: Julia Suvorova
---
target/arm/translate.c | 35
On 13.06.2018 17:05, Stefan Hajnoczi wrote:
On Tue, Jun 12, 2018 at 11:46:32PM +0300, Julia Suvorova wrote:
ARMv6-M supports 6 Thumb2 instructions. This patch checks for these
instructions and allows their execution.
Like Thumb2 cores, ARMv6-M always interprets BL instruction as 32-bit.
This pa
On 15.06.2018 13:55, Peter Maydell wrote:
On 12 June 2018 at 21:46, Julia Suvorova wrote:
ARMv6-M supports 6 Thumb2 instructions. This patch checks for these
instructions and allows their execution.
Like Thumb2 cores, ARMv6-M always interprets BL instruction as 32-bit.
This patch is required f
Despite the fact that now when the initialization of vde fails, qemu
does not end silently, no informative error is printed. The patch
generates an error and pushes it through the calling function.
Related bug: https://bugs.launchpad.net/qemu/+bug/676029
Signed-off-by: Julia Suvorova
---
net/vd
basename(3) and dirname(3) modify their argument and may return
pointers to statically allocated memory which may be overwritten by
subsequent calls.
g_path_get_basename and g_path_get_dirname have no such issues, and
therefore more preferable.
Signed-off-by: Julia Suvorova
---
fsdev/virtfs-prox
On 01.03.2018 13:59, Cornelia Huck wrote:
> On Thu, 1 Mar 2018 10:47:42 +0100
> Marc-André Lureau wrote:
>
>> Hi
>>
>> On Thu, Mar 1, 2018 at 8:08 AM, Julia Suvorova via Qemu-devel
>> wrote:
>>> basename(3) and dirname(3) modify their argument
On 01.03.2018 14:21, Paolo Bonzini wrote:
> On 01/03/2018 11:59, Cornelia Huck wrote:
Signed-off-by: Julia Suvorova
>>> What about adding a warning for basename()/dirname() usage in
>>> scripts/checkpatch.pl ?
>> +1 to that.
>>
>
> Good idea indeed. Julia, would you like to send a
Hi,
My name is Julia. I am a bachelor of mathematics from Moscow who is
interested in system programming. I've been selected for Outreachy this
year to work on the micro:bit project.
The project is divided between two people - me and Steffen.
We will develop support for the micro:bit board and the
> This patch adds Intel Hexadecimal Object File format support to
> the loader. The file format specification is available here:
> http://www.piclist.com/techref/fileext/hex/intel.htm
>
> The file format is mainly intended for embedded systems
> and microcontrollers, such as Micro:bit Arduino, AR
Signed-off-by: Julia Suvorova
---
scripts/checkpatch.pl | 5 +
1 file changed, 5 insertions(+)
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index 1b4b812..6c4fb42 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -2584,6 +2584,11 @@ sub process {
On 02.03.2018 11:56, Paolo Bonzini wrote:
> On 02/03/2018 09:22, Julia Suvorova wrote:
>> Signed-off-by: Julia Suvorova
>> ---
>> scripts/checkpatch.pl | 5 +
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
>> index 1b4b812..6c4fb42 100755
g_path_get_* do the same as g_strdup(basename/dirname(...)) but
without modifying the argument.
Signed-off-by: Julia Suvorova
---
scripts/checkpatch.pl | 5 +
1 file changed, 5 insertions(+)
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index 1b4b812..a88af61 100755
--- a/scrip
On 01.02.2019 12:14, Markus Armbruster wrote:
Julia Suvorova via Qemu-devel writes:
The whitelist option allows to run a reduced monitor with a subset of
QMP commands. This allows the monitor to run in secure mode, which is
For a value of "secure". I'm not saying this
On 11.02.2019 18:51, Daniel P. Berrangé wrote:
On Thu, Jan 31, 2019 at 03:03:21PM -0600, Eric Blake wrote:
On 1/31/19 2:26 PM, Julia Suvorova via Qemu-devel wrote:
The whitelist option allows to run a reduced monitor with a subset of
QMP commands. This allows the monitor to run in secure
On 30.05.2019 17:07, Paolo Bonzini wrote:
On 30/05/19 10:42, Kevin Wolf wrote:
Am 27.05.2019 um 11:23 hat Stefan Hajnoczi geschrieben:
qemu_aio_get() does not zero allocated memory. Explicitly initialize
laiocb->co to prevent an uninitialized memory access in
qemu_laio_process_completion().
N
Callback-based laio_submit() and laio_cancel() were left after
rewriting Linux AIO backend to coroutines in hope that they would be
used in other code that could bypass coroutines. They can be safely
removed because they have not been used since that time.
Signed-off-by: Julia Suvorova
---
block
On 12.02.2019 10:13, Markus Armbruster wrote:
Julia Suvorova via Qemu-devel writes:
On 01.02.2019 12:14, Markus Armbruster wrote:
Julia Suvorova via Qemu-devel writes:
The whitelist option allows to run a reduced monitor with a subset of
QMP commands. This allows the monitor to run in
The whitelist option allows to run a reduced monitor with a subset of
QMP commands. This allows the monitor to run in secure mode, which is
convenient for sending commands via the WebSocket monitor using the
web UI. This is planned to be done on micro:bit board.
The list of allowed commands should
On 01.02.2019 0:03, Eric Blake wrote:
On 1/31/19 2:26 PM, Julia Suvorova via Qemu-devel wrote:
The whitelist option allows to run a reduced monitor with a subset of
QMP commands. This allows the monitor to run in secure mode, which is
convenient for sending commands via the WebSocket monitor
On 21.01.2019 20:24, Peter Maydell wrote:
On Thu, 17 Jan 2019 at 19:27, Peter Maydell wrote:
On Thu, 17 Jan 2019 at 10:58, Julia Suvorova wrote:
On 17.01.2019 13:13, Stefan Hajnoczi wrote:
generic_loader_reset() calls cpu_reset(s->cpu) followed by
CPUClass->set_pc(s->cpu, s->addr).
ARM's
Using of global_qtest is not required here. Let's replace functions like
readl() with the corresponding qtest_* counterparts.
Signed-off-by: Julia Suvorova
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Thomas Huth
Reviewed-by: Stefan Hajnoczi
---
tests/microbit-test.c | 247 ++
Run qtest with a socket that connects QEMU chardev and test code.
Signed-off-by: Julia Suvorova
Reviewed-by: Stefan Hajnoczi
---
tests/libqtest.c | 25 +
tests/libqtest.h | 11 +++
2 files changed, 36 insertions(+)
diff --git a/tests/libqtest.c b/tests/libqtest.
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