On 05/07/17 07:45, Tian, Kevin wrote:
>> From: Liu, Yi L
>> Sent: Monday, July 3, 2017 6:31 PM
>>
>> Hi Jean,
>>
>>
>>>
2. Define a structure in include/uapi/linux/iommu.h(newly added header
>> file)
struct iommu_tlb_invalidate {
__u32 scope;
/* pasid-selective invalid
On 05/07/17 08:14, Tian, Kevin wrote:
>> From: Jean-Philippe Brucker [mailto:jean-philippe.bruc...@arm.com]
>> Sent: Monday, June 19, 2017 6:15 PM
>>
>> On 19/06/17 08:54, Bharat Bhushan wrote:
>>> Hi Eric,
>>>
>>> I started added replay in virt
On 05/07/17 08:25, Tian, Kevin wrote:
>> From: Jean-Philippe Brucker [mailto:jean-philippe.bruc...@arm.com]
>> Sent: Tuesday, June 27, 2017 12:13 AM
>>
>> On 26/06/17 09:22, Auger Eric wrote:
>>> Hi Jean-Philippe,
>>>
>>> On 19/06/2017 12:15,
On 05/07/17 09:49, Bharat Bhushan wrote:>>> Also when setup msi-route
kvm_irqchip_add_msi_route() we needed to
>> provide the translated address.
>>> According to my understanding this is required because kernel does no go
>> through viommu translation when generating interrupt, no?
>>
>> yes this
On 06/07/17 12:24, Bharat Bhushan wrote:
>
>
>> -Original Message-----
>> From: Jean-Philippe Brucker [mailto:jean-philippe.bruc...@arm.com]
>> Sent: Thursday, July 06, 2017 3:33 PM
>> To: Bharat Bhushan ; Auger Eric
>> ; eric.auger@gmail.com;
>&
On 07/07/17 07:21, Tian, Kevin wrote:
> sorry I didn't quite get this part, and here is my understanding:
>
> Guest programs vIOMMU to map a gIOVA (used by MSI to a GPA
> of doorbell register of virtual irqchip. vIOMMU then
> triggers VFIO map/unmap to update physical IOMMU page
> table for gIOV
Hi Ashish,
On 07/07/17 00:33, Tian, Kevin wrote:
>> From: Kalra, Ashish [mailto:ashish.ka...@cavium.com]
>> Sent: Friday, July 7, 2017 7:24 AM
>>
>> I have a generic question on vIOMMU support, is there any proposal/plan to
>> add ATS/PRI extension support to vIOMMUs and allow
>> handling for end
On 06/07/17 22:11, Auger Eric wrote:
> Hello Bharat, Jean-Philippe,
> On 06/07/2017 12:02, Jean-Philippe Brucker wrote:
>> On 05/07/17 09:49, Bharat Bhushan wrote:>>> Also when setup msi-route
>> kvm_irqchip_add_msi_route() we needed to
>>>> provide the tr
On 07/07/17 12:36, Bharat Bhushan wrote:
>>> In this proposal, QEMU reserves a iova-range for guest (not host) and guest
>> kernel will use this as msi-iova untranslated (IOMMU_RESV_MSI). While this
>> does not change host interface and it will continue to use host reserved
>> mapping for actual in
On 17/05/17 11:27, Liu, Yi L wrote:
> On Fri, May 12, 2017 at 03:58:51PM -0600, Alex Williamson wrote:
>> On Wed, 26 Apr 2017 18:12:02 +0800
>> "Liu, Yi L" wrote:
>>>
>>> +/* IOCTL for Shared Virtual Memory Bind */
>>> +struct vfio_device_svm {
>>> + __u32 argsz;
>>> +#define VFIO_SVM_BIND_P
On 23/05/17 08:50, Liu, Yi L wrote:
> On Fri, Apr 28, 2017 at 01:51:42PM +0100, Jean-Philippe Brucker wrote:
[...]
>>>>
>>>> For the next version of my SVM series, I was thinking of passing group
>>>> instead of device to iommu_bind. Since all devices in a gr
some small fixes.
>>
>> This is a proof of concept based on the virtio-iommu specification
>> written by Jean-Philippe Brucker [1].
>>
>> The device gets instantiated using the "-device virtio-iommu-device"
>> option. It currently works with ARM virt mac
On 17/08/17 16:26, Auger Eric wrote:
> Hi Linu, Jean,
>
> On 17/08/2017 15:39, Jean-Philippe Brucker wrote:
>> Hi Linu,
>>
>> On 17/08/17 12:26, Linu Cherian wrote:
>>> Hi Eric,
>>>
>>> On Tue Aug 01, 2017 at 11:33:06AM +0200, Eric Auger wrot
On 18/07/17 15:29, Alex Williamson wrote:
> On Tue, 18 Jul 2017 10:38:40 +0100
> Jean-Philippe Brucker wrote:
>
>> On 17/07/17 23:45, Alex Williamson wrote:
>> [..]
>>>>>
>>>>> How does a user learn which model(s) are supported by the interfa
On 12/10/17 11:09, Auger Eric wrote:
> Hi Peter,
>
> On 12/10/2017 11:54, Peter Maydell wrote:
>> On 11 October 2017 at 17:08, Auger Eric wrote:
>>> Hi Peter,
>>>
>>> On 11/10/2017 16:56, Peter Maydell wrote:
On 19 September 2017 at 08:46, Eric Auger wrote:
> This series implements the
Hi Eric,
A few issues creeped in when the resv_mem structure changed
On 09/11/2018 11:29, Eric Auger wrote:
> +#define SUPPORTED_PROBE_PROPERTIES (\
> +VIRTIO_IOMMU_PROBE_T_NONE | \
> +VIRTIO_IOMMU_PROBE_T_RESV_MEM)
You might be missing "1 <<" here, since the properties types are normal
On 09/11/2018 11:29, Eric Auger wrote:
> +static void create_virtio_iommu(VirtMachineState *vms,
> +const char *pciehb_nodename, PCIBus *bus)
> +{
> +const char compat[] = "virtio,pci-iommu";
> +uint16_t bdf = 0x8; /* 00:01.0 */
> +DeviceState *dev;
> +
On 09/11/2018 11:29, Eric Auger wrote:
> +static void virtio_iommu_register_resv_region(viommu_endpoint *ep,
> + uint8_t subtype,
> + uint64_t start, uint64_t end)
> +{
> +viommu_interval *interval;
> +
On 26/04/17 11:12, Liu, Yi L wrote:
> From: "Liu, Yi L"
>
> This patch adds VFIO_IOMMU_SVM_BIND_TASK for potential PASID table
> binding requests.
>
> On VT-d, this IOCTL cmd would be used to link the guest PASID page table
> to host. While for other vendors, it may also be used to support other
Hi Yi, Jacob,
On 26/04/17 11:11, Liu, Yi L wrote:
> From: Jacob Pan
>
> Virtual IOMMU was proposed to support Shared Virtual Memory (SVM) use
> case in the guest:
> https://lists.gnu.org/archive/html/qemu-devel/2016-11/msg05311.html
>
> As part of the proposed architecture, when a SVM capable P
On 26/04/17 19:29, jacob pan wrote:
> On Wed, 26 Apr 2017 17:56:45 +0100
> Jean-Philippe Brucker wrote:
>
>> Hi Yi, Jacob,
>>
>> On 26/04/17 11:11, Liu, Yi L wrote:
>>> From: Jacob Pan
>>>
>>> Virtual IOMMU was proposed to support Shared Vir
On 27/04/17 07:36, Liu, Yi L wrote:
> On Wed, Apr 26, 2017 at 05:56:45PM +0100, Jean-Philippe Brucker wrote:
>> Hi Yi, Jacob,
>>
>> On 26/04/17 11:11, Liu, Yi L wrote:
>>> From: Jacob Pan
>>>
>>> Virtual IOMMU was proposed to support Share
On 28/04/17 10:04, Liu, Yi L wrote:
> On Wed, Apr 26, 2017 at 05:56:45PM +0100, Jean-Philippe Brucker wrote:
>> Hi Yi, Jacob,
>>
>> On 26/04/17 11:11, Liu, Yi L wrote:
>>> From: Jacob Pan
>>>
>>> Virtual IOMMU was proposed to support Share
Hi Eric,
On 12/02/18 18:58, Eric Auger wrote:
[...]
> +for (;;) {
> +elem = virtqueue_pop(vq, sizeof(VirtQueueElement));
> +
> +if (!elem) {
> +virtio_error(vdev,
> + "no buffer available in event queue to report
> event");
> +re
ive IPA size for the given CD.
>
> However, this check was missing.
>
> There is already a similar check for stage-2 against effective PA.
>
> Reviewed-by: Eric Auger
> Signed-off-by: Mostafa Saleh
Reviewed-by: Jean-Philippe Brucker
> ---
> hw/arm/smmu-common.
rm/smmuv3: Add page table walk for stage-2”
> Reviewed-by: Eric Auger
> Signed-off-by: Mostafa Saleh
Reviewed-by: Jean-Philippe Brucker
> ---
> hw/arm/smmu-common.c | 10 ++
> hw/arm/smmuv3.c | 4
> 2 files changed, 10 insertions(+), 4 deletions(-)
>
On Mon, Jul 01, 2024 at 11:02:25AM +, Mostafa Saleh wrote:
> The SMMUv3 spec (ARM IHI 0070 F.b - 7.3 Event records) defines the
> class of events faults as:
>
> CLASS: The class of the operation that caused the fault:
> - 0b00: CD, CD fetch.
> - 0b01: TTD, Stage 1 translation table fetch.
> -
On Mon, Jul 01, 2024 at 11:02:29AM +, Mostafa Saleh wrote:
> Soon, smmuv3_do_translate() will be used to translate the CD and the
> TTBx, instead of re-writting the same logic to convert the returned
> cached entry to an address, add a new macro CACHED_ENTRY_TO_ADDR.
>
> Signed-off-by: Mostafa
On Mon, Jul 01, 2024 at 11:02:30AM +, Mostafa Saleh wrote:
> According to ARM SMMU architecture specification (ARM IHI 0070 F.b),
> In "5.2 Stream Table Entry":
> [51:6] S1ContextPtr
> If Config[1] == 1 (stage 2 enabled), this pointer is an IPA translated by
> stage 2 and the programmed valu
On Mon, Jul 01, 2024 at 11:02:31AM +, Mostafa Saleh wrote:
> In the next patch, combine_tlb() will be added which combines 2 TLB
> entries into one for nested translations, which chooses the granule
> and level from the smallest entry.
>
> This means that with nested translation, an entry can
ova that would be cached is recalculated.
>- Translated_addr is chosen from stage-2.
>
> Signed-off-by: Mostafa Saleh
Reviewed-by: Jean-Philippe Brucker
> ---
> hw/arm/smmu-common.c | 37
> include/hw/arm/smmu-common.h | 1 +
>
On Mon, Jul 01, 2024 at 11:02:33AM +, Mostafa Saleh wrote:
> When nested translation is requested, do the following:
>
> - Translate stage-1 table address IPA into PA through stage-2.
> - Translate stage-1 table walk output (IPA) through stage-2.
> - Create a single TLB entry from stage-1 and
On Mon, Jul 01, 2024 at 11:02:34AM +, Mostafa Saleh wrote:
> With nesting, we would need to invalidate IPAs without
> over-invalidating stage-1 IOVAs. This can be done by
> distinguishing IPAs in the TLBs by having ASID=-1.
> To achieve that, rework the invalidation for IPAs to have a
> separat
isn't bisectable.
Reviewed-by: Jean-Philippe Brucker
> ---
> hw/arm/smmu-common.c | 20 +---
> hw/arm/smmuv3.c | 2 +-
> include/hw/arm/smmu-common.h | 2 +-
> 3 files changed, 15 insertions(+), 9 deletions(-)
>
> diff --git
rted, otherwise
> invalidate everything, this required a new vmid invalidation
> function for stage-1 only (ASID >= 0)
>
> Also, rework trace events to reflect the new implementation.
>
> Signed-off-by: Mostafa Saleh
Reviewed-by: Jean-Philippe Brucker
> -
On Mon, Jul 01, 2024 at 11:02:37AM +, Mostafa Saleh wrote:
> IOMMUTLBEvent only understands IOVA, for stage-1 or stage-2
> SMMU instances we consider the input address as the IOVA, but when
> nesting is used, we can't mix stage-1 and stage-2 addresses, so for
> nesting only stage-1 is considere
(cfg)->record_faults) || \
> +((ptw_info).stage == SMMU_STAGE_2 &&
> \
> + (cfg)->s2cfg.record_faults))
I guess this could be simplified as "(info.stage == STAGE_1)
On Mon, Jul 01, 2024 at 11:02:39AM +, Mostafa Saleh wrote:
> Everything is in place, consolidate parsing of STE cfg and setting
> translation stage.
>
> Advertise nesting if stage requested is "nested".
>
> Signed-off-by: Mostafa Saleh
Reviewed-by: Jean-Philip
On Mon, Jul 01, 2024 at 11:02:40AM +, Mostafa Saleh wrote:
> QEMU doesn's support memory attributes, so FWB is NOP, this
> might change in the future if memory attributre would be supported.
>
> Signed-off-by: Mostafa Saleh
> ---
> hw/arm/smmuv3.c | 8
> 1 file changed, 8 insertions
o, it is easier just to change IDR5 and
> it propagages correctly.
> - Add additional checks when OAS is greater than 48bits.
> - Remove unused functions/macros: pa_range/MAX_PA.
>
> Reviewed-by: Eric Auger
> Signed-off-by: Mostafa Saleh
Reviewed-by: Jean-Philippe Brucker
Hi Mostafa,
On Tue, Jul 09, 2024 at 07:12:59AM +, Mostafa Saleh wrote:
> > In this case I think we're reporting InputAddr as the CD address, but it
> > should be the IOVA
>
> As Eric mentioned this would require some rework to propagate the iova,
> but what I am more worried about is the read
On Tue, Jul 09, 2024 at 07:14:19AM +, Mostafa Saleh wrote:
> Hi Jean,
>
> On Thu, Jul 04, 2024 at 07:12:35PM +0100, Jean-Philippe Brucker wrote:
> > On Mon, Jul 01, 2024 at 11:02:31AM +, Mostafa Saleh wrote:
> > > In the next patch, combine_tlb() will be ad
nested”, and
> advertised to guests as (IDR0.S1P == 1 && IDR0.S2P == 2)
For the whole series (3-9, 11, 12, 15, 16, 18):
Reviewed-by: Jean-Philippe Brucker
(and I think patch 16 is missing Eric's R-b)
Hi Eric,
On Wed, Jul 17, 2024 at 05:07:57PM +0200, Eric Auger wrote:
> Hi Jean,
>
> On 7/15/24 10:45, Mostafa Saleh wrote:
> > The SMMUv3 spec (ARM IHI 0070 F.b - 7.3 Event records) defines the
> > class of events faults as:
> >
> > CLASS: The class of the operation that caused the fault:
> > - 0
On Wed, Mar 04, 2020 at 09:41:44AM +0100, Auger Eric wrote:
> >>> Could I ask one question?
> >>> To support vSVA and pasid in guest, which direction you recommend,
> >>> virtio-iommu or vSMMU (your nested paging)
> >>>
> >>> Do we still have any obstacles?
> >> you can ask the question but not sur
On Thu, Mar 05, 2020 at 02:56:20AM +, Tian, Kevin wrote:
> > From: Jean-Philippe Brucker
> > Sent: Thursday, March 5, 2020 12:47 AM
> >
> [...]
> > > >
> > > > * We can't use DVM in nested mode unless the VMID is shared with the
> > &
Hi Bharat,
A few more things found while rebasing
On Mon, Mar 23, 2020 at 02:16:16PM +0530, Bharat Bhushan wrote:
> This patch implements the PROBE request. Currently supported
> page size mask per endpoint is returned. Also append a NONE
> property in the end.
>
> Signed-off-by: Bharat Bhushan
On Mon, Jul 27, 2020 at 11:14:03AM +0100, Stefan Hajnoczi wrote:
> On Tue, Jul 21, 2020 at 11:49:04AM +0100, Alex Bennée wrote:
> > Stefan Hajnoczi writes:
> > > 2. Alexander Graf's idea for a new Linux driver that provides an
> > > enforcing software IOMMU. This would be a character device driver
On Wed, Jun 24, 2020 at 09:47:59AM -0400, Michael S. Tsirkin wrote:
> On Wed, Jun 24, 2020 at 03:26:20PM +0200, Eric Auger wrote:
> > By default the virtio-iommu translates MSI transactions. This
> > behavior is inherited from ARM SMMU. However the virt machine
> > code knows where the MSI doorbell
k=0x4)
Fix the page mask.
Signed-off-by: Jean-Philippe Brucker
---
hw/i386/amd_iommu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 74a93a5d93f..43b6e9bf510 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386/amd_iommu.c
@
On Fri, Apr 23, 2021 at 02:01:19PM +0100, Peter Maydell wrote:
> On Thu, 22 Apr 2021 at 23:24, Michael S. Tsirkin wrote:
> >
> > From: Jean-Philippe Brucker
> >
> > AMD IOMMU PTEs have a special mode allowing to specify an arbitrary page
> > size. Quoting the A
On Fri, Apr 23, 2021 at 05:11:33PM +0100, Peter Maydell wrote:
> > > Jean-Philippe, do you know if this is a regression since 5.2?
> >
> > I don't think so, I can reproduce it with v5.2.0.
>
> OK, thanks; I think I favour not putting this into rc5, then.
No problem, please let me know if I should
On Sun, Feb 21, 2021 at 06:45:18AM -0500, Michael S. Tsirkin wrote:
> On Thu, Feb 18, 2021 at 11:59:30AM +0100, Jean-Philippe Brucker wrote:
> > Currently the virtio-iommu device must be programmed before it allows
> > DMA from any PCI device. This can make the VM entirely
On Fri, Feb 26, 2021 at 08:11:41AM +, Tian, Kevin wrote:
> > From: Qemu-devel
> > On Behalf Of Jean-Philippe Brucker
> >
> > On Sun, Feb 21, 2021 at 06:45:18AM -0500, Michael S. Tsirkin wrote:
> > > On Thu, Feb 18, 2021 at 11:59:30AM +0100, Jean-Philippe Bru
On Mon, Oct 19, 2020 at 05:35:39PM -0400, Peter Xu wrote:
> > +/*
> > + * Disallow shrinking the page size. For example if an endpoint only
> > + * supports 64kB pages, we can't globally enable 4kB pages. But that
> > + * shouldn't happen, the host is unlikely to setup differing pag
On Fri, Oct 16, 2020 at 09:58:28AM +0200, Auger Eric wrote:
> > +static void virtio_iommu_notify_map(IOMMUMemoryRegion *mr, hwaddr
> > virt_start,
> > +hwaddr virt_end, hwaddr paddr)
> > +{
> > +IOMMUTLBEntry entry;
> > +IOMMUNotifierFlag flags = mr->iom
On Fri, Oct 16, 2020 at 11:12:35AM +0200, Auger Eric wrote:
> > +static gboolean virtio_iommu_remap(gpointer key, gpointer value, gpointer
> > data)
> > +{
> > +VirtIOIOMMUMapping *mapping = (VirtIOIOMMUMapping *) value;
> > +VirtIOIOMMUInterval *interval = (VirtIOIOMMUInterval *) key;
> >
On Fri, Oct 16, 2020 at 11:24:08AM +0200, Auger Eric wrote:
> > +/*
> > + * Set supported IOMMU page size
> > + *
> > + * If supported, allows to restrict the page size mask that can be
> > supported
> To match other docs: Optional method:
> > + * with a given IOMMU memory regi
On Fri, Oct 16, 2020 at 03:08:03PM +0200, Auger Eric wrote:
> > +static int virtio_iommu_set_page_size_mask(IOMMUMemoryRegion *mr,
> > + uint64_t page_size_mask,
> > + Error **errp)
> > +{
> > +int new_granule,
On Thu, Oct 22, 2020 at 04:56:16PM -0400, Peter Xu wrote:
> On Thu, Oct 22, 2020 at 06:39:37PM +0200, Jean-Philippe Brucker wrote:
> > So what I'd like to do for next version:
> >
> > * Set qemu_real_host_page_mask as the default page mask, instead of the
> > r
On Fri, Oct 23, 2020 at 12:47:02PM -0400, Peter Xu wrote:
> On Fri, Oct 23, 2020 at 09:48:58AM +0200, Jean-Philippe Brucker wrote:
> > Arm CPUs and SMMU support 4k, 16k and 64k page sizes. I don't think 16k is
> > used anywhere but some distributions chose 64k (RHEL, I think?
o DMA bypassing
the IOMMU during boot. Add a "boot-bypass" option that lets users change
this behavior.
Signed-off-by: Jean-Philippe Brucker
---
include/hw/virtio/virtio-iommu.h | 1 +
hw/virtio/virtio-iommu.c | 23 +--
2 files changed, 22 insertions(
Hi Eric,
On Tue, Jul 30, 2019 at 07:21:28PM +0200, Eric Auger wrote:
> static void virtio_iommu_device_unrealize(DeviceState *dev, Error **errp)
> {
> VirtIODevice *vdev = VIRTIO_DEVICE(dev);
> +VirtIOIOMMU *s = VIRTIO_IOMMU(dev);
> +
> +g_tree_destroy(s->domains);
> +g_tree_des
On Thu, May 07, 2020 at 04:32:01PM +0200, Eric Auger wrote:
> At the moment the virtio-iommu translates MSI transactions.
> This behavior is inherited from ARM SMMU. The virt machine
> code knows where the guest MSI doorbells are so we can easily
> declare those regions as VIRTIO_IOMMU_RESV_MEM_T_M
On Thu, May 07, 2020 at 04:31:58PM +0200, Eric Auger wrote:
> +static ssize_t virtio_iommu_fill_resv_mem_prop(VirtIOIOMMU *s, uint32_t ep,
> + uint8_t *buf, size_t free)
> +{
> +struct virtio_iommu_probe_resv_mem prop = {};
> +size_t size = size
Hi Bharat,
Could you Cc me on your next posting? Unfortunately I don't have much
hardware for testing this at the moment, but I might be able to help a
little on the review.
On Mon, Mar 16, 2020 at 02:40:00PM +0530, Bharat Bhushan wrote:
> > >>> First issue is: your guest can use 4K page and you
On Tue, Mar 17, 2020 at 12:40:39PM +0530, Bharat Bhushan wrote:
> Hi Jean,
>
> On Mon, Mar 16, 2020 at 3:41 PM Jean-Philippe Brucker
> wrote:
> >
> > Hi Bharat,
> >
> > Could you Cc me on your next posting? Unfortunately I don't have much
> > hardw
On Tue, Mar 17, 2020 at 02:46:55PM +0530, Bharat Bhushan wrote:
> Hi Jean,
>
> On Tue, Mar 17, 2020 at 2:23 PM Jean-Philippe Brucker
> wrote:
> >
> > On Tue, Mar 17, 2020 at 12:40:39PM +0530, Bharat Bhushan wrote:
> > > Hi Jean,
> > >
> > > On
On Wed, Mar 18, 2020 at 03:47:44PM +0530, Bharat Bhushan wrote:
> Hi Jean,
>
> On Tue, Mar 17, 2020 at 9:29 PM Jean-Philippe Brucker
> wrote:
> >
> > On Tue, Mar 17, 2020 at 02:46:55PM +0530, Bharat Bhushan wrote:
> > > Hi Jean,
> > >
> > > On
On Wed, Mar 18, 2020 at 12:42:25PM +0100, Auger Eric wrote:
> Hi Jean,
>
> On 3/18/20 12:20 PM, Bharat Bhushan wrote:
> >
> >
> >> -Original Message-
> >> From: Jean-Philippe Brucker
> >> Sent: Wednesday, March 18, 2020 4:48 PM
>
On Fri, May 08, 2020 at 07:30:57PM +0200, Eric Auger wrote:
> At the moment the virtio-iommu translates MSI transactions.
> This behavior is inherited from ARM SMMU. The virt machine
> code knows where the guest MSI doorbells are so we can easily
> declare those regions as VIRTIO_IOMMU_RESV_MEM_T_M
On Wed, Jan 08, 2020 at 05:55:52PM +0100, Auger Eric wrote:
> Hi Jean-Philippe, Peter,
>
> On 1/7/20 11:10 AM, Jean-Philippe Brucker wrote:
> > On Mon, Jan 06, 2020 at 12:58:50PM -0500, Peter Xu wrote:
> >> On Mon, Jan 06, 2020 at 06:06:34PM +0100, Jean-Philippe Brucker
On Thu, Jan 09, 2020 at 09:58:49AM +0100, Auger Eric wrote:
> >> I share Peter's concern about having a different default policy than x86.
> >
> > Yes I'd say just align with whatever policy is already in place. Do you
> > think we could add a command-line option to let people disable
> > default-
On Thu, Jan 09, 2020 at 12:01:26PM +0100, Auger Eric wrote:
> Hi,
>
> On 1/9/20 11:40 AM, Jean-Philippe Brucker wrote:
> > On Thu, Jan 09, 2020 at 09:58:49AM +0100, Auger Eric wrote:
> >>>> I share Peter's concern about having a different default policy tha
On Thu, Dec 19, 2019 at 04:09:47PM +0100, Auger Eric wrote:
> >> @@ -412,19 +412,80 @@ static IOMMUTLBEntry
> >> virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr,
> >> int iommu_idx)
> >> {
> >> IOMMUDevice *sdev = con
On Thu, Dec 19, 2019 at 07:31:08PM +0100, Auger Eric wrote:
> Hi Jean,
>
> On 12/10/19 5:37 PM, Jean-Philippe Brucker wrote:
> > On Fri, Nov 22, 2019 at 07:29:28PM +0100, Eric Auger wrote:
> >> +typedef struct viommu_domain {
> >> +uint32_t id;
> >>
On Fri, Dec 20, 2019 at 11:51:00AM -0500, Peter Xu wrote:
> On Fri, Dec 20, 2019 at 05:26:42PM +0100, Jean-Philippe Brucker wrote:
> > There is at the virtio transport level: the driver sets status to
> > FEATURES_OK once it accepted the feature bits, and to DRIVER_OK onc
On Mon, Jan 06, 2020 at 12:58:50PM -0500, Peter Xu wrote:
> On Mon, Jan 06, 2020 at 06:06:34PM +0100, Jean-Philippe Brucker wrote:
> > On Fri, Dec 20, 2019 at 11:51:00AM -0500, Peter Xu wrote:
> > > On Fri, Dec 20, 2019 at 05:26:42PM +0100, Jean-Philippe Brucker wrote:
>
On Tue, Aug 17, 2021 at 04:11:49PM +0200, Eric Auger wrote:
> Hi Jean,
>
> On 8/10/21 10:45 AM, Jean-Philippe Brucker wrote:
> > From: Eric Auger
> >
> > Add a hotplug handler for virtio-iommu on x86 and set the necessary
> > reserved region property. On x86,
On Tue, Aug 17, 2021 at 03:42:22PM +0200, Eric Auger wrote:
> > diff --git a/hw/virtio/virtio-iommu-pci.c b/hw/virtio/virtio-iommu-pci.c
> > index 770c286be7..f30eb16cbf 100644
> > --- a/hw/virtio/virtio-iommu-pci.c
> > +++ b/hw/virtio/virtio-iommu-pci.c
> > @@ -48,16 +48,9 @@ static void virtio_io
On Tue, Aug 10, 2021 at 11:22:27AM +0200, Igor Mammedov wrote:
> On Tue, 10 Aug 2021 10:45:02 +0200
> Jean-Philippe Brucker wrote:
>
> > Add a function that generates a Virtual I/O Translation table (VIOT),
> > describing the topology of paravirtual IOMMUs. The
Hi Eric,
On Tue, Aug 17, 2021 at 04:58:01PM +0200, Eric Auger wrote:
> Hi Jean,
>
> On 8/10/21 10:45 AM, Jean-Philippe Brucker wrote:
> > Allow instantiating a virtio-iommu device on ACPI systems by adding a
> > Virtual I/O Translation table (VIOT). Enable x86 support for
ply ignore
spurious EOIR writes.
Fixes: 382c7160d1cd ("hw/intc/arm_gicv3_cpuif: Fix EOIR write access check
logic")
Signed-off-by: Jean-Philippe Brucker
---
hw/intc/arm_gicv3_cpuif.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/in
On Thu, Jun 03, 2021 at 02:39:30PM +0200, Philippe Mathieu-Daudé wrote:
> > diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
> > index 81f94c7f4a..1d0964c9bf 100644
> > --- a/hw/intc/arm_gicv3_cpuif.c
> > +++ b/hw/intc/arm_gicv3_cpuif.c
> > @@ -1357,7 +1357,8 @@ static void icc_eo
Display a guest error and tolerate spurious EOIR writes.
Fixes: 382c7160d1cd ("hw/intc/arm_gicv3_cpuif: Fix EOIR write access check
logic")
Signed-off-by: Jean-Philippe Brucker
---
v2: Added qemu_log_mask() (so I didn't keep the Reviewed-by tag)
v1:
https://lore.kernel.org/qemu-devel
pc: Allow instantiating a virtio-iommu device
Jean-Philippe Brucker (5):
acpi: Add VIOT structure definitions
hw/acpi: Add VIOT table
hw/arm/virt-acpi-build: Add VIOT table for virtio-iommu
hw/arm/virt: Remove device tree restriction for virtio-iommu
pc: Add VIOT table for virtio-iommu
hw/a
The ACPI Virtual I/O Translation table (VIOT) describes the relation
between a virtio-iommu and the endpoints it manages. When a virtio-iommu
device is instantiated, add a VIOT table.
Signed-off-by: Jean-Philippe Brucker
---
include/hw/i386/pc.h | 2 ++
hw/i386/acpi-build.c | 5 +
hw/i386
The ACPI Virtual I/O Translation table (VIOT) table describes I/O
topology for paravirtual devices. At the moment it describes the
relation between virtio-iommu devices and their endpoints. Add the
structure definitions for VIOT.
Signed-off-by: Jean-Philippe Brucker
---
Following the latest spec
virtio-iommu does not support IRQ remapping it must be informed
of the reserved region so that it can forward DMA transactions targeting
this region.
Signed-off-by: Eric Auger
Signed-off-by: Jean-Philippe Brucker
---
hw/i386/pc.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion
virtio-iommu is now supported with ACPI VIOT as well as device tree.
Remove the restriction that prevents from instantiating a virtio-iommu
device under ACPI.
Signed-off-by: Jean-Philippe Brucker
---
hw/arm/virt.c| 10 ++
hw/virtio/virtio-iommu-pci.c | 7 ---
2
describes all PCI devices. When passing the "default_bus_bypass_iommu"
machine option and "bypass_iommu" PXB option, only buses that do not
bypass the IOMMU are described by PCI Range nodes.
Signed-off-by: Jean-Philippe Brucker
---
hw/acpi/viot.h | 13 +++
hw/a
When a virtio-iommu is instantiated, describe it using the ACPI VIOT
table.
Signed-off-by: Jean-Philippe Brucker
---
hw/arm/virt-acpi-build.c | 7 +++
hw/arm/Kconfig | 1 +
2 files changed, 8 insertions(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index
ehavior by explicitly checking for aliases of these options instead of
transforming all machine options.
Fixes: d8fb7d0969d5 ("vl: switch -M parsing to keyval")
Signed-off-by: Jean-Philippe Brucker
---
My first take was renaming default_bus_bypass_iommu, since it's the only
machine o
the underscore are
transformed automatically.
Fixes: 6d7a85483a06 ("hw/arm/virt: Add default_bus_bypass_iommu machine option")
Signed-off-by: Jean-Philippe Brucker
---
hw/arm/virt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
the underscore are
transformed automatically.
Fixes: c9e96b04fc19 ("hw/i386: Add a default_bus_bypass_iommu pc machine
option")
Signed-off-by: Jean-Philippe Brucker
---
hw/i386/pc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index fb
this region.
Signed-off-by: Jean-Philippe Brucker
---
include/hw/i386/pc.h | 2 ++
hw/i386/acpi-build.c | 5 +
hw/i386/pc.c | 28 +++-
hw/i386/Kconfig | 1 +
4 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/include/hw/i386/pc.h b/include
virtio-iommu is now supported with ACPI VIOT as well as device tree.
Remove the restriction that prevents from instantiating a virtio-iommu
device under ACPI.
Reviewed-by: Eric Auger
Signed-off-by: Jean-Philippe Brucker
---
hw/arm/virt.c| 10 ++
hw/virtio/virtio-iommu
describes all PCI devices. When passing the "default_bus_bypass_iommu"
machine option and "bypass_iommu" PXB option, only buses that do not
bypass the IOMMU are described by PCI Range nodes.
Signed-off-by: Jean-Philippe Brucker
---
Sizes and types are hardcoded because it will now
Create empty data files and allow updates for the upcoming VIOT tests.
Signed-off-by: Jean-Philippe Brucker
---
tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
tests/data/acpi/q35/DSDT.viot | 0
tests/data/acpi/q35/VIOT.viot | 0
tests/data/acpi/virt/VIOT
[068h 0104 2] Output node : 0030
[06Ah 0106 6] Reserved : 00000000
Signed-off-by: Jean-Philippe Brucker
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
tests/data/acpi/q35/VIOT.viot | Bin 0 -> 112 bytes
2 files changed, 1 deleti
301 - 400 of 503 matches
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