Add SDHCI model for AST2700 SDHCI support. The SDHCI controller only support 1
slot and registers base address is start at 0x1408_ and its interrupt is
connected to GICINT133_INTC at bit 1.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed_ast27x0.c | 20 +
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/sd/aspeed_sdhci.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c
index 98d5460905..acd6538261 100644
--- a/hw/sd/aspee
Currently, it set the hardcode value of capability registers to all ASPEED SOCs
However, the value of capability registers should be different for all ASPEED
SOCs. For example: the bit 28 of the Capability Register 1 should be 1 for
64-bits System Bus support for AST2700.
Introduce a new "capareg"
Add SDHCI model for AST2700 eMMC support. The eMMC controller only support 1
slot and registers base address is start at 0x1209_ and its interrupt is
connected to GICINT 15.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed_ast27x0.c | 15 +++
1 file chang
Add SDHCI model for AST2700 eMMC support. The eMMC controller only support 1
slot and registers base address is start at 0x1209_ and its interrupt is
connected to GICINT 15.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 15 +++
1 file changed, 15 insertions(+)
diff --gi
Currently, it set the hardcode value of capability registers to all ASPEED SOCs
However, the value of capability registers should be different for all ASPEED
SOCs. For example: the bit 28 of the Capability Register 1 should be 1 for
64-bits System Bus support for AST2700.
Introduce a new "capareg"
Add SDHCI model for AST2700 SDHCI support. The SDHCI controller only support 1
slot and registers base address is start at 0x1408_ and its interrupt is
connected to GICINT133_INTC at bit 1.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 20
1 file changed, 20 ins
change from v1:
This patch series do not support boot from an eMMC.
Only support eMMC and SD Slot 0 as storages.
change from v2:
- Add hw/sd/aspeed_sdhci: Fix coding style patch
change from v3:
- Directly set capareg and sd_spec_version instead of property
- Keep DEFINE_TYPES
Jamin Lin (7):
hw
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin
---
hw/sd/aspeed_sdhci.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c
index 98d5460905..acd6538261 100644
--- a/hw/sd/aspeed_sdhci.c
+++ b/hw/sd/aspeed_sd
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast2600.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index be3eb70cdd..c40d3d8443 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/
Introduce a new ast2700 class to support AST2700. Add a new ast2700 SDHCI class
init function and set the value of capability register to "0x000719f80080".
Signed-off-by: Jamin Lin
---
hw/sd/aspeed_sdhci.c | 16 ++--
include/hw/sd/aspeed_sdhci.h | 1 +
2 files changed, 1
Directly set sd_spec_version instead of property and remove
unused local variable.
Signed-off-by: Jamin Lin
---
hw/sd/aspeed_sdhci.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c
index ccaeefa75b..4e64e2537a 100644
--- a/hw/s
QEMU supports GICv3 Non-maskable Interrupt, adds to support Non-maskable
Interrupt for AST2700.
Reference:
https://github.com/qemu/qemu/commit/b36a32ead
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/
Currently, these trace events only refer to INTC. To simplify the INTC model,
both INTC(CPU Die) and INTC_IO(IO Die) will share the same helper functions.
However, it is difficult to recognize whether these trace events are comes from
INTC or INTC_IO. To make these trace events more readable, adds
The behavior of the enable and status registers is almost identical between
INTC(CPU Die) and INTC_IO(IO Die). To reduce duplicated code, adds
"aspeed_intc_enable_handler" functions to handle enable register write
behavior and "aspeed_intc_status_handler" functions to handle status
register write b
To improve readability, sort the IRQ table by IRQ number.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 50 -
1 file changed, 25 insertions(+), 25 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 39567fcab9..6a848
The previous implementation set the "aspeed_intc_ops" struct, containing read
and write callbacks, to be used when I/O is performed on the INTC region.
Both "aspeed_intc_read" and "aspeed_intc_write" callback functions were used
for INTC (CPU Die).
To support the INTC_IO (IO Die) model, introduces
According to the AST2700 datasheet, the INTC (CPU DIE) controller has 16KB
(0x4000) of register space, and the INTC_IO (I/O DIE) controller has 1KB (0x400)
of register space.
Introduced a new class attribute "mem_size" to set different memory sizes for
the INTC models in AST2700.
Introduced a new
v2:
To streamline the review process, split the following patch series into
three parts.
https://patchwork.kernel.org/project/qemu-devel/cover/20250121070424.2465942-1-jamin_...@aspeedtech.com/
This patch series focuses on cleaning up the INTC model to
facilitate future support for the I
Currently, AST2700 SoC only supports A0. To support AST2700 A1, rename its IRQ
table and machine name.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed.c | 8
hw/arm/aspeed_ast27x0.c | 8
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/
How to reproduce it:
1. The value of "s->blksie" was 0x7200. The bits[14:12] was "111", so the buffer
boundary was 0x8.(512Kbytes). This SDMA buffer boundary the same as
u-boot default value.
The bit[11:0] is "0010", so the block size is 0x200.(512bytes)
2. The SDMA address was
According to the design of sdhci_sdma_transfer_multi_blocks, if the
"s->blkcnt * 512" was bigger than the SDMA Buffer boundary, it breaked the
while loop of data transfer and set SDHC_NISEN_DMA in the normal interreupt
status to notify the firmware that this SDMA boundary buffer Transfer Complete
a
v1:
1. Fix boundary_count overflow
2. Fix data transfer did not complete if data size is bigger then SDMA Buffer
Boundary
Jamin Lin (2):
RFC:sd:sdhci: Fix boundary_count overflow in
sdhci_sdma_transfer_multi_blocks
RFC:sd:sdhci: Fix data transfer did not complete if data size is
bigge
Add Timer model for AST2700 Timer support. The Timer controller include 8 sets
of 32-bit decrement counters.
The base address of TIMER0 to TIMER7 as following.
Base Address of Timer 0 = 0x12C1_
Base Address of Timer 1 = 0x12C1_0040
Base Address of Timer 2 = 0x12C1_0080
Base Address of Timer 3
The timer controller include 8 sets of 32-bit decrement counters, based on
either PCLK or 1MHZ clock and the design of timer controller between AST2600
and AST2700 are almost the same.
The different is that the register set have a significant change in AST2700.
TIMER0 – TIMER7 has their own indivi
It set "aspeed_timer_ops" struct which containing read and write callbacks
to be used when I/O is performed on the TIMER region.
Besides, in the previous design of ASPEED SOCs, the timer registers address
space are contiguous.
ex: TMC00-TMC0C are used for TIMER0.
ex: TMC10-TMC1C are used for TIME
v1:
- Support timer for AST2700
- Introduce new "aspeed_2700_timer_read" and "aspeed_2700_timer_write"
callback functions and "aspeed_2700_timer_ops" memory
region operation for AST2700.
Introduce a new ast2700 class to support AST2700.
Jamin Lin (3):
hw/timer/aspeed: Support dif
v1:
1. Fix boundary_count overflow
2. Fix data transfer did not complete if data size is bigger then SDMA Buffer
Boundary
v2:
1. fix typo
2. update to none RFC patch
3. check the most upper byte of SDMA System Address Register (0x00) is written,
then restarts SDMA data transfer.
Jamin Lin (2)
How to reproduce it:
1. The value of "s->blksie" was 0x7200. The bits[14:12] was "111", so the buffer
boundary was 0x8.(512Kbytes). This SDMA buffer boundary was the same as
u-boot default value.
The bit[11:0] was "0010", so the block size was 0x200.(512bytes)
2. The SDMA addre
According to the design of sdhci_sdma_transfer_multi_blocks, if the
"s->blkcnt * 512" was bigger than the SDMA Buffer boundary, it break the
while loop of data transfer and set SDHC_NISEN_DMA in the normal interrupt
status to notify the firmware that this SDMA boundary buffer Transfer Complete
and
The INTC0 controller supports GICINT128 to GICINT136, mapping 1:1 to input and
output IRQs 0 to 8. Previously, the formula "address & 0x0f00" was used to
derive the IRQ index numbers.
However, the INTC0 controller also supports GICINT192_201, mapping 1 input IRQ
pin to 10 output IRQ pins. The pin
The design of the INTC has significant changes in the AST2700 A1. In the
AST2700 A0, there was one INTC controller, whereas in the AST2700 A1,
there were two INTC controllers: INTC0 (CPU DIE) and INTC1 (I/O DIE).
The previous INTC model only supported the AST2700 A0 and was implemented for
the INT
Currently, it does not support the CRYPT command.
Instead, it only sends an interrupt to notify the firmware
that the crypt command has completed.
It is a temporary workaround to resolve the boot issue in
the Crypto Manager Self Test.
Full support for the CRYPT command will be implemented in the fu
Introduce a new ast2700 INTC1 class to support AST2700 INTC1.
Added new register definitions for INTC1, including enable and status registers
for IRQs GICINT192 through GICINT197.
Created a dedicated IRQ array for INTC1, supporting six input pins and six
output pins, aligning with the newly defined
Added new definitions for AST2700_A1_SILICON_REV and AST2750_A1_SILICON_REV to
identify the A1 silicon revisions.
Update "aspeed_ast2700_scu_reset" to set the silicon_rev field in the SCU
registers.
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_scu.c | 3 +++
include/hw/misc/aspeed_scu.h
The design of INTC controllers has significantly changed in AST2700 A1.
There are a total of 480 interrupt sources in AST2700 A1. For interrupt numbers
from 0 to 127, they can route directly to PSP, SSP, and TSP. Due to the
limitation of interrupt numbers of processors, the interrupts are merged e
This update introduces support for handling multi-output IRQs in the AST2700
interrupt controller (INTC), specifically for GICINT192_201. GICINT192_201 maps
1:10 to input IRQ 0 and output IRQs 0 to 9. Each status bit corresponds to a
specific IRQ.
Implemented "aspeed_intc_set_irq_handler_multi_out
According to the AST2700 datasheet, the INTC0 (CPU DIE) controller has 16KB
(0x4000) of register space, and the INTC1 (I/O DIE) controller has 1KB (0x400)
of register space.
Introduced a new class attribute "mem_size" to set different memory sizes for
the INTC models in AST2700.
Introduced a new
The HACE controller between AST2600 and AST2700 are almost identical.
The HACE controller registers base address starts at 0x1207_ and
its alarm interrupt is connected to GICINT4.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 15 +++
1 file changed, 15 insertions(+)
dif
The memory map for AST2700 A1 remains compatible with AST2700 A0.
However, the IRQ mapping has been updated for AST2700 A1, with GIC interrupts
now ranging from 192 to 201. Add a new IRQ map table for AST2700 A1.
Introduce "aspeed_machine_ast2700_evb_class_init" to initialize the AST2700 EVB
machi
Currently, it is difficult to recognize whether these trace events are from
INTC0 or INTC1. To make these trace events more readable, add an ID to the
INTC trace events.
Updated trace events to include the "id" field for better identification.
Updated the "AspeedINTCClass" structure to include an "
The behavior of the INTC set IRQ is almost identical between INTC0 and INTC1.
To reduce duplicated code, introduce the `aspeed_intc_set_irq_handler` function
to handle both INTC0 and INTC1 IRQ behavior.
Signed-off-by: Jamin Lin
---
hw/intc/aspeed_intc.c | 56 +++--
Currently, AST2700 SoC only supports A0. To support AST2700 A1, rename its IRQ
table and machine name.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed.c | 8
hw/arm/aspeed_ast27x0.c | 8
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/
v1:
1. Refactor INTC model to support both INTC0 and INTC1.
2. Support AST2700 A1.
3. Create ast2700a0-evb machine.
With the patch applied, QEMU now supports two machines for running AST2700 SoCs:
ast2700a0-evb: Designed for AST2700 A0
ast2700-evb: Designed for AST2700 A1
Test information
1.
The previous implementation set the "aspeed_intc_ops" struct, containing read
and write callbacks, to be used when I/O is performed on the INTC region.
Both "aspeed_intc_read" and "aspeed_intc_write" callback functions were used
for INTC0 (CPU DIE).
To support the INTC1 (I/O DIE) model, introduces
Rename "aspeed_intc_read" to "aspeed_2700_intc0_read" and "aspeed_intc_write" to
"aspeed_2700_intc0_write".
Introduce a new memory region operation, "aspeed_2700_intc0_ops", for the
AST2700 INTC0 model.
Signed-off-by: Jamin Lin
---
hw/intc/aspeed_intc.c | 20 +++-
1 file changed
Introduce a new ast2700 class to support AST2700.
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_hace.c | 20
include/hw/misc/aspeed_hace.h | 1 +
2 files changed, 21 insertions(+)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index 18b85081c7..86422cb3be
The behavior of the enable and status registers is almost identical between
INTC0 and INTC1. To reduce duplicated code, adds
"aspeed_2700_intc_enable_handler" functions to handle enable register write
behavior and "aspeed_2700_intc_status_handler" functions to handle status
register write behavior.
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_hace.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index e3f7df2e86..18b85081c7 100644
--- a/hw/misc/aspeed_hace.c
+++ b/hw/m
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin
---
hw/watchdog/wdt_aspeed.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
index 81f5c5189a..22e94e7b9c 100644
--- a/hw/watchdog/wdt_aspeed.c
+++ b/hw/
On the AST2400 and AST2500 platforms, the system can only be reset by enabling
the WDT (Watchdog Timer) and waiting for the WDT timeout. However, starting
from the AST2600 platform, the reset event can be triggered directly and
intentionally by software, without relying on the WDT timeout.
This me
v1:
Support software reset mode for AST2600
Jamin Lin (2):
aspeed/wdt: Fix coding style
aspeed/wdt: Support software reset mode for AST2600
hw/watchdog/wdt_aspeed.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
--
2.34.1
v1:
Support software reset mode for AST2600
v2:
Change to validate WDT_CTRL_RESET_MODE_SOC
Jamin Lin (2):
aspeed/wdt: Fix coding style
aspeed/wdt: Support software reset mode for AST2600
hw/watchdog/wdt_aspeed.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
On the AST2400 and AST2500 platforms, the system can only be reset by enabling
the WDT (Watchdog Timer) and waiting for the WDT timeout. However, starting
from the AST2600 platform, the reset event can be triggered directly and
intentionally by software, without relying on the WDT timeout.
This me
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/watchdog/wdt_aspeed.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
index 81f5c5189a..22e94e7b9c 100644
--- a/hw/
v1:
- Support timer for AST2700
- Introduce new "aspeed_2700_timer_read" and "aspeed_2700_timer_write"
callback functions and "aspeed_2700_timer_ops" memory
region operation for AST2700.
Introduce a new ast2700 class to support AST2700.
v2:
Refactor Timer Callbacks for SoC-Sp
Add Timer model for AST2700 Timer support. The Timer controller include 8 sets
of 32-bit decrement counters.
The base address of TIMER0 to TIMER7 as following.
Base Address of Timer 0 = 0x12C1_
Base Address of Timer 1 = 0x12C1_0040
Base Address of Timer 2 = 0x12C1_0080
Base Address of Timer 3
The register set have a significant change in AST2700. The TMC00-TMC3C
are used for TIMER0 and TMC40-TMC7C are used for TIMER1. In additional,
TMC20-TMC3C and TMC60-TMC7C are reserved registers for TIMER0 and TIMER1,
respectively.
Besides, each TIMER has their own control and interrupt status regi
The timer controller include 8 sets of 32-bit decrement counters, based on
either PCLK or 1MHZ clock and the design of timer controller between AST2600
and AST2700 are almost the same.
TIMER0 – TIMER7 has their own individual control and interrupt status register.
In other words, users are able to
The design of INTC controllers has significantly changed in AST2700 A1.
There are a total of 480 interrupt sources in AST2700 A1. For interrupt numbers
from 0 to 127, they can route directly to PSP, SSP, and TSP. Due to the
limitation of interrupt numbers of processors, the interrupts are merged e
Added support for multiple output pins in the INTC controller to
accommodate the AST2700 A1.
Introduced "num_outpins" to represent the number of output pins. Updated the
IRQ handling logic to initialize and connect output pins separately from input
pins. Modified the "aspeed_soc_ast2700_realize" f
Currently, AST2700 SoC only supports A0. To support AST2700 A1, rename its IRQ
table and machine name.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed.c | 8
hw/arm/aspeed_ast27x0.c | 8
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/
This method simplifies the process of fetching and extracting assets from the
Aspeed GitHub repository.
Signed-off-by: Jamin Lin
---
tests/functional/test_aarch64_aspeed.py | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/tests/functional/test_aarch64_aspeed.py
b/tes
Added a new method `start_ast2700_test` to the `AST2x00MachineSDK` class and
this method centralizes the logic for starting the AST2700 test, making it
reusable for different test cases.
Modified the hwmon path to use a wildcard to handle different SDK versions:
"cat /sys/bus/i2c/devices/1-004d/hw
Currently, these trace events only refer to INTC. To simplify the INTC model,
both INTC(CPU Die) and INTCIO(IO Die) will share the same helper functions.
However, it is difficult to recognize whether these trace events are comes from
INTC or INTCIO. To make these trace events more readable, adds o
Refactors the INTC to distinguish between input and output pin indices,
improving interrupt handling clarity and accuracy.
Updated the functions to handle both input and output pin indices.
Added detailed logging for input and output pin indices in trace events.
These changes ensure that the INTC
Introduce a new ast2700 class to support AST2700.
Signed-off-by: Jamin Lin
Reviewed-by: Andrew Jeffery
---
hw/misc/aspeed_hace.c | 20
include/hw/misc/aspeed_hace.h | 1 +
2 files changed, 21 insertions(+)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
Add AST2700 INTC design guidance and its block diagram.
Signed-off-by: Jamin Lin
---
docs/specs/aspeed-intc.rst | 136 +
docs/specs/index.rst | 1 +
2 files changed, 137 insertions(+)
create mode 100644 docs/specs/aspeed-intc.rst
diff --git a/docs/sp
To improve readability, sort the IRQ table by IRQ number.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 50 -
1 file changed, 25 insertions(+), 25 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 6e3375f5d3..4862b
The HACE controller between AST2600 and AST2700 are almost identical.
The HACE controller registers base address starts at 0x1207_ and
its alarm interrupt is connected to GICINT4.
Signed-off-by: Jamin Lin
Reviewed-by: Andrew Jeffery
---
hw/arm/aspeed_ast27x0.c | 15 +++
1 file c
Currently, it does not support the CRYPT command. Instead, it only sends an
interrupt to notify the firmware that the crypt command has completed.
It is a temporary workaround to resolve the boot issue in the Crypto Manager
Self Test.
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_hace.c | 12 +
Currently, these IRQ tables support from GIC 128 - 136 for AST2700 A0.
These IRQ tables can be reused for AST2700 A1 from GIC 192 - 197.
Updates the interrupt mapping to include support for AST2700 A1 by extending
the existing mappings to the new GIC range.
Signed-off-by: Jamin Lin
---
hw/arm/as
According to the AST2700 datasheet, the INTC(CPU DIE) controller has 16KB
(0x4000) of register space, and the INTCIO (I/O DIE) controller has 1KB (0x400)
of register space.
Introduced a new class attribute "mem_size" to set different memory sizes for
the INTC models in AST2700.
Introduced a new c
The previous implementation set the "aspeed_intc_ops" struct, containing read
and write callbacks, to be used when I/O is performed on the INTC region.
Both "aspeed_intc_read" and "aspeed_intc_write" callback functions were used
for INTC (CPU Die).
To support the INTCIO (IO Die) model, introduces
The behavior of the enable and status registers is almost identical between
INTC(CPU Die) and INTCIO(IO Die). To reduce duplicated code, adds
"aspeed_intc_enable_handler" functions to handle enable register write
behavior and "aspeed_intc_status_handler" functions to handle status
register write be
This update introduces support for handling multi-output IRQs in the AST2700
interrupt controller (INTC), specifically for GICINT192_201. GICINT192_201 maps
1:10 to input IRQ 0 and output IRQs 0 to 9. Each status bit corresponds to a
specific IRQ.
Implemented "aspeed_intc_set_irq_handler_multi_out
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_hace.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index e3f7df2e86..18b85081c7 100644
--- a/hw/misc/aspeed_hace.c
+++ b/hw/m
v1:
1. Refactor INTC model to support both INTC0 and INTC1.
2. Support AST2700 A1.
3. Create ast2700a0-evb machine.
v2:
To streamline the review process, split the following patch series into
three parts.
https://patchwork.kernel.org/project/qemu-devel/cover/20250121070424.2465942-1-jam
The behavior of the INTC set IRQ is almost identical between INTC and INTCIO.
To reduce duplicated code, introduce the "aspeed_intc_set_irq_handler" function
to handle both INTC and INTCIO IRQ behavior.
Signed-off-by: Jamin Lin
---
hw/intc/aspeed_intc.c | 62 -
To support AST2700 A1, some registers of the INTC(CPU Die) support one input
pin to multiple output pins. Renamed "num_ints" to "num_inpins" in the INTC
controller code for better clarity and consistency in naming conventions.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 2 +-
h
According to the design of the AST2600, it has a Silicon Revision ID Register,
specifically SCU004 and SCU014, to set the Revision ID for the AST2600.
For the AST2600 A3, SCU004 is set to 0x05030303 and SCU014 is set to 0x05030303.
In the "aspeed_ast2600_scu_reset" function, the hardcoded value
"AS
Added new definitions for AST2700_A1_SILICON_REV and AST2750_A1_SILICON_REV to
identify the A1 silicon revisions.
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_scu.c | 2 ++
include/hw/misc/aspeed_scu.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/a
Signed-off-by: Jamin Lin
---
tests/functional/test_aarch64_aspeed.py | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tests/functional/test_aarch64_aspeed.py
b/tests/functional/test_aarch64_aspeed.py
index aa817afa4e..788dd29a6d 100755
--- a/tests/functional/test_aarch64
Signed-off-by: Jamin Lin
---
tests/functional/test_aarch64_aspeed.py | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tests/functional/test_aarch64_aspeed.py
b/tests/functional/test_aarch64_aspeed.py
index 788dd29a6d..ad2774be15 100755
--- a/tests/functional/test_aarch
Introduce a new ast2700 INTCIO class to support AST2700 INTCIO.
Added new register definitions for INTCIO, including enable and status
registers for IRQs GICINT192 through GICINT197.
Created a dedicated IRQ array for INTCIO, supporting six input pins and six
output pins, aligning with the newly def
The memory map for AST2700 A1 remains compatible with AST2700 A0. However, the
IRQ mapping has been updated for AST2700 A1, with GIC interrupts now ranging
from 192 to 201. Add a new IRQ map table for AST2700 A1.
Add "aspeed_soc_ast2700a1_class_init" to initialize the AST2700 A1 SoC.
Introduce "asp
Signed-off-by: Jamin Lin
---
tests/functional/test_aarch64_aspeed.py | 7 +++
1 file changed, 7 insertions(+)
diff --git a/tests/functional/test_aarch64_aspeed.py
b/tests/functional/test_aarch64_aspeed.py
index ad2774be15..2afc50265a 100755
--- a/tests/functional/test_aarch64_aspeed.py
+++
The INTC controller supports GICINT128 to GICINT136, mapping 1:1 to input and
output IRQs 0 to 8. Previously, the formula "address & 0x0f00" was used to
derive the IRQ index numbers.
However, the INTC controller also supports GICINT192_201, mapping 1 input IRQ
pin to 10 output IRQ pins. The pin nu
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
tests/functional/test_aarch64_aspeed.py | 10 ++
1 file changed, 10 insertions(+)
diff --git a/tests/functional/test_aarch64_aspeed.py
b/tests/functional/test_aarch64_aspeed.py
index 8df6a97a28..c25c966278 100755
--- a/tests/fu
To improve readability, sort the memmap table by mapping address
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed_ast27x0.c | 54 -
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/as
The HACE models in AST2600 and AST2700 are nearly identical. Based on the
AST2600 test cases, new tests have been added for AST2700.
Implemented test functions for SHA-256, SHA-384, SHA-512, and MD5.
Added scatter-gather and accumulation test variants.
For AST2700, the HACE controller base address
v1:
1. Added support for 64-bit DMA in the HACE model
2. Refactored the do_hash operation in the HACE model
3. Fixed a crash caused by out-of-bound memory access in HACE
4. Added more trace events and implemented dumping of source hash data and
resulting digests to improve debugging
5. Ref
According to the AST2700 design, the data source address is 64-bit, with
R_HASH_SRC_HI storing bits [63:32] and R_HASH_SRC storing bits [31:0].
Similarly, the digest address is 64-bit, with R_HASH_DEST_HI storing bits
[63:32] and R_HASH_DEST storing bits [31:0].
Ideally, sg_addr should be 64-bit
Currently, the hash data source and digest result buffer addresses are set to
32-bit. However, the AST2700 CPU is a 64-bit Cortex-A35 architecture, and its
DRAM base address is also 64-bit.
To support AST2700, update the hash data source address and digest result buffer
address to use 64-bit addre
This cleanup follows significant changes in commit 4c1d0af4a28d, making the
model more readable.
- Deleted "iov_cache" and "iov_count" from "AspeedHACEState".
- Removed "reconstruct_iov" function and related logic.
- Simplified "do_hash_operation" by eliminating redundant checks.
Signed-off-by: J
The HACE model in AST2600 and AST1030 is identical. Referencing the AST2600
test cases, new tests have been created for AST1030.
Implemented test functions for SHA-256, SHA-384, SHA-512, and MD5.
Added scatter-gather and accumulation test variants.
For AST1030, the HACE controller base address sta
The test cases for the ASPEED HACE model were originally placed in
aspeed_hace-test.c. However, this test file only supports ARM32. To enable
compatibility with all ASPEED SoCs, including the AST2700, which uses the
AArch64 architecture, this update introduces a new source file,
aspeed-hace-utils.c
1. Disabled by default. Uncomment "#define DEBUG_HACE 1" to enable it.
2. Uses the "qemu_hexdump" API to dump the digest result.
3. Uses the "iov_hexdump" API to dump the source vector, which contains the
source plaintext.
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_hace.c | 12
Introduced SHA-384 test functions to verify hashing operations.
Extended support for scatter-gather (`_sg`) and accumulation (`_accum`) tests.
Updated test result vectors for SHA-384 validation.
Signed-off-by: Jamin Lin
---
tests/qtest/aspeed-hace-utils.h | 6 ++
tests/qtest/aspeed-hace-utils.
The AST2700 CPU, based on the Cortex-A35, is a 64-bit processor, and its DRAM
address space is also 64-bit. To support future AST2700 updates, the source
hash buffer address data type is being updated to 64-bit.
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_hace.c | 8 +---
1 file changed, 5 i
301 - 400 of 685 matches
Mail list logo
