AST2700 dram size calculation is not back compatible AST2600.
According to the DDR capacity hardware behavior,
if users write the data to address which is beyond the ram size,
it would write the data to address 0.
For example:
a. sdram base address "0x4 "
b. sdram size is 1 GiB
The availabl
AST2700 support the maximum dram size is 8GiB
and has a "DMA DRAM Side Address High Part(0x7C)"
register to support 64 bits dma dram address.
Add helper routines functions to compute the dma dram
address, new features and update trace-event
to support 64 bits dram address.
Signed-off-by: Troy Lee
The SDRAM memory controller(DRAMC) controls the access to external
DDR4 and DDR5 SDRAM and power up to DDR4 and DDR5 PHY.
The DRAM memory controller of AST2700 is not backward compatible
to previous chips such AST2600, AST2500 and AST2400.
Max memory is now 8GiB on the AST2700. Introduce new
aspe
These macros are no longer used for ASPEED SOCs, so removes them.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/misc/aspeed_sdmc.c | 15 ---
1 file changed, 15 deletions(-)
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index 64c
Fix coding style issues from checkpatch.pl
Test command:
scripts/checkpatch.pl --no-tree -f hw/misc/aspeed_sdmc.c
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/misc/aspeed_sdmc.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --
Add AST2700 Evaluation board and its boot command.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
docs/system/arm/aspeed.rst | 39 ++
1 file changed, 35 insertions(+), 4 deletions(-)
diff --git a/docs/system/arm/aspeed.rs
AST2700 interrupt controller(INTC) provides hardware interrupt interfaces
to interrupt of processors PSP, SSP and TSP. In INTC, each interrupt of
INT 128 to INT136 combines 32 interrupts.
Introduce a new aspeed_intc class with instance_init and realize handlers.
So far, this model only supports G
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/ssi/aspeed_smc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 6e1a84c197..8a8d77b480 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/a
AST2700 have two SCU controllers which are SCU and SCUIO.
Both SCU and SCUIO registers are not compatible previous SOCs
, introduces new registers and adds ast2700 scu, sucio class init handler.
The pclk divider selection of SCUIO is defined in SCUIO280[20:18] and
the pclk divider selection of SCU
AST2700 wdt controller is similiar to AST2600's wdt, but
the AST2700 has 8 watchdogs, and they each have 0x80 of registers.
Introduce ast2700 object class and increase the number of regs(offset) of
ast2700 model.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
Add a test case to test Aspeed OpenBMC SDK v09.01 on AST2700 board.
It loads u-boot-nodtb.bin, u-boot.dtb, tfa and optee-os
images to dram first which base address is 0x4.
Then, boot and launch 4 cpu cores.
```
qemu-system-aarch64 -machine ast2700-evb
-device loader,force-raw=on,addr=
Changes from v1:
The patch series supports WDT, SDMC, SMC, SCU, SLI and INTC for AST2700 SoC.
Changes from v2:
- replace is_aarch64 with is_bus64bit for sdmc patch review.
- fix incorrect dram size for AST2700
Changes from v3:
- Add AST2700 Evaluation board in ASPEED document
- Add avocado test c
AST2700 SLI engine is designed to accelerate the
throughput between cross-die connections.
It have CPU_SLI at CPU die and IO_SLI at IO die.
Introduce dummy AST2700 SLI and SLIIO models.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/misc/aspeed_sli.c
AST2700 have two SCU controllers which are SCU and SCUIO.
Both SCU and SCUIO registers are not compatible previous SOCs
, introduces new registers and adds ast2700 scu, sucio class init handler.
The pclk divider selection of SCUIO is defined in SCUIO280[20:18] and
the pclk divider selection of SCU
AST2700 wdt controller is similiar to AST2600's wdt, but
the AST2700 has 8 watchdogs, and they each have 0x80 of registers.
Introduce ast2700 object class and increase the number of regs(offset) of
ast2700 model.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
It set "aspeed_smc_flash_ops" struct which containing
read and write callbacks to be used when I/O is performed
on the SMC flash region. And it set the valid max_access_size 4
by default for all ASPEED SMC models.
However, the valid max_access_size 4 only support 32 bits CPUs.
To support all ASPEE
AST2700 fmc/spi controller's address decoding unit is 64KB
and only bits [31:16] are used for decoding. Introduce seg_to_reg
and reg_to_seg handlers for ast2700 fmc/spi controller.
In addition, adds ast2700 fmc, spi0, spi1, and spi2 class init handler.
AST2700 is a 64 bits quad core CPUs(Cortex-a3
AST2700 CPU is ARM Cortex-A35 which is 64 bits.
Add TARGET_AARCH64 to build this machine.
According to the design of ast2700, it has a bootmcu(riscv-32) which
is used for executing SPL.
Then, CPUs(cortex-a35) execute u-boot, kernel and rofs.
Currently, qemu not support emulate two CPU architectur
AST2700 dram size calculation is not back compatible AST2600.
According to the DDR capacity hardware behavior,
if users write the data to the address which is beyond the ram size,
it would write the data to the "address % ram_size".
For example:
a. sdram base address "0x4 "
b. sdram size 1
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/ssi/aspeed_smc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 7075bc9d61..fe1cd96b80 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/a
Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35 CPU).
AST2700 SOC and its interrupt controller are too complex to handle
in the common Aspeed SoC framework. We introduce a new ast2700
class with instance_init and realize handlers.
AST2700 is a 64 bits quad core cpus and
AST2700 interrupt controller(INTC) provides hardware interrupt interfaces
to interrupt of processors PSP, SSP and TSP. In INTC, each interrupt of
INT 128 to INT136 combines 32 interrupts.
Introduce a new aspeed_intc class with instance_init and realize handlers.
So far, this model only supports G
Add AST2700 Evaluation board and its boot command.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
docs/system/arm/aspeed.rst | 39 ++
1 file changed, 35 insertions(+), 4 deletions(-)
diff --git a/docs/system/arm/aspeed.rs
The SDRAM memory controller(DRAMC) controls the access to external
DDR4 and DDR5 SDRAM and power up to DDR4 and DDR5 PHY.
The DRAM memory controller of AST2700 is not backward compatible
to previous chips such AST2600, AST2500 and AST2400.
Max memory is now 8GiB on the AST2700. Introduce new
aspe
Fix coding style issues from checkpatch.pl
Test command:
scripts/checkpatch.pl --no-tree -f hw/misc/aspeed_sdmc.c
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/misc/aspeed_sdmc.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --
DMA length is from 1 byte to 32MB for AST2600 and AST10x0
and DMA length is from 4 bytes to 32MB for AST2500.
In other words, if "R_DMA_LEN" is 0, it should move at least 1 byte
data for AST2600 and AST10x0 and 4 bytes data for AST2500.
To support all ASPEED SOCs, adds dma_start_length parameter t
Add a test case to test Aspeed OpenBMC SDK v09.01 on AST2700 board.
It loads u-boot-nodtb.bin, u-boot.dtb, tfa and optee-os
images to dram first which base address is 0x4.
Then, boot and launch 4 cpu cores.
```
qemu-system-aarch64 -machine ast2700-evb
-device loader,force-raw=on,addr=
AST2700 support the maximum dram size is 8GiB
and has a "DMA DRAM Side Address High Part(0x7C)"
register to support 64 bits dma dram address.
Add helper routines functions to compute the dma dram
address, new features and update trace-event
to support 64 bits dram address.
Signed-off-by: Troy Lee
These macros are no longer used for ASPEED SOCs, so removes them.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/misc/aspeed_sdmc.c | 15 ---
1 file changed, 15 deletions(-)
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index 64c
Add ASPEED members "Steven Lee", "Troy Lee" and "Jamin Lin"
to be maintainers of ASPEED BMCs.
Signed-off-by: Jamin Lin
Signed-off-by: Troy Lee
Signed-off-by: Steven Lee
---
MAINTAINERS | 3 +++
1 file changed, 3 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 951556224a..39651be467
Add ASPEED members "Steven Lee", "Troy Lee" and "Jamin Lin"
to be reviewers of ASPEED BMCs.
Signed-off-by: Jamin Lin
Signed-off-by: Troy Lee
Signed-off-by: Steven Lee
---
MAINTAINERS | 3 +++
1 file changed, 3 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 951556224a..0f63bcdc7d 1
Fix coverity defect: DIVIDE_BY_ZERO.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index b6876b4862..d14a46df6f 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@
change from v1:
aspeed/soc: coverity defect: DIVIDE_BY_ZERO
aspeed/sdmc: coverity defect: Control flow issues (DEADCODE)
Jamin Lin (2):
aspeed/soc: fix coverity issue
aspeed/sdmc: fix coverity issue
hw/arm/aspeed_ast27x0.c | 6 ++
hw/misc/aspeed_sdmc.c | 1 -
2 files changed, 6 inserti
Fix coverity defect: Control flow issues (DEADCODE)
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_sdmc.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index 93e2e29ead..94eed9264d 100644
--- a/hw/misc/aspeed_sdmc.c
+++ b/hw/misc/aspeed_sdmc.c
@@ -
Fix coding style issues from checkpatch.pl
Test command:
./scripts/checkpatch.pl --no-tree -f hw/net/ftgmac100.c
Signed-off-by: Jamin Lin
---
hw/net/ftgmac100.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
index 74b6c3d
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
And the base address of dram is "0x4 " which
is 64bits address.
It have "Normal Priority Transmit Ring Base Address Register High(0x17C)",
"High Priority Transmit Ring Base Address Register High(0x184)" and
"Receive Ring Base Addr
change from v1:
- ftgmac100
- fix coding style
- support 64 bits dma dram address for AST2700
Jamin Lin (2):
hw/net:ftgmac100: fix coding style
hw/net:ftgmac100: support 64 bits dma dram address for AST2700
hw/net/ftgmac100.c | 83 ++
include/hw/
Introduce a new ast2700 class to support AST2700.
The I2C bus register memory regions and
I2C bus pool buffer memory regions are discontinuous
and they do not back compatible AST2600.
Add a new ast2700 i2c class init function to match the
address of I2C bus register and pool buffer from the datash
v1:
- support I2C for AST2700
v2:
- fix review issues and add reviewer suggestion
- update avocado test case for AST2700 I2C
- support i2c bus pool
v3:
- update commit messages and commit title
- update API to get the device irq
Jamin Lin (11):
hw/i2c/aspeed: Support discontinuous register mem
The "Current DMA Operating Address Status(0x50)" register of
I2C new mode has been removed in AST2700.
This register is used for debugging and it is a read only register.
To support AST2700 DMA mode, introduce a new
dma_dram_offset class attribute in AspeedI2Cbus to save the
current DMA operating
It only support continuous pool buffer memory region for all I2C bus.
However, the pool buffer address of all I2c bus are discontinuous
for AST2700.
Ex: the pool buffer address of I2C bus for ast2700 as following.
0x1A0 - 0x1BF: Device 0 buffer
0x2A0 - 0x2BF: Device 1 buffer
0x3A0 - 0x3BF: Device
ASPEED SDK add lm75 in i2c bus 0 for AST2700.
LM75 is compatible with TMP105 driver.
Introduce a new i2c init function and
add tmp105 device model in i2c bus 0.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed.c | 10 ++
1 file changed, 10 insertions(+)
diff --
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
and the base address of dram is "0x4 " which
is 64bits address.
It has "Master DMA Mode Tx Buffer Base Address[39:32](0x60)"
and "Master DMA Mode Rx Buffer Base Address[39:32](0x64)"
registers to save the high part physical addres
According to the datasheet of ASPEED SOCs,
each I2C bus has their own pool buffer since AST2500.
Only AST2400 utilized a pool buffer share to all I2C bus.
Besides, using a share pool buffer only support
pool buffer memory regions are continuous for all I2C bus.
To make this model more readable and
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
and the base address of dram is "0x4 " which
is 64bits address.
The AST2700 support the maximum DRAM size is 8 GB.
The DRAM physical address range is from "0x4__" to
"0x5__".
The DRAM offset range is from "0x0_000
It only support continuous register memory region for all I2C bus.
However, the register address of all I2c bus are discontinuous
for AST2700.
Ex: the register address of I2C bus for ast2700 as following.
0x100 - 0x17F: Device 0
0x200 - 0x27F: Device 1
0x300 - 0x37F: Device 2
0x400 - 0x47F: Device
Add I2C model for AST2700 I2C support.
The I2C controller registers base address is start at
0x14C0_F000 and its address space is 0x2000.
The AST2700 I2C controller has one source INTC per bus.
I2C buses interrupt are connected to GICINT130_INTC
from bit 0 to bit 15.
I2C bus 0 is connected to GICI
Currently, users can set the INTC mapping table with
enumerated device id and device irq to get the INTC orgate
input pins. However, some devices use the continuous source numbers in the
same INTC orgate. To reduce the enumerated device id definition,
create a new API to get the INTC orgate input p
Update test case to test lm75 temperature sensor.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
tests/avocado/machine_aspeed.py | 16
1 file changed, 16 insertions(+)
diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
index c0b01e8f1f..
Add ADC model for AST2700 ADC support.
The ADC controller registers base address is start at
0x14C0_ and its address space is 0x1000.
The ADC controller interrupt is connected to
GICINT130_INTC group at bit 16. The GIC IRQ is 130.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 12 +++
v1:
1. support ADC for AST2700
2. support I2C for AST2700
Jamin Lin (15):
aspeed/adc: Add AST2700 support
aspeed/soc: support ADC for AST2700
hw/i2c/aspeed: support to set the different memory size
hw/i2c/aspeed: support discontinuous register memory region of I2C bus
hw/i2c/aspeed: ren
According to the datasheet of ASPEED SOCs,
an I2C controller owns 8KB of register space for AST2700,
owns 4KB of register space for AST2600, AST2500 and AST2400,
and owns 64KB of register space for AST1030.
It set the memory region size 4KB by default and it does not compatible
register space for
It only support continuous register memory region for all I2C bus.
However, the register address of all I2c bus are discontinuous
for AST2700.
Ex: the register address of I2C bus for ast2700 as following.
0x100 - 0x17F: Device 0
0x200 - 0x27F: Device 1
0x300 - 0x37F: Device 2
0x400 - 0x47F: Device
AST2700 and AST2600 ADC controllers are identical.
Introduce ast2700 class and set 2 engines.
Signed-off-by: Jamin Lin
---
hw/adc/aspeed_adc.c | 16
include/hw/adc/aspeed_adc.h | 1 +
2 files changed, 17 insertions(+)
diff --git a/hw/adc/aspeed_adc.c b/hw/adc/aspeed_ad
Introduce a new ast2700 class to support AST2700.
The I2C bus register memory regions and
I2C bus pool buffer memory regions are discontinuous
and they do not back compatible AST2600.
Add a new ast2700 i2c class init function to match the
address of I2C bus register and pool buffer from the datash
According to the datasheet of ASPEED SOCs,
each I2C bus has their own pool buffer since AST2500.
Only AST2400 utilized a pool buffer share to all I2C bus.
And firmware required to set the offset of pool buffer
by writing "Function Control Register(I2CD 00)"
To make this model more readable, will
ASPEED SDK add lm75 in i2c bus 0 for AST2700.
LM75 is compatible with TMP105 driver.
Introduce a new i2c init function and
add tmp105 device model in i2c bus 0.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/
Add I2C model for AST2700 I2C support.
The I2C controller registers base address is start at
0x14C0_F000 and its address space is 0x2000.
The AST2700 I2C controller has one source INTC per bus.
I2C buses interrupt are connected to GICINT130_INTC
from bit 0 to bit 15.
I2C bus 0 is connected to GICI
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
And the base address of dram is "0x4 " which
is 64bits address.
It have "Master DMA Mode Tx Buffer Base Address[39:32](0x60)"
and "Master DMA Mode Rx Buffer Base Address[39:32](0x64)"
to save the high part physical address of Tx/R
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
And the base address of dram is "0x4 " which
is 64bits address.
The AST2700 support the maximum DRAM size is 8 GB.
The DRAM physical address range is from "0x4__" to
"0x5__".
The DRAM offset range is from "0x0_000
The "Current DMA Operating Address Status(0x50)" register of
I2C new mode has been removed in AST2700.
This register is used for debugging and it is a read only register.
To support AST2700 DMA mode, introduce a new
dma_dram_offset class attribute in AspeedI2Cbus to save the
current DMA operating
It only support continuous pool buffer memory region for all I2C bus.
However, the pool buffer address of all I2c bus are discontinuous
for AST2700.
Ex: the pool buffer address of I2C bus for ast2700 as following.
0x1A0 - 0x1BF: Device 0 buffer
0x2A0 - 0x2BF: Device 1 buffer
0x3A0 - 0x3BF: Device
According to the datasheet of ASPEED SOCs,
each I2C bus has their own pool buffer since AST2500.
Only AST2400 utilized a pool buffer share to all I2C bus.
Besides, using a share pool buffer only support
pool buffer memory regions are continuous for all I2C bus.
To make this model more readable and
Currently, users can set the intc mapping table with
enumerated device id and device irq to get the INTC orgate
input pins. However, some devices use the continuous bits number in the
same orgate. To reduce the enumerated device id definition,
create a new API to get the INTC orgate index and sourc
Fix coding style issues from checkpatch.pl
Test command:
./scripts/checkpatch.pl --no-tree -f hw/arm/aspeed.c
Signed-off-by: Jamin Lin
---
hw/arm/aspeed.c | 21 ++---
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 53a4f665d
Hi Konstantin
> Subject: Re: [PATCH v3 0/6] Support GPIO for AST2700
>
> On Fri, Sep 27, 2024 at 06:29:22AM GMT, Jamin Lin wrote:
> > > Also, your emails have an invalid "From" field set to
> > > "qemu-devel@nongnu.org" when retrieved with the b4 command.
>
> This is almost certainly done by the
Fix coding style issues from checkpatch.pl
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/gpio/aspeed_gpio.c | 6 +++---
include/hw/gpio/aspeed_gpio.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
inde
According to the datasheet of ASPEED SOCs, a GPIO controller owns 4KB of
register space for AST2700, AST2500, AST2400 and AST1030; owns 2KB of
register space for AST2600 1.8v and owns 2KB of register space for
AST2600 3.3v.
It set the memory region size 2KB by default and it does not compatible
re
The register set of GPIO have a significant change since AST2700.
Each GPIO pin has their own individual control register and users are able to
set one GPIO pin’s direction, interrupt enable, input mask and so on in the
same one control register.
AST2700 does not have GPIO18_XXX registers for GPIO
AST2700 integrates two set of Parallel GPIO Controller with maximum 212
control pins, which are 27 groups. (H, exclude pin: H7 H6 H5 H4)
In the previous design of ASPEED SOCs, one register is used for setting
one function for one set which are 32 pins and 4 groups.
ex: GPIO000 is used for setting
It set "aspeed_gpio_ops" struct which containing read and write callbacks
to be used when I/O is performed on the GPIO region.
Besides, in the previous design of ASPEED SOCs, one register is used for
setting one function for 32 GPIO pins.
ex: GPIO000 is used for setting data value for GPIO A, B, C
The interrupt status field is W1C, where a set bit on read indicates an
interrupt is pending. If the bit extracted from data is set it should
clear the corresponding bit in reg_value. However, if the extracted
bit is clear then the value of the corresponding bit in reg_value
should be unchanged.
S
v1: Support GPIO for AST2700
v2: Fix clear incorrect interrupt status and adds reviewer suggestions
v3: remove nested conditionals and adds reviewer suggestions
v4: add test cases to test GPIO for AST2700 and update commit messages
v5: fix aspeed_gpio-test test failed if arch is arm
v6: add to test
Add GPIO model for AST2700 GPIO support. The GPIO controller registers base
address is start at 0x14C0_B000 and its address space is 0x1000.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/as
Add test case to test GPIO output and input pins from A0 to D7 for AST2700.
Signed-off-by: Jamin Lin
---
tests/qtest/aspeed_gpio-test.c | 77 --
tests/qtest/meson.build| 3 ++
2 files changed, 76 insertions(+), 4 deletions(-)
diff --git a/tests/qtest/asp
Currently, these test cases are only used for testing fmc_cs0 for AST2400.
To test others BMC SOCs, introduces a new TestData structure.
Users can set the spi base address, flash base address, jedesc id and so on
for different BMC SOCs and flash model testing.
Introduce new helper functions to mak
Add test_ast2700_evb function and reused testcases which are from
aspeed_smc-test.c for AST2700 testing. The base address, flash base address
and ce index of fmc_cs0 are 0x1400, 0x1 and 0, respectively.
The default flash model of fmc_cs0 is "w25q01jvq" whose size is 128MB,
so set jedec_
Currently, these test cases only support to test CE0. To test all CE pins,
introduces new ce and node members in TestData structure. The ce member is used
for saving the ce index and node member is used for saving the node path,
respectively.
Signed-off-by: Jamin Lin
---
tests/qtest/aspeed_smc-t
Currently, the default fmc_model was "sst25vf032b" whose size was 4MB for
ast1030-a1 EVB. However, according to the schematic of ast1030-a1 EVB,
ASPEED shipped default flash of fmc_cs0 and fmc_cs1 were "w25q80bl" and
"w25q256", respectively. The size of w25q80bl is 1MB and the size of w25q256
is 32
Fix coding style issues from checkpatch.pl
Signed-off-by: Jamin Lin
---
tests/qtest/aspeed_smc-test.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
index c713a3700b..4673371d95 100644
--- a/tests/qtest/aspe
Add test_ast1030_evb function and reused testcases for AST1030 testing.
The base address, flash base address and ce index of fmc_cs0 are
0x7E62, 0x8000 and 0, respectively.
The default flash model of fmc_cs0 is "w25q80bl" whose size is 1MB,
so set jedec_id 0xef4014.
Signed-off-by: Jamin Li
Add test_ast2600_evb function and reused testcases for AST2600 testing.
The spi base address, flash base address and ce index of fmc_cs0 are
0x1E62, 0x2000 and 0, respectively.
The default flash model of fmc_cs0 is "mx66u51235f" whose size is 64MB,
so set jedec_id 0xc2253a.
Signed-off-by:
Add test_ast2500_evb function and reused testcases for AST2500 testing.
The spi base address, flash base address and ce index of fmc_cs0 are
0x1E62, 0x2000 and 0, respectively.
The default flash model of fmc_cs0 is "mx25l25635e" whose size is 32MB,
so set jedec_id 0xc22019.
Signed-off-by:
change from v1:
1. Fix write incorrect data into flash in user mode.
2. Refactor aspeed smc qtest testcases to support AST2600, AST2500 and
AST1030.
3. Add ast2700 smc qtest testcase to support AST2700.
QEMU version:
https://github.com/qemu/qemu/commit/95a16ee753d6da651fce8df876333bf7fcf134d9
Add the SFDP table for the Windbond w25q80bl flash.
Signed-off-by: Jamin Lin
---
hw/block/m25p80.c | 3 ++-
hw/block/m25p80_sfdp.c | 36
hw/block/m25p80_sfdp.h | 2 +-
3 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/hw/block/m25p80.c b/
Add a new testcase for write page command with QPI mode testing.
Currently, only run this testcase for AST2500, AST2600 and AST1030.
Signed-off-by: Jamin Lin
---
tests/qtest/aspeed_smc-test.c | 74 +++
1 file changed, 74 insertions(+)
diff --git a/tests/qtest/asp
Currently, the default spi_model was "sst25vf032b" whose size was 4MB for
ast1030-a1 EVB. However, according to the schematic of ast1030-a1 EVB,
ASPEED shipped default flash of spi1 and spi2 were w25q256 whose size
was 32MB.
Correct spi_model default flash to w25q256 for ast1030-a1 EVB.
Signed-of
Currently, these test cases used the hardcode offset 0x140 (0x14000 * 256)
which was beyond the 16MB flash size for flash page read/write command testing.
However, the default fmc flash model of ast1030-a1 EVB is "w25q80bl" whose size
is 1MB. To test all flash models, introduces a new page_addr
According to the design of ASPEED SPI controllers user mode, users write the
data to flash, the SPI drivers set the Control Register(0x10) bit 0 and 1
enter user mode. Then, SPI drivers send flash commands for writing data.
Finally, SPI drivers set the Control Register (0x10) bit 2 to stop
active c
Fix coding style issues from checkpatch.pl
Signed-off-by: Jamin Lin
---
hw/block/m25p80.c | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index f7123f9e68..3f55b8f385 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m
So far, the test cases are used for testing SMC model with AST2400 BMC.
However, AST2400 is end off live and ASPEED is no longer support this SOC.
To test SMC model for AST2500, AST2600 and AST1030, move the test cases
from main to test_palmetto_bmc function.
Signed-off-by: Jamin Lin
---
tests/q
According to the w25q01jv datasheet at page 16, it is required to set QE bit
in "Status Register 2" to enable quad mode.
Currently, m25p80 support users utilize "Write Status Register 1(0x01)" command
to set QE bit in "Status Register 2" and utilize "Read Status Register 2(0x35)"
command to get th
The testcases for ASPEED SMC model were placed in aspeed_smc-test.c.
However, this test file only supports for ARM32. To support all ASPEED SOCs
such as AST2700 whose CPU architecture is aarch64, introduces a new
aspeed-smc-utils source file and move all common APIs and testcases
from aspeed_smc-te
Add test_ast2600_evb function and reused testcases for AST2600 testing.
The spi base address, flash base address and ce index of fmc_cs0 are
0x1E62, 0x2000 and 0, respectively.
The default flash model of fmc_cs0 is "mx66u51235f" whose size is 64MB,
so set jedec_id 0xc2253a.
Signed-off-by:
Add the SFDP table for the Windbond w25q80bl flash.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/block/m25p80.c | 3 ++-
hw/block/m25p80_sfdp.c | 36
hw/block/m25p80_sfdp.h | 2 +-
3 files changed, 39 insertions(+), 2 deletions(-)
di
Fix coding style issues from checkpatch.pl
Signed-off-by: Jamin Lin
Reviewed-by: Thomas Huth
Reviewed-by: Cédric Le Goater
---
tests/qtest/aspeed_smc-test.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
i
Currently, these test cases used the hardcode offset 0x140 (0x14000 * 256)
which was beyond the 16MB flash size for flash page read/write command testing.
However, the default fmc flash model of ast1030-a1 EVB is "w25q80bl" whose size
is 1MB. To test all flash models, introduces a new page_addr
It only attached flash model of fmc and spi[0] in aspeed_machine_init function.
However, AST2500 and AST2600 have one fmc and two spi(spi1 and spi2)
controllers; AST2700 have one fmc and 3 spi(spi0, spi1 and spi2) controllers.
Besides, it used hardcode to attach flash model of fmc, spi[0] and spi[
Fix coding style issues from checkpatch.pl
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/block/m25p80.c | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index f7123f9e68..3f55b8f385 100644
--- a/hw/
Add a new testcase for write page command with QPI mode testing.
Currently, only run this testcase for AST2500, AST2600 and AST1030.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
tests/qtest/aspeed_smc-test.c | 74 +++
1 file changed, 74 insertions(+
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