[Qemu-devel] [PATCH 1/3] apic: Added helper function apic_match_dest, apic_match_[physical, logical]_dest

2015-03-24 Thread James Sullivan
Added three helper functions apic_match_dest(), apic_match_physical_dest(), and apic_match_logical_dest() which can be used to determine if a logical or physical APIC ID match a given LAPIC under a given dest_mode. This does not account for shorthand. Signed-off-by: James Sullivan --- hw/intc

[Qemu-devel] [PATCH] apic: Implement low-priority arbitration for IRQ delivery

2015-03-24 Thread James Sullivan
Currently, there is no arbitration among processors for low priority IRQ delivery. Implemented apic_get_arb_pri(), and added two new functions apic_compare_prio() and apic_lowest_prio() to support arbitration in apic_bus_deliver(). Signed-off-by: James Sullivan --- hw/intc/apic.c | 67

[Qemu-devel] [PATCH 2/3] apic: Set and pass in RH bit for MSI interrupts

2015-03-24 Thread James Sullivan
In apic_send_msi(), set msi_redir_hint to 0x1 when RH=1 in the MSI Address Register. Added an argument for msi_redir_hint to apic_deliver_irq(), and changed calls to the function accordingly (using 0 as a default value for non-MSI interrupts). Signed-off-by: James Sullivan --- hw/intc/apic.c

[Qemu-devel] [PATCH 3/3] apic: Implement handling of RH=1 for MSI interrupt delivery

2015-03-24 Thread James Sullivan
message should target only the lowest-priority processor among those specified by the logical destination of the IRQ. Signed-off-by: James Sullivan --- hw/intc/apic.c | 34 -- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/hw/intc/apic.c b/hw/intc

[Qemu-devel] [PATCH 0/3] apic: Implement handling for MSI redirection hint in IRQ delivery

2015-03-24 Thread James Sullivan
VM in http://www.spinics.net/lists/kvm/msg114915.html ("kvm: x86: Implement handling of RH=1 for MSI delivery in KVM"), which are under review but are largely settled in terms of functionality. James Sullivan (3): apic: Added helper function apic_match_dest, apic_match_[physical,logic

[Qemu-devel] [PATCH v2 0/5] Implement RH bit handling and lowpri arbitration

2015-03-24 Thread James Sullivan
quot;), which are under review but are largely settled in terms of functionality. James Sullivan (5): apic: Implement LAPIC low priority arbitration functions apic: Implement low priority arbitration for IRQ delivery apic: Added helper function apic_match_dest, apic_match_[physical,logical

[Qemu-devel] [PATCH v2 2/5] apic: Implement low priority arbitration for IRQ delivery

2015-03-24 Thread James Sullivan
). Signed-off-by: James Sullivan --- hw/intc/apic.c | 20 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/hw/intc/apic.c b/hw/intc/apic.c index b372513..47d2fb1 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -249,22 +249,10 @@ static void apic_bus_del

[Qemu-devel] [PATCH v2 4/5] apic: Set and pass in RH bit for MSI interrupts

2015-03-24 Thread James Sullivan
In apic_send_msi(), set msi_redir_hint to 0x1 when RH=1 in the MSI Address Register. Added an argument for msi_redir_hint to apic_deliver_irq(), and changed calls to the function accordingly (using 0 as a default value for non-MSI interrupts). Signed-off-by: James Sullivan --- Changes in v2

[Qemu-devel] [PATCH v2 3/5] apic: Added helper function apic_match_dest, apic_match_[physical, logical]_dest

2015-03-24 Thread James Sullivan
Added three helper functions apic_match_dest(), apic_match_physical_dest(), and apic_match_logical_dest() which can be used to determine if a logical or physical APIC ID match a given LAPIC under a given dest_mode. This does not account for shorthand. Signed-off-by: James Sullivan --- hw/intc

Re: [Qemu-devel] [PATCH] apic: Implement low-priority arbitration for IRQ delivery

2015-03-24 Thread James Sullivan
Merging this into <1427224426-9025-1-git-send-email-sullivan.jame...@gmail.com>. On 03/23/2015 04:26 PM, James Sullivan wrote: > Currently, there is no arbitration among processors for low priority IRQ > delivery. Implemented apic_get_arb_pri(), and added two new functions > ap

[Qemu-devel] [PATCH v2 5/5] apic: Implement handling of RH=1 for MSI interrupt delivery

2015-03-24 Thread James Sullivan
message should target only the lowest-priority processor among those specified by the logical destination of the IRQ. Signed-off-by: James Sullivan --- hw/intc/apic.c | 34 -- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/hw/intc/apic.c b/hw/intc

[Qemu-devel] [PATCH v3 2/5] apic: Implement LAPIC low priority arbitration functions

2015-03-24 Thread James Sullivan
Currently, apic_get_arb_pri() is unimplemented and returns 0. Implemented apic_get_arb_pri() and added two helper functions apic_compare_prio() and apic_lowest_prio() to be used for LAPIC arbitration. Signed-off-by: James Sullivan --- hw/intc/apic.c | 47

[Qemu-devel] [PATCH v2 RESEND 2/5] apic: Implement low priority arbitration for IRQ delivery

2015-04-06 Thread James Sullivan
). Signed-off-by: James Sullivan --- hw/intc/apic.c | 20 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/hw/intc/apic.c b/hw/intc/apic.c index b372513..47d2fb1 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -249,22 +249,10 @@ static void apic_bus_del

[Qemu-devel] [PATCH v2 RESEND 3/5] apic: Added helper function apic_match_dest, apic_match_[physical, logical]_dest

2015-04-06 Thread James Sullivan
Added three helper functions apic_match_dest(), apic_match_physical_dest(), and apic_match_logical_dest() which can be used to determine if a logical or physical APIC ID match a given LAPIC under a given dest_mode. This does not account for shorthand. Signed-off-by: James Sullivan --- hw/intc

[Qemu-devel] [PATCH v2 RESEND 4/5] apic: Set and pass in RH bit for MSI interrupts

2015-04-06 Thread James Sullivan
In apic_send_msi(), set msi_redir_hint to 0x1 when RH=1 in the MSI Address Register. Added an argument for msi_redir_hint to apic_deliver_irq(), and changed calls to the function accordingly (using 0 as a default value for non-MSI interrupts). Signed-off-by: James Sullivan --- Changes in v2

[Qemu-devel] [PATCH v2 RESEND 1/5] apic: Implement LAPIC low priority arbitration functions

2015-04-06 Thread James Sullivan
Currently, apic_get_arb_pri() is unimplemented and returns 0. Implemented apic_get_arb_pri() and added two helper functions apic_compare_prio() and apic_lowest_prio() to be used for LAPIC arbitration. Signed-off-by: James Sullivan --- hw/intc/apic.c | 47

[Qemu-devel] [PATCH v2 RESEND 0/5] apic: Implement MSI RH bit handling, lowpri IRQ

2015-04-06 Thread James Sullivan
"), which have been reviewed and discussed on the KVM mailing list. James Sullivan (5): apic: Implement LAPIC low priority arbitration functions apic: Implement low priority arbitration for IRQ delivery apic: Added helper function apic_match_dest, apic_match_[physical,logical]_dest apic

[Qemu-devel] [PATCH v2 RESEND 5/5] apic: Implement handling of RH=1 for MSI interrupt delivery

2015-04-06 Thread James Sullivan
message should target only the lowest-priority processor among those specified by the logical destination of the IRQ. Signed-off-by: James Sullivan --- hw/intc/apic.c | 34 -- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/hw/intc/apic.c b/hw/intc

Re: [Qemu-devel] [PATCH v2 RESEND 1/5] apic: Implement LAPIC low priority arbitration functions

2015-04-23 Thread James Sullivan
On 04/23/2015 07:49 AM, Radim Krčmář wrote: > 2015-04-06 17:45-0600, James Sullivan: >> Currently, apic_get_arb_pri() is unimplemented and returns 0. >> >> Implemented apic_get_arb_pri() and added two helper functions >> apic_compare_prio() and apic_lowest_

Re: [Qemu-devel] [PATCH v2 RESEND 5/5] apic: Implement handling of RH=1 for MSI interrupt delivery

2015-04-23 Thread James Sullivan
On 04/23/2015 08:14 AM, Radim Krčmář wrote: > 2015-04-06 17:45-0600, James Sullivan: >> Added argument to apic_get_delivery_bitmask() for msi_redir_hint, >> and changed calls to the function accordingly (using 0 as a default >> value for non-MSI interrupts). >> >&g

[Qemu-devel] [PATCH v3 0/4] apic: Implement MSI RH bit handling, lowpri IRQ delivery

2015-04-30 Thread James Sullivan
RH=1 for MSI delivery in KVM"), which is queued for 4.2. James Sullivan (4): apic: Implement LAPIC low priority arbitration functions apic: Set and pass in RH bit for MSI interrupts apic: Add helper functions apic_match_dest, apic_match_[physical,logical]_dest apic: Handle RH=1 a

[Qemu-devel] [PATCH v3 1/4] apic: Implement LAPIC low priority arbitration functions

2015-04-30 Thread James Sullivan
Currently, apic_get_arb_pri() is unimplemented and returns 0. Implemented apic_get_arb_pri() and added helper function apic_compare_prio() to be used for LAPIC arbitration. Signed-off-by: James Sullivan --- Changes in v3: * Fixed apic_get_arb_pri to use AMD's algorithm vs. In

[Qemu-devel] [PATCH v3 3/4] apic: Add helper functions apic_match_dest, apic_match_[physical, logical]_dest

2015-04-30 Thread James Sullivan
Added three helper functions apic_match_dest(), apic_match_physical_dest(), and apic_match_logical_dest() which can be used to determine if a logical or physical APIC ID match a given LAPIC under a given dest_mode. This does not account for shorthand. Signed-off-by: James Sullivan --- hw/intc

[Qemu-devel] [PATCH v3 4/4] apic: Handle RH=1 and lowpri delivery mode in apic_get_delivery_bitmask()

2015-04-30 Thread James Sullivan
. Signed-off-by: James Sullivan --- Changes in v3: * Added extra argument to apic_get_delivery_bitmask() for delivery_mode * Perform lowpri arbitration in apic_get_delivery_bitmask() for RH=1 and for APIC_DM_LOWPRI, saving the cost of the LAPIC iteration in v2 * Deliver

[Qemu-devel] [PATCH v3 2/4] apic: Set and pass in RH bit for MSI interrupts

2015-04-30 Thread James Sullivan
In apic_send_msi(), set msi_redir_hint to 0x1 when RH=1 in the MSI Address Register. Added an argument for msi_redir_hint to apic_deliver_irq(), and changed calls to the function accordingly (using 0 as a default value for non-MSI interrupts). Signed-off-by: James Sullivan --- Changes in v2