or1ksim simulator currently handles "l.nop 0xC" instruction as a halt signal. Do
the same for QEMU.
Signed-off-by: Hesham ALMatary
---
target-openrisc/translate.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
ind
or1ksim simulator currently handles "l.nop 0xC" instruction as
a halt signal. Do the same for QEMU.
Signed-off-by: Hesham ALMatary
---
target-openrisc/translate.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
ind
tables
Brice Goglin (4):
hmat acpi: Don't require initiator value in -numa
tests: acpi: add and whitelist *.hmat-noinitiator expected blobs
tests: acpi: q35: add test for hmat nodes without initiators
tests: acpi: q35: update expected blobs *.hmat-noinitiators expected
HMAT:
H
Entry : 000A
[11Eh 0286 2]Entry : 0001
Signed-off-by: Brice Goglin
Signed-off-by: Hesham Almatary
Reviewed-by: Jingqi Liu
---
hw/core/machine.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index a673302c
00 00 00 40 00 00 00 00 03 00 00 02 00 00 00 // @...
00F0: 03 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 //
0100: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 //
0110: 02 00 00 00 0A 00 05 00 01 00 05 00 0A 00 01 00 //
Signe
From: Xiang Chen
Since the patchset ("Build ACPI Heterogeneous Memory Attribute Table (HMAT)"),
HMAT is supported, but only x86 is enabled. Enable HMAT on arm virt machine.
Signed-off-by: Xiang Chen
Signed-off-by: Hesham Almatary
Reviewed-by: Igor Mammedov
---
hw/arm/Kconfig
Signed-off-by: Hesham Almatary
---
tests/data/acpi/virt/APIC.acpihmatvirt | 0
tests/data/acpi/virt/DSDT.acpihmatvirt | 0
tests/data/acpi/virt/HMAT.acpihmatvirt | 0
tests/data/acpi/virt/PPTT.acpihmatvirt | 0
tests/data/acpi/virt/SRAT.acpihmatvirt | 0
tests/qtest/bios
From: Brice Goglin
.. which will be used by follow up hmat-noinitiator test-case.
Signed-off-by: Brice Goglin
Signed-off-by: Hesham Almatary
---
tests/data/acpi/q35/APIC.acpihmat-noinitiator | 0
tests/data/acpi/q35/DSDT.acpihmat-noinitiator | 0
tests/data/acpi/q35/HMAT.acpihmat-noinitiator
00 00 00 0A 00 05 00 01 00 05 00 0A 00 01 00 //
....
Signed-off-by: Hesham Almatary
---
tests/data/acpi/virt/APIC.acpihmatvirt | Bin 0 -> 396 bytes
tests/data/acpi/virt/DSDT.acpihmatvirt | Bin 0 -> 5282 bytes
tests/data/acpi/virt/HMAT.acpihmatvirt | Bin 0 -> 288 byte
60
\
-numa
hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,latency=30
\
-numa
hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576
Signed-off-by: Hesham Almatary
---
tests/qtest/bios-tables-test.c | 59 ++
00 00 00 40 00 00 00 00 03 00 00 02 00 00 00 // @...
00F0: 03 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 //
0100: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 //
0110: 02 00 00 00 0A 00 05 00 01 00 05 00 0A 00 01 00 //
Signe
The PMP should be checked when doing a page table walk, and report access
fault exception if the to-be-read PTE failed the PMP check.
Suggested-by: Jonathan Behrens
Signed-off-by: Hesham Almatary
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h| 1 +
target/riscv/cpu_helper.c
ceptions
trap values.
Signed-off-by: Hesham Almatary
Reviewed-by: Alistair Francis
---
target/riscv/cpu_helper.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 40fb47e794..7c7282c680 100644
--- a/target/risc
instruction fetch page
fault.
This patch prioritises MMU exceptions over PMP exceptions and only checks for
PMP if MMU translation succeeds. This patch is required for future commits
that properly report PMP exception violations if PTW succeeds.
Signed-off-by: Hesham Almatary
Reviewed-by: Alistair
PRV_S.
This patch passes the effective memory privilege mode to the PMP check.
Functions that call the PMP check should pass the correct memory privilege mode
after reading mstatus' MPRV/MPP or hstatus.SPRV (if Hypervisor mode exists).
Suggested-by: Alistair Francis
Signed-off-by: Hesh
The PMP check should be of the memory access size rather
than TARGET_PAGE_SIZE.
Signed-off-by: Hesham Almatary
Reviewed-by: Alistair Francis
---
target/riscv/cpu_helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
checking the PMP permissions if the address is
in range and its corresponding PMP entry it not off. Otherwise, it will keep
the ret = -1 which will be checked and handled correctly at the end of the
function.
Signed-off-by: Hesham Almatary
Reviewed-by: Alistair Francis
---
target/riscv/pmp.c | 9
ping
On Wed, 22 May 2019 at 11:26, Hesham Almatary
wrote:
>
> On Tue, 21 May 2019 at 23:40, Alistair Francis wrote:
> >
> > On Tue, May 21, 2019 at 3:44 AM Hesham Almatary
> > wrote:
> > >
> > > The PMP should be checked when doing a page table walk,
On Thu, 30 May 2019 at 05:07, Alistair Francis wrote:
>
> On Wed, May 22, 2019 at 2:27 AM Hesham Almatary
> wrote:
> >
> > On Tue, 21 May 2019 at 23:40, Alistair Francis wrote:
> > >
> > > On Tue, May 21, 2019 at 3:44 AM Hesham Almatary
> > >
PRV_S.
This patch passes the effective memory privilege mode to the PMP check.
Functions that call the PMP check should pass the correct memory privilege mode
after reading mstatus' MPRV/MPP or hstatus.SPRV (if Hypervisor mode exists).
Suggested-by: Alistair Francis
Signed-off-by: Hesh
ceptions
trap values.
Signed-off-by: Hesham Almatary
Reviewed-by: Alistair Francis
---
target/riscv/cpu_helper.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 40fb47e794..7c7282c680 100644
--- a/target/risc
The PMP should be checked when doing a page table walk, and report access
fault exception if the to-be-read PTE failed the PMP check.
Suggested-by: Jonathan Behrens
Signed-off-by: Hesham Almatary
---
target/riscv/cpu.h| 1 +
target/riscv/cpu_helper.c | 10 +-
2 files changed
instruction fetch page
fault.
This patch prioritises MMU exceptions over PMP exceptions and only checks for
PMP if MMU translation succeeds. This patch is required for future commits
that properly report PMP exception violations if PTW succeeds.
Signed-off-by: Hesham Almatary
Reviewed-by: Alistair
checking the PMP permissions if the address is
in range and its corresponding PMP entry it not off. Otherwise, it will keep
the ret = -1 which will be checked and handled correctly at the end of the
function.
Signed-off-by: Hesham Almatary
Reviewed-by: Alistair Francis
---
target/riscv/pmp.c | 9
The PMP check should be of the memory access size rather
than TARGET_PAGE_SIZE.
Signed-off-by: Hesham Almatary
Reviewed-by: Alistair Francis
---
target/riscv/cpu_helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
On Wed, 5 Jun 2019 at 23:07, Alistair Francis wrote:
>
> On Thu, May 30, 2019 at 6:52 AM Hesham Almatary
> wrote:
> >
> > The PMP should be checked when doing a page table walk, and report access
> > fault exception if the to-be-read PTE failed the PMP check.
>
ceptions
trap values.
Signed-off-by: Hesham Almatary
---
target/riscv/cpu_helper.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 41d6db41c3..b48de36114 100644
--- a/target/riscv/cpu_helper.c
+++ b/targe
instruction fetch page
fault.
This patch prioritises MMU exceptions over PMP exceptions and only checks for
PMP if MMU translation succeeds.
Signed-off-by: Hesham Almatary
---
target/riscv/cpu_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv
The PMP should be checked when doing a page table walk, and report access
fault exception if the to-be-read PTE address failed the PMP check.
Suggested-by: Jonathan Behrens
Signed-off-by: Hesham Almatary
---
target/riscv/cpu.h| 1 +
target/riscv/cpu_helper.c | 10 +-
2 files
happy to submit another patch to fix the second issue.
> Jonathan
>
> On Sat, May 18, 2019 at 3:14 PM Hesham Almatary
> wrote:
>>
>> Section 3.6 in RISC-V v1.10 privilege specification states that PMP
>> violations
>> report "access exceptions." T
instruction fetch page
fault.
This patch prioritises MMU exceptions over PMP exceptions and only checks for
PMP if MMU translation succeeds.
Signed-off-by: Hesham Almatary
---
target/riscv/cpu_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv
ceptions
trap values.
Signed-off-by: Hesham Almatary
---
target/riscv/cpu_helper.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 41d6db41c3..b48de36114 100644
--- a/target/riscv/cpu_helper.c
+++ b/targe
instruction fetch page
fault.
This patch prioritises MMU exceptions over PMP exceptions and only checks for
PMP if MMU translation succeeds.
Signed-off-by: Hesham Almatary
---
target/riscv/cpu_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv
The PMP should be checked when doing a page table walk, and report access
fault exception if the to-be-read PTE failed the PMP check.
Suggested-by: Jonathan Behrens
Signed-off-by: Hesham Almatary
---
target/riscv/cpu.h| 1 +
target/riscv/cpu_helper.c | 10 +-
2 files changed
The PMP check should be of the memory access size rather
than TARGET_PAGE_SIZE.
Signed-off-by: Hesham Almatary
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index d0b0f9cf88..ce1f47e4e3
ceptions
trap values.
Reviewed-by: Alistair Francis
Signed-off-by: Hesham Almatary
---
target/riscv/cpu_helper.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 40fb47e794..7c7282c680 100644
--- a/target/risc
checking the PMP permissions if the address is
in range and its corresponding PMP entry it not off. Otherwise, it will keep
the ret = -1 which will be checked and handled correctly at the end of the
function.
Signed-off-by: Hesham Almatary
---
target/riscv/pmp.c | 9 +
1 file changed, 5
ction
> between physical memory protection and paging is very subtle. Even some real
> hardware has had errata related to it!
>
> Jonathan
>
> On Tue, May 21, 2019 at 6:33 PM Alistair Francis wrote:
>>
>> On Tue, May 21, 2019 at 3:45 AM Hesham Almatary
>> wrote:
instruction fetch page
fault.
This patch prioritises MMU exceptions over PMP exceptions and only checks for
PMP if MMU translation succeeds. This patch is required for future commits
that properly report PMP exception violations if PTW succeeds.
Signed-off-by: Hesham Almatary
---
target/riscv
checking the PMP permissions if the address is
in range and its corresponding PMP entry it not off. Otherwise, it will keep
the ret = -1 which will be checked and handled correctly at the end of the
function.
Signed-off-by: Hesham Almatary
Reviewed-by: Alistair Francis
---
target/riscv/pmp.c | 9
On Tue, 21 May 2019 at 23:40, Alistair Francis wrote:
>
> On Tue, May 21, 2019 at 3:44 AM Hesham Almatary
> wrote:
> >
> > The PMP should be checked when doing a page table walk, and report access
> > fault exception if the to-be-read PTE failed the PMP check.
>
Hello Michael,
On 7/26/2022 4:04 PM, Michael S. Tsirkin wrote:
On Tue, Jul 19, 2022 at 10:49:42AM +0100, Hesham Almatary wrote:
This patchset adds support for AArch64/HMAT including a test.
It relies on other two patch sets from:
Brice Goglin: to support -numa without initiators on q35/x86
Updates to issues with earlier patches in the pull request:
tests: acpi: q35: update expected blobs *.hmat-noinitiators expected HMAT
Signed-off-by: Hesham Almatary
---
tests/data/acpi/q35/DSDT.acpihmat-noinitiator | Bin 8553 -> 8691 bytes
1 file changed, 0 insertions(+), 0 deletions(-)
d
Updates to issues with earlier patches in the pull request:
tests: virt: Update expected *.acpihmatvirt tables
Signed-off-by: Hesham Almatary
---
tests/data/acpi/virt/APIC.acpihmatvirt | Bin 396 -> 412 bytes
1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/tests/data/acpi/v
Hello Michael,
On 7/26/2022 4:04 PM, Michael S. Tsirkin wrote:
On Tue, Jul 19, 2022 at 10:49:42AM +0100, Hesham Almatary wrote:
This patchset adds support for AArch64/HMAT including a test.
It relies on other two patch sets from:
Brice Goglin: to support -numa without initiators on q35/x86
Entry : 000A
[11Eh 0286 2]Entry : 0001
Signed-off-by: Brice Goglin
Signed-off-by: Hesham Almatary
Reviewed-by: Jingqi Liu
---
hw/core/machine.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index aa520e74
00 00 00 40 00 00 00 00 03 00 00 02 00 00 00 // @...
00F0: 03 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 //
0100: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 //
0110: 02 00 00 00 0A 00 05 00 01 00 05 00 0A 00 01 00 //
Signe
ected blobs *.hmat-noinitiators expected
HMAT:
Hesham Almatary (3):
tests: Add HMAT AArch64/virt empty table files
tests: acpi: aarch64/virt: add a test for hmat nodes with no
initiators
tests: virt: Update expected *.acpihmatvirt tables
Xiang Chen (1):
hw/arm/virt: Enable HMAT o
From: Xiang Chen
Since the patchset ("Build ACPI Heterogeneous Memory Attribute Table (HMAT)"),
HMAT is supported, but only x86 is enabled. Enable HMAT on arm virt machine.
Signed-off-by: Xiang Chen
Signed-off-by: Hesham Almatary
Reviewed-by: Igor Mammedov
---
hw/arm/Kconfig
00 00 00 0A 00 05 00 01 00 05 00 0A 00 01 00 //
....
Signed-off-by: Hesham Almatary
---
tests/data/acpi/virt/APIC.acpihmatvirt | Bin 0 -> 396 bytes
tests/data/acpi/virt/DSDT.acpihmatvirt | Bin 0 -> 5282 bytes
tests/data/acpi/virt/HMAT.acpihmatvirt | Bin 0 -> 288 byte
00 02 00 00 00 // @...
00F0: 03 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 //
0100: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 //
0110: 02 00 00 00 0A 00 05 00 01 00 05 00 0A 00 01 00 //
Signed-off-by:
From: Brice Goglin
.. which will be used by follow up hmat-noinitiator test-case.
Signed-off-by: Brice Goglin
Signed-off-by: Hesham Almatary
---
tests/data/acpi/q35/APIC.acpihmat-noinitiator | 0
tests/data/acpi/q35/DSDT.acpihmat-noinitiator | 0
tests/data/acpi/q35/HMAT.acpihmat-noinitiator
Signed-off-by: Hesham Almatary
---
tests/data/acpi/virt/APIC.acpihmatvirt | 0
tests/data/acpi/virt/DSDT.acpihmatvirt | 0
tests/data/acpi/virt/HMAT.acpihmatvirt | 0
tests/data/acpi/virt/PPTT.acpihmatvirt | 0
tests/data/acpi/virt/SRAT.acpihmatvirt | 0
tests/qtest/bios
60
\
-numa
hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,latency=30
\
-numa
hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576
Signed-off-by: Hesham Almatary
---
tests/qtest/bios-tables-test.c | 59 ++
From: Brice Goglin
.. which will be used by follow up hmat-noinitiator test-case.
Signed-off-by: Brice Goglin
---
tests/data/acpi/q35/APIC.acpihmat-noinitiator | 0
tests/data/acpi/q35/DSDT.acpihmat-noinitiator | 0
tests/data/acpi/q35/FACP.acpihmat-noinitiator | 0
tests/data/acpi/q35/HMAT.ac
blobs
tests: acpi: q35: add test for hmat nodes without initiators
tests: acpi: q35: update expected blobs *.hmat-noinitiators
Hesham Almatary (3):
tests: Add HMAT AArch64/virt empty table files
tests: acpi: aarch64/virt: add a test for hmat nodes with no
initiators
tests: virt: Update exp
From: Brice Goglin
The "Memory Proximity Domain Attributes" structure of the ACPI HMAT
has a "Processor Proximity Domain Valid" flag that is currently
always set because Qemu -numa requires an initiator=X value
when hmat=on. Unsetting this flag allows to create more complex
memory topologies by h
From: Brice Goglin
expected HMAT:
[000h 4]Signature : "HMAT"[Heterogeneous Memory
Attributes Table]
[004h 0004 4] Table Length : 0120
[008h 0008 1] Revision : 02
[009h 0009 1] Checksum : 4F
[00Ah 00
From: Brice Goglin
expected HMAT:
[000h 4]Signature : "HMAT"[Heterogeneous Memory
Attributes Table]
[004h 0004 4] Table Length : 0120
[008h 0008 1] Revision : 02
[009h 0009 1] Checksum : 4F
[00Ah 00
From: Xiang Chen
Since the patchset ("Build ACPI Heterogeneous Memory Attribute Table (HMAT)"),
HMAT is supported, but only x86 is enabled. Enable HMAT on arm virt machine.
Signed-off-by: Xiang Chen
---
hw/arm/Kconfig | 1 +
hw/arm/virt-acpi-build.c | 7 +++
2 files changed, 8 in
Signed-off-by: Hesham Almatary
---
tests/data/acpi/virt/DSDT.acpihmatvirt | 0
tests/data/acpi/virt/FACP.acpihmatvirt | 0
tests/data/acpi/virt/HMAT.acpihmatvirt | 0
tests/data/acpi/virt/SRAT.acpihmatvirt | 0
tests/qtest/bios-tables-test-allowed-diff.h | 4
5 files
h,bandwidth=10485760
\
-numa
hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,latency=30
\
-numa
hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576
Signed-off-by: Hesham Almatary
---
tests/qtest/bio
1 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 //
0030: 03 12 00 00 00 00 00 00 00 00 01 00 00 00 00 00 //
0040: 00 00 01 28 00 00 00 00 00 00 00 00 00 40 00 00 // ...(.@..
0050: 00 00 00 00 00 08 00 00 00 00 00 00 00 00 01 00 //
00
On 7/18/2022 2:54 PM, Igor Mammedov wrote:
On Mon, 11 Jul 2022 11:44:29 +0100
Hesham Almatary wrote:
From: Brice Goglin
The "Memory Proximity Domain Attributes" structure of the ACPI HMAT
has a "Processor Proximity Domain Valid" flag that is currently
always se
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