On Mon, Aug 24, 2015 at 03:13:40PM +0100, Peter Maydell wrote:
>On 24 August 2015 at 13:03, Gavin Shan wrote:
>> This submits changes with formatted commit log while updating Linux
>> headers using scripts/update-linux-headers.sh.
>>
>> Signed-off-by: Gavin Shan
>
On Mon, Aug 24, 2015 at 03:08:33PM +0100, Peter Maydell wrote:
>On 24 August 2015 at 13:03, Gavin Shan wrote:
>> This submits changes with formatted commit log while updating Linux
>> headers using scripts/update-linux-headers.sh.
>>
>> Signed-off-by: Gavin Shan
>
&
On Tue, Aug 25, 2015 at 04:09:22PM +0100, Peter Maydell wrote:
>On 25 August 2015 at 00:58, Gavin Shan wrote:
>> On Mon, Aug 24, 2015 at 03:08:33PM +0100, Peter Maydell wrote:
>>>On 24 August 2015 at 13:03, Gavin Shan wrote:
>>>> +cd $to
>>>&
On Tue, Aug 25, 2015 at 04:07:35PM +0200, Thomas Huth wrote:
>On 24/08/15 14:03, Gavin Shan wrote:
>> This supports RTAS calls "ibm,{open,close}-errinjct" to manupliate
>> the token, which is passed to RTAS call "ibm,errinjct" to indicate
>> the vali
of
pointer in vring_init()").
Signed-off-by: Gavin Shan
Reviewed-by: Thomas Huth
---
scripts/update-linux-headers.sh | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh
index f0e830c..2fddf2e 100755
--- a/scripts
rtas_ibm_errinjct().
* Don't expose error injection tokens for unsupported types.
v2:
* Rebased to git://github.com/dgibson/qemu.git (branch: spapr-next)
* Remove specific PCI error types in hw/ppc/spapr.h. Use those macros
asm-powerpc/eeh.h instead.
Gavin Shan (8):
scripts: Allow inc
This submits changes with formatted commit log while updating Linux
headers using scripts/update-linux-headers.sh.
Signed-off-by: Gavin Shan
---
scripts/update-linux-headers.sh | 24
1 file changed, 24 insertions(+)
diff --git a/scripts/update-linux-headers.sh b
/eeh: Introduce eeh_pe_inject_err()")
Signed-off-by: Gavin Shan
---
scripts/update-linux-headers.sh | 1 +
1 file changed, 1 insertion(+)
diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh
index 2fddf2e..18daabe 100755
--- a/scripts/update-linux-headers.sh
+++ b/
Synchronize the Linux headers from kernel version 4.2.0-rc8
(commit c13dcf9)
Signed-off-by: Gavin Shan
---
include/standard-headers/linux/pci_regs.h| 381 ---
include/standard-headers/linux/virtio_ring.h | 3 +-
linux-headers/asm-powerpc/eeh.h | 56
:
commit 24bc69da ("PCI: Clean up MSI/MSI-X capability #defines")
commit 846fc709 ("PCI/AER: Rename PCI_ERR_UNC_TRAIN to PCI_ERR_UNC_UND")
Signed-off-by: Gavin Shan
---
hw/i386/kvm/pci-assign.c | 4 ++--
hw/pci/msix.c| 2 +-
hw/pci/pcie_aer.c| 2 +-
hw/s390x
This introduces rtas_ldq() to load 64-bits parameter from continuous
two 4-bytes memory chunk of RTAS parameter buffer, to simplify the
code.
Signed-off-by: Gavin Shan
Reviewed-by: Thomas Huth
---
hw/ppc/spapr_pci.c | 20 ++--
include/hw/ppc/spapr.h | 5 +
2 files
token is resetted in ppc_spapr_reset() when rebooting guest. It's
notable that the least bit of the token is reserved to indicate if the
token has been opened, meaning the valid token should be always odd.
Signed-off-by: Gavin Shan
---
hw/ppc/spapr.c | 9 +++-
hw
container IOCTL command to be handled
by the host.
Signed-off-by: Gavin Shan
---
hw/ppc/spapr_pci.c | 36 +
hw/ppc/spapr_pci_vfio.c | 35 +
hw/ppc/spapr_rtas.c | 77 +
include/hw/pci-host/sp
On Fri, Aug 28, 2015 at 01:50:47PM +0200, Laurent Vivier wrote:
>On 28/08/2015 09:15, Gavin Shan wrote:
>> This submits changes with formatted commit log while updating Linux
>> headers using scripts/update-linux-headers.sh.
>>
>> Signed-off-by: Gavin Shan
>
On Fri, Aug 28, 2015 at 10:30:48PM +1000, Gavin Shan wrote:
>On Fri, Aug 28, 2015 at 01:50:47PM +0200, Laurent Vivier wrote:
>>On 28/08/2015 09:15, Gavin Shan wrote:
>>> This submits changes with formatted commit log while updating Linux
>>> headers using scri
On Mon, Aug 31, 2015 at 02:37:43PM +0200, Laurent Vivier wrote:
>On 28/08/2015 14:30, Gavin Shan wrote:
>> On Fri, Aug 28, 2015 at 01:50:47PM +0200, Laurent Vivier wrote:
>>> On 28/08/2015 09:15, Gavin Shan wrote:
>>>> This submits changes with formatted c
The patch implements sPAPRPHBClass::eeh_handler so that the
EEH RTAS requests can be routed to VFIO for further handling.
Signed-off-by: Gavin Shan
---
hw/ppc/spapr_pci_vfio.c | 56 +
1 file changed, 56 insertions(+)
diff --git a/hw/ppc
Replace "if (...)" with "switch (...)".
Gavin Shan (3):
sPAPR: Implement EEH RTAS calls
headers: Update kernel header
sPAPR: Implement sPAPRPHBClass::eeh_handler
hw/ppc/spapr_pci.c | 240
hw/ppc/spapr_pci_vfio.c |
This updates kernel header (vfio.h) for EEH support on VFIO PCI
devices.
Signed-off-by: Gavin Shan
---
linux-headers/linux/vfio.h | 34 ++
1 file changed, 34 insertions(+)
diff --git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h
index f0aa97d
call. Error
codes from that ioctl() are transferred back to the guest.
Signed-off-by: Gavin Shan
---
hw/ppc/spapr_pci.c | 240
include/hw/pci-host/spapr.h | 7 ++
include/hw/ppc/spapr.h | 33 ++
3 files changed, 280 insertions(+)
On Thu, Jun 26, 2014 at 12:30:16PM +0200, Alexander Graf wrote:
>
>On 26.06.14 03:35, Gavin Shan wrote:
>>The emulation for EEH RTAS requests from guest isn't covered
>>by QEMU yet and the patch implements them.
>>
>>The patch defines constants used by
On Thu, Jun 26, 2014 at 12:46:50PM +0200, Alexander Graf wrote:
>
>On 26.06.14 12:43, Gavin Shan wrote:
>>On Thu, Jun 26, 2014 at 12:30:16PM +0200, Alexander Graf wrote:
>>>On 26.06.14 03:35, Gavin Shan wrote:
>>>>The emulation for EEH RTAS requests from guest isn&
ions (Markus)
v2: The property is changed to smp-cpus since 5.0 (Phild)
---
qapi/qom.json | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Gavin Shan
diff --git a/qapi/qom.json b/qapi/qom.json
index 30e76653ad..f4a7917f3d 100644
--- a/qap
are fixed by PATCH[1] and PATCH[2] separately.
Gavin Shan (2):
hw/arm/virt: Improve address assignment for highmem IO regions
hw/arm/virt: Warn when high memory region is disabled
hw/arm/virt.c | 72 +++
1 file changed, 49 insertions(+), 23
roperly if PCIE_MMIO high memory region is
disabled due to the PA limit.
Signed-off-by: Gavin Shan
---
hw/arm/virt.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index bc0cd218f9..c91756e33d 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1691
It's incorrectly incurring waste in the PA
space.
Improve address assignment for highmem IO regions to avoid the waste
in the PA space by putting the logic into virt_memmap_fits().
Signed-off-by: Gavin Shan
---
hw/arm/virt.c | 54 +--
1 file c
Hi Eric,
On 8/2/22 7:41 PM, Eric Auger wrote:
On 8/2/22 08:45, Gavin Shan wrote:
There are 3 highmem IO regions as below. They can be disabled in
two situations: (a) The specific region is disabled by user. (b)
The specific region doesn't fit in the PA space. However, the base
addres
Hi Eric,
On 8/2/22 7:49 PM, Eric Auger wrote:
On 8/2/22 08:45, Gavin Shan wrote:
When one specific high memory region is disabled due to the PA
limit, it'd better to warn user about that. The warning messages
help to identify the cause in some cases. For example, PCIe device
that has
Hi Marc,
On 8/3/22 5:01 PM, Marc Zyngier wrote:
On Wed, 03 Aug 2022 04:01:04 +0100,
Gavin Shan wrote:
On 8/2/22 7:41 PM, Eric Auger wrote:
On 8/2/22 08:45, Gavin Shan wrote:
There are 3 highmem IO regions as below. They can be disabled in
two situations: (a) The specific region is disabled
Hi Eric,
On 8/3/22 6:44 PM, Eric Auger wrote:
On 8/3/22 05:01, Gavin Shan wrote:
On 8/2/22 7:41 PM, Eric Auger wrote:
On 8/2/22 08:45, Gavin Shan wrote:
There are 3 highmem IO regions as below. They can be disabled in
two situations: (a) The specific region is disabled by user. (b)
The
Hi Eric,
On 8/3/22 10:52 PM, Eric Auger wrote:
On 8/3/22 15:02, Gavin Shan wrote:
On 8/3/22 5:01 PM, Marc Zyngier wrote:
On Wed, 03 Aug 2022 04:01:04 +0100,
Gavin Shan wrote:
On 8/2/22 7:41 PM, Eric Auger wrote:
On 8/2/22 08:45, Gavin Shan wrote:
There are 3 highmem IO regions as below
Hi Eric,
On 8/4/22 5:19 PM, Eric Auger wrote:
On 8/4/22 04:47, Gavin Shan wrote:
On 8/3/22 10:52 PM, Eric Auger wrote:
On 8/3/22 15:02, Gavin Shan wrote:
On 8/3/22 5:01 PM, Marc Zyngier wrote:
On Wed, 03 Aug 2022 04:01:04 +0100,
Gavin Shan wrote:
On 8/2/22 7:41 PM, Eric Auger wrote:
On 8
Hi Marc,
On 8/8/22 7:17 PM, Marc Zyngier wrote:
On Wed, 03 Aug 2022 14:02:04 +0100,
Gavin Shan wrote:
On 8/3/22 5:01 PM, Marc Zyngier wrote:
On Wed, 03 Aug 2022 04:01:04 +0100,
Gavin Shan wrote:
On 8/2/22 7:41 PM, Eric Auger wrote:
On 8/2/22 08:45, Gavin Shan wrote:
There are 3 highmem
avoid the warning messages.
Fixes: a494fdb715 ("numa: Validate cluster and NUMA node boundary if required")
Signed-off-by: Gavin Shan
---
hw/core/machine.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index f0d35c6401..1c
On 7/20/23 23:10, Peter Maydell wrote:
On Mon, 26 Jun 2023 at 12:15, Paolo Bonzini wrote:
From: Gavin Shan
For some architectures like ARM64, multiple CPUs in one cluster can be
associated with different NUMA nodes, which is irregular configuration
because we shouldn't have th
(+), 58 deletions(-)
Some wrong replacements to be fixed in kvm_arch_put_fpsimd() as below.
Apart from that, LGTM:
Reviewed-by: Gavin Shan
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index b4c7654f4980..cdbffc3c6e0d 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -561,7 +561,6
Hi Connie,
On 7/18/23 21:14, Cornelia Huck wrote:
We can neaten the code by switching the callers that work on a
CPUstate to the kvm_get_one_reg function.
Signed-off-by: Cornelia Huck
---
target/arm/kvm.c | 15 +++-
target/arm/kvm64.c | 57 -
On 7/24/23 18:48, Cornelia Huck wrote:
On Mon, Jul 24 2023, Gavin Shan wrote:
On 7/18/23 21:14, Cornelia Huck wrote:
We can neaten the code by switching the callers that work on a
CPUstate to the kvm_get_one_reg function.
Signed-off-by: Cornelia Huck
---
target/arm/kvm.c | 15
Set mc->valid_cpu_{types, models} so that the specified CPU type
can be checked in machine_run_board_init(). We needn't to do the
check by ourselves.
Signed-off-by: Gavin Shan
---
hw/arm/virt.c | 39 ++-
1 file changed, 22 insertions(+), 17 deletions(
s to move the check (Marcin)
Gavin Shan (8):
machine: Use error handling when CPU type is checked
machine: Introduce helper is_cpu_type_supported()
machine: Print supported CPU models instead of typenames
hw/arm/virt: Check CPU type in machine_run_board_init()
hw/arm/virt: Unsuppo
Set mc->valid_cpu_{types, models} so that the specified CPU type
can be checked in machine_run_board_init(). We needn't to do the
check by ourselves.
Signed-off-by: Gavin Shan
---
hw/riscv/shakti_c.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/
Set mc->valid_cpu_{types, models} so that the specified CPU type
can be checked in machine_run_board_init(). We needn't to do the
check by ourselves.
Signed-off-by: Gavin Shan
---
hw/arm/sbsa-ref.c | 29 -
1 file changed, 12 insertions(+), 17 deletions(-)
di
s in the same function.
No functional change intended.
Suggested-by: Igor Mammedov
Signed-off-by: Gavin Shan
---
hw/core/machine.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index f0d35c6401..d7e7f8f120 100644
--- a
Set mc->valid_cpu_{types, models} so that the specified CPU type
can be checked in machine_run_board_init(). We needn't to do the
check by ourselves.
Signed-off-by: Gavin Shan
---
hw/arm/bananapi_m2u.c | 18 +++--
hw/arm/cubieboard.c | 18 +++--
hw/arm/m
line spanning of code. The comments are tweaked
a bit either.
No functional change intended.
Signed-off-by: Gavin Shan
---
hw/core/machine.c | 82 +--
1 file changed, 44 insertions(+), 38 deletions(-)
diff --git a/hw/core/machine.c b/hw/core/machine.c
the newly
added mc->valid_cpu_models because there is no fixed pattern for the
conversion between CPU model and typename. Besides, mc->valid_cpu_types
and mc->valid_cpu_models are further constified since we're here.
Signed-off-by: Gavin Shan
---
hw/core/machine.c | 10 ++-
7, cortex-a15, cortex-a35,
cortex-a55, cortex-a72, cortex-a76, a64fx, neoverse-n1,
neoverse-v1, cortex-a53, cortex-a57, host, max
Hide 'host' CPU model until KVM or HVF is enabled.
Signed-off-by: Gavin Shan
---
hw/arm/virt.c | 4
1 file changed, 4 insertions(+)
diff --git a/
Hi Xianglai,
On 7/20/23 17:15, xianglai li wrote:
Hello everyone, We refer to the implementation of ARM CPU
Hot-Plug to add GED-based CPU Hot-Plug support to Loongarch.
The first 4 patches are changes to the QEMU common code,
including adding GED support for CPU Hot-Plug, updating
the ACPI tabl
On 7/27/23 09:08, Richard Henderson wrote:
On 7/25/23 17:32, Gavin Shan wrote:
-static const char *q800_machine_valid_cpu_types[] = {
+static const char * const q800_machine_valid_cpu_types[] = {
M68K_CPU_TYPE_NAME("m68040"),
NULL
};
+static const ch
Hi Salil,
On 7/28/23 00:58, Salil Mehta wrote:
From: Gavin Shan
Sent: Thursday, July 27, 2023 1:57 AM
On 7/20/23 17:15, xianglai li wrote:
Hello everyone, We refer to the implementation of ARM CPU
Hot-Plug to add GED-based CPU Hot-Plug support to Loongarch.
The first 4 patches are changes to
073029 ("hw/arm/virt: Use machine_memory_devices_init()")
Signed-off-by: Gavin Shan
---
accel/kvm/kvm-all.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index 373d876c05..c825cba12f 100644
--- a/accel/kvm/kvm-all.c
+++ b/accel/kvm/kvm-all.c
@@ -24
On 7/27/23 19:00, Igor Mammedov wrote:
On Thu, 27 Jul 2023 15:16:18 +1000
Gavin Shan wrote:
On 7/27/23 09:08, Richard Henderson wrote:
On 7/25/23 17:32, Gavin Shan wrote:
-static const char *q800_machine_valid_cpu_types[] = {
+static const char * const q800_machine_valid_cpu_types
On 7/28/23 00:27, Richard Henderson wrote:
On 7/26/23 22:16, Gavin Shan wrote:
On 7/27/23 09:08, Richard Henderson wrote:
On 7/25/23 17:32, Gavin Shan wrote:
-static const char *q800_machine_valid_cpu_types[] = {
+static const char * const q800_machine_valid_cpu_types
files changed, 18 insertions(+), 54 deletions(-)
Reviewed-by: Gavin Shan
Thanks,
Gavin
crash is observed on
arm64.
Fixes: 176d073029 ("hw/arm/virt: Use machine_memory_devices_init()")
Signed-off-by: Gavin Shan
---
v2: Bail early in kvm_flush_coalesced_mmio_buffer() on the uninitialized
@kvm_state and improved changelog(David/Peter)
---
accel/kvm/kvm-all.c | 2 +
On 7/31/23 22:39, Peter Maydell wrote:
On Mon, 31 Jul 2023 at 08:18, David Hildenbrand wrote:
On 31.07.23 01:48, Gavin Shan wrote:
Runs into core dump on arm64 and the backtrace extracted from the
core dump is shown as below. It's caused by accessing @kvm_state which
isn't init
On 7/26/23 01:00, Shameer Kolothum wrote:
Now that we have Eager Page Split support added for ARM in the kernel[0],
enable it in Qemu. This adds,
-eager-split-size to Qemu options to set the eager page split chunk size.
-enable KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE.
The chunk size specifies h
On 2/12/20 10:34 PM, Peter Maydell wrote:
On Wed, 12 Feb 2020 at 06:39, Gavin Shan wrote:
On 2/5/20 10:05 PM, Gavin Shan wrote:
This allows to inject SError interrupt, which will be used on receiving
QMP/HMP "nmi" command in next patch.
Signed-off-by: Gavin Shan
---
target
On 2/13/20 4:39 PM, Richard Henderson wrote:
On 2/12/20 7:49 PM, Gavin Shan wrote:
On 2/12/20 10:34 PM, Peter Maydell wrote:
Yeah, this is on my list to look at; Richard Henderson also could
have a look at it. From a quick scan I suspect you may be missing
handling for AArch32.
[Thanks for
On 2/13/20 9:31 PM, Peter Maydell wrote:
On Thu, 13 Feb 2020 at 03:49, Gavin Shan wrote:
On 2/12/20 10:34 PM, Peter Maydell wrote:
Yeah, this is on my list to look at; Richard Henderson also could
have a look at it. From a quick scan I suspect you may be missing
handling for AArch32.
Yes
d Henderson)
* Export the SError injection through IRQ line (Peter Maydell)
* Removed RFC tag as it seems in correct track (Gavin Shan)
v2:
* Redesigned to fully exploit SError interrupt
Gavin Shan (2):
target/arm: Support SError injection
hw/arm/virt: Sim
vices who want to have the
capability of reporting errors in future.
Signed-off-by: Gavin Shan
---
hw/arm/virt.c | 34 +-
hw/intc/arm_gic_common.c | 3 +++
hw/intc/arm_gicv3_common.c | 3 +++
include/hw/intc/arm_gic_common.h | 1 +
led or not.
kvm_vcpu_ioctl(cpu, KVM_SET_VCPU_EVENTS) is leveraged to inject SError
or data abort to guest. When TCG is enabled, the behavior is simulated
by injecting SError and data abort to guest.
Signed-off-by: Gavin Shan
---
target/arm/cpu.c | 69 +++
target
On 2/13/20 10:11 PM, Peter Maydell wrote:
On Wed, 5 Feb 2020 at 11:06, Gavin Shan wrote:
This supports QMP/HMP "nmi" command by injecting SError interrupt to
guest, which is expected to crash with that. Currently, It's supported
on two CPU models: "host" and "ma
On 2/16/20 2:41 PM, Richard Henderson wrote:
On 2/13/20 9:59 PM, Gavin Shan wrote:
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b0762a76c4..180e29fb83 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -78,7 +78,7 @@ static bool arm_cpu_has_work(CPUState *cs)
&
Hi Marc,
On 2/16/20 11:34 PM, Marc Zyngier wrote:
On 2020-02-14 05:59, Gavin Shan wrote:
This supports SError injection, which will be used by "virt" board to
simulating the behavior of NMI injection in next patch. As Peter Maydell
suggested, this adds a new interrupt (ARM_CPU_SERR
, the implementation is similar to VFIQ.
Signed-off-by: Gavin Shan
---
target/arm/cpu.c | 48 +-
target/arm/cpu.h | 13 +++-
target/arm/helper.c| 20 +-
target/arm/internals.h | 10 +
target/arm/machine.c | 2 +-
5
vices who want to have the
capability of reporting errors in future.
Signed-off-by: Gavin Shan
---
hw/arm/virt.c | 34 +-
hw/intc/arm_gic_common.c | 3 +++
hw/intc/arm_gicv3_common.c | 3 +++
include/hw/intc/arm_gic_common.h | 1 +
ializing
the CPU's inbound IRQ lines atomic (Richard Henderson)
* Correct comments about ARM_CPU_IRQ (Richard Henderson)
* Update ISR.EL1 with SError state (Gavin Shan)
* Include SError state during migration(Gavi
led or not.
kvm_vcpu_ioctl(cpu, KVM_SET_VCPU_EVENTS) is leveraged to inject SError
or data abort to guest. When TCG is enabled, the behavior is simulated
by injecting SError and data abort to guest.
Signed-off-by: Gavin Shan
---
target/arm/cpu.c | 69 +++
target
Hi Marc,
On 2/19/20 3:28 AM, Marc Zyngier wrote:
On 2020-02-18 02:04, Gavin Shan wrote:
This supports SError injection, which will be used by "virt" board to
simulating the behavior of NMI injection in next patch. As Peter Maydell
suggested, this adds a new interrupt (ARM_CPU_SERROR)
ite_all() as the data will be dropped if the backend has
been running into so-called broken state or 50 attempts of transmissions.
The broken state is cleared if the data is transmitted at once.
Signed-off-by: Gavin Shan
---
chardev/char-fe.c | 15 +--
chardev/char.c
:All patches CC here)
Thanks for keeping right persons copied :)
On 2/20/20 7:01 AM, Gavin Shan wrote:
Currently, PL011 is used by ARM virt board by default. It's possible to
block the system from booting. With below parameters in command line, the
backend could run into endless atte
Hi Peter and Marc,
On 2/20/20 9:10 PM, Peter Maydell wrote:
On Thu, 20 Feb 2020 at 09:10, Marc Zyngier wrote:
On 2020-02-20 06:01, Gavin Shan wrote:
This fixes the issue by using newly added API
qemu_chr_fe_try_write_all(),
which provides another type of service (best-effort). It's diff
e_all(), which isn't nice.
This enables TxFIFO if possible. On ther other hand, the asynchronous
transmission is enabled if needed, as we did in hw/char/cadence_uart.c
Signed-off-by: Gavin Shan
---
hw/char/pl011.c | 70 +
include/hw/char/pl
On 2/21/20 7:25 PM, Paolo Bonzini wrote:
On 21/02/20 05:49, Gavin Shan wrote:
@@ -306,6 +362,7 @@ static const VMStateDescription vmstate_pl011 = {
VMSTATE_UINT32(int_enabled, PL011State),
VMSTATE_UINT32(int_level, PL011State),
VMSTATE_UINT32_ARRAY(read_fifo
arent object
is passed to the function, to avoid potential data corruption.
Signed-off-by: Gavin Shan
---
hw/core/nmi.c | 8
hw/i386/x86.c | 2 +-
hw/misc/macio/gpio.c | 6 +++---
hw/ppc/spapr.c | 2 +-
hw/s390x/s390-virtio-ccw.c | 2 +-
inclu
ring != NULL' failed
This just removes the check and unused message.
Signed-off-by: Gavin Shan
---
exec.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/exec.c b/exec.c
index ffdb518535..3cff459e43 100644
--- a/exec.c
+++ b/exec.c
@@ -963,11 +963,6 @@ const char *parse_cpu_opti
On 12/7/19 3:50 AM, Greg Kurz wrote:
On Fri, 6 Dec 2019 17:36:42 +1100
Gavin Shan wrote:
object_dynamic_cast() should return machine (or GPIO) state instad of NMI
state in do_nmi(). So it's wrong to convert it to NMI state unconditionally.
object_dynamic_cast() returns either its
ilippe Mathieu-Daudé
---
Reviewed-by: Gavin Shan
include/hw/nmi.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/nmi.h b/include/hw/nmi.h
index a1e128724e..fe37ce3ad8 100644
--- a/include/hw/nmi.h
+++ b/include/hw/nmi.h
@@ -31,7 +31,7 @@
#defi
On 12/7/19 3:58 AM, Greg Kurz wrote:
On Fri, 6 Dec 2019 17:33:37 +1100
Gavin Shan wrote:
The @cpu_option shouldn't be NULL, otherwise assertion from g_strsplit()
should be raised as below message indicates. So it's meaningless to validate
@model_pices[0] in parse_cpu_option() as it
On 12/8/19 3:51 AM, Greg Kurz wrote:
On Sat, 7 Dec 2019 23:56:55 +1100
Gavin Shan wrote:
On 12/7/19 3:58 AM, Greg Kurz wrote:
On Fri, 6 Dec 2019 17:33:37 +1100
Gavin Shan wrote:
The @cpu_option shouldn't be NULL, otherwise assertion from g_strsplit()
should be raised as below me
On 12/9/19 7:36 PM, Greg Kurz wrote:
On Sun, 8 Dec 2019 00:14:00 +1100
Gavin Shan wrote:
On 12/7/19 3:50 AM, Greg Kurz wrote:
On Fri, 6 Dec 2019 17:36:42 +1100
Gavin Shan wrote:
object_dynamic_cast() should return machine (or GPIO) state instad of NMI
state in do_nmi(). So it's wro
On 12/9/19 9:55 PM, Greg Kurz wrote:
On Mon, 9 Dec 2019 20:12:09 +1100
Gavin Shan wrote:
On 12/9/19 7:36 PM, Greg Kurz wrote:
On Sun, 8 Dec 2019 00:14:00 +1100
Gavin Shan wrote:
On 12/7/19 3:50 AM, Greg Kurz wrote:
On Fri, 6 Dec 2019 17:36:42 +1100
Gavin Shan wrote
On 1/31/20 8:39 PM, Marc Zyngier wrote:
On 2020-01-31 06:59, Gavin Shan wrote:
On 1/29/20 8:04 PM, Marc Zyngier wrote:
On 2020-01-29 02:44, Alexey Kardashevskiy wrote:
On 28/01/2020 17:48, Gavin Shan wrote:
but a NMI is injected
through LAPIC on x86. So I'm not sure what architect (s
This allows to inject SError interrupt, which will be used on receiving
QMP/HMP "nmi" command in next patch.
Signed-off-by: Gavin Shan
---
target/arm/cpu.c| 11 +++
target/arm/cpu.h| 12 +---
target/arm/helper.c | 4
3 files changed, 24 insertions(+), 3
mi" command is issued. The following error message
is given on "virt"+"cortext-a72": "Error: NMI injection not supported"
Changelog
=
v2:
* Redesigned to fully exploit SError interrupt
Gavin Shan (2):
target/arm: Allow to inject SError inte
This supports QMP/HMP "nmi" command by injecting SError interrupt to
guest, which is expected to crash with that. Currently, It's supported
on two CPU models: "host" and "max".
Signed-off-by: Gavin Shan
---
hw/arm/virt.c | 18
target
On 2/5/20 10:05 PM, Gavin Shan wrote:
This allows to inject SError interrupt, which will be used on receiving
QMP/HMP "nmi" command in next patch.
Signed-off-by: Gavin Shan
---
target/arm/cpu.c| 11 +++
target/arm/cpu.h| 12 +---
target/arm/helper.c |
0x140
ret_from_fork+0x10/0x20
Improve the situation to warn when multiple CPUs in one cluster have
been associated with different NUMA nodes. However, one NUMA node is
allowed to be associated with different clusters.
Signed-off-by: Gavin Shan
Acked-by: Philippe Mathieu-Daudé
Acked-by: Igor Mammedov
--
odes.
Signed-off-by: Gavin Shan
Reviewed-by: Daniel Henrique Barboza
Acked-by: Igor Mammedov
---
hw/riscv/spike.c | 2 ++
hw/riscv/virt.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 2c5546560a..81f7e53aed 100644
--- a/hw/riscv/spike.c
++
A
nodes.
Signed-off-by: Gavin Shan
Acked-by: Igor Mammedov
---
hw/arm/sbsa-ref.c | 2 ++
hw/arm/virt.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 0b93558dde..efb380e7c8 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -864,6 +
node boundary issues in qtests/numa-test (Gavin)
* Add helper set_numa_socket_boundary() and validate the
boundary in the generic path (Philippe)
Gavin Shan (3):
numa: Validate cluster and NUMA node boundary if required
hw/arm: Validate cluster and NUMA n
Hi Paolo,
On 5/9/23 10:27 AM, Gavin Shan wrote:
For arm64 and riscv architecture, the driver (/base/arch_topology.c) is
used to populate the CPU topology in the Linux guest. It's required that
the CPUs in one cluster can't span mutiple NUMA nodes. Otherwise, the Linux
scheduling domai
p the secondary bitmap and use the original one directly
(Juan)
* Avoid "goto out" in helper kvm_dirty_ring_init()
(Juan)
Gavin Shan (4):
migration: Add last stage indicator to global dirty log
kvm: Synchronize the backup bi
ring. With this,
the code looks a bit clean.
No functional change intended.
Signed-off-by: Gavin Shan
Reviewed-by: Peter Xu
Tested-by: Zhenyu Zhang
---
accel/kvm/kvm-all.c | 76 -
1 file changed, 47 insertions(+), 29 deletions(-)
diff --git a/accel
n the subsequent patches.
No functional change intended.
Signed-off-by: Gavin Shan
Reviewed-by: Peter Xu
Tested-by: Zhenyu Zhang
---
accel/kvm/kvm-all.c | 2 +-
include/exec/memory.h | 7 +--
migration/dirtyrate.c | 4 ++--
migration/ram.c | 20 ++--
softmmu/mem
In the last stage of live migration or memory slot removal, the
backup bitmap needs to be synchronized when it has been enabled.
Signed-off-by: Gavin Shan
Reviewed-by: Peter Xu
Tested-by: Zhenyu Zhang
---
accel/kvm/kvm-all.c | 11 +++
include/sysemu/kvm_int.h | 1 +
2 files
s always enabled
and the unnecessary overhead to do the last stage of dirty log synchronization
when those two devices aren't used is introduced, but the overhead should
be very small and acceptable. The benefit is cover future cases where those
two devices are used without modifying the code.
Hi Paolo,
On 5/9/23 12:21 PM, Gavin Shan wrote:
This series intends to support dirty ring for live migration for arm64. The
dirty ring use discrete buffer to track dirty pages. For arm64, the speciality
is to use backup bitmap to track dirty pages when there is no-running-vcpu
context. It&#
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