From: Frank Chang
tinfo.info:
One bit for each possible type enumerated in tdata1.
If the bit is set, then that type is supported by the currently
selected trigger.
Signed-off-by: Frank Chang
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 8
target/riscv/debug.c
From: Frank Chang
Current RISC-V debug assumes that only type 2 trigger is supported.
To allow more types of triggers to be supported in the future
(e.g. type 6 trigger, which is similar to type 2 trigger with additional
functionality), we should determine the trigger type from tdata1.type
From: Frank Chang
Trigger actions are shared among all triggers. Extract to a common
function.
Signed-off-by: Frank Chang
---
target/riscv/debug.c | 55 ++--
target/riscv/debug.h | 13 +++
2 files changed, 66 insertions(+), 2 deletions(-)
diff
From: Frank Chang
Type 2 trigger cannot be fired in VU/VS modes.
Signed-off-by: Frank Chang
---
target/riscv/debug.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index ab23566113..ce9ff15d75 100644
--- a/target/riscv/debug.c
+++ b
From: Frank Chang
Type 6 trigger is similar to a type 2 trigger, but provides additional
functionality and should be used instead of type 2 in newer
implementations.
Signed-off-by: Frank Chang
---
target/riscv/debug.c | 174 ++-
target/riscv/debug.h
From: Frank Chang
If the value written to tselect is greater than or equal to the number
of supported triggers, then the following reads of tselect would return
value 0.
Signed-off-by: Frank Chang
---
target/riscv/cpu.h | 1 +
target/riscv/debug.c | 6 ++
2 files changed, 7 insertions
On Thu, Feb 2, 2023 at 9:01 PM Alexandre Ghiti
wrote:
> Hi Frank,
>
> On Wed, Feb 1, 2023 at 4:49 PM Frank Chang wrote:
> >
> > On Tue, Jan 31, 2023 at 10:36 PM Alexandre Ghiti
> wrote:
> >>
> >> Currently, the max satp mode is set with the only constr
Reviewed-by: Frank Chang
On Fri, Feb 3, 2023 at 2:02 PM Alexandre Ghiti
wrote:
> Currently, the max satp mode is set with the only constraint that it must
> be
> implemented in QEMU, i.e. set in valid_vm_1_10_[32|64].
>
> But we actually need to add another level of constraint:
return "sv39";
> +case VM_1_10_MBARE:
> +return "none";
> +}
> +}
> +
> +g_assert_not_reached();
> +}
> +
> +/* Sets the satp mode to the max supported */
> +static void set_satp_mode_default_map(RISCVCPU *cpu
From: Frank Chang
The RVV specification does not require that the core needs to support
the privileged specification v1.12.0 to support RVV, and there is no
dependency from ISA level. This commit removes the restriction.
Signed-off-by: Frank Chang
---
target/riscv/csr.c | 21
I realized that I should also remove the privileged version check
in isa_edata_arr[], too.
I will send out v2 patch to fix it.
Regards,
Frank Chang
On Tue, Feb 7, 2023 at 4:43 PM wrote:
> From: Frank Chang
>
> The RVV specification does not require that the core needs to supp
From: Frank Chang
The RVV specification does not require that the core needs to support
the privileged specification v1.12.0 to support RVV, and there is no
dependency from ISA level.
This commit removes the restriction from both RVV CSRs and extension CPU
ISA string.
Signed-off-by: Frank
Reviewed-by: Frank Chang
On Thu, Feb 9, 2023 at 8:34 AM Alistair Francis <
alistair.fran...@opensource.wdc.com> wrote:
> From: Alistair Francis
>
> This patch adds some active RISC-V members as reviewers to the
> MAINTAINERS file.
>
> Signed-off-by: Alistair Francis
Reviewed-by: Frank Chang
On Mon, Feb 13, 2023 at 5:45 PM LIU Zhiwei
wrote:
> vslide1up_##BITWIDTH is used by the vslide1up.vx and vslide1up.vf. So its
> scalar input should be uint64_t to hold the 64 bits float register.And the
> same for vslide1down_##BITWIDTH.
>
> This bug is
Reviewed-by: Frank Chang
On Wed, Feb 22, 2023 at 2:46 AM Daniel Henrique Barboza <
dbarb...@ventanamicro.com> wrote:
> Commit 752614cab8e6 ("target/riscv: rvv: Add tail agnostic for vector
> load / store instructions") added code to set the tail elements to 1 in
> th
Reviewed-by: Frank Chang
On Tue, Feb 21, 2023 at 5:10 PM Weiwei Li wrote:
> The spec can be found in https://github.com/riscv/riscv-zicond.
> Two instructions are added:
> - czero.eqz: Moves zero to a register rd, if the condition rs2 is
>equal to zero, otherwise mov
Reviewed-by: Frank Chang
On Thu, Dec 15, 2022 at 11:09 PM Elta <503386...@qq.com> wrote:
> Should be cpu->cfg.elen in range [8, 64].
>
> Signed-off-by: Dongxue Zhang
> ---
> target/riscv/cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --
we add another helper function to wrap this for the "named" CPUs?
Regards,
Frank Chang
On Mon, Dec 12, 2022 at 6:23 PM Alexandre Ghiti
wrote:
> RISC-V specifies multiple sizes for addressable memory and Linux probes for
> the machine's support at startup via the satp CSR
From: Frank Chang
Currently, the implied extensions are enabled and checked in
riscv_cpu_validate_set_extensions(). However, the order of enabling the
implied extensions must follow a strict sequence, which is error-prone.
This patchset introduce extension implied rule helpers to enable the
From: Frank Chang
RISCVCPUImpliedExtsRule is created to store the implied rules.
'is_misa' flag is used to distinguish whether the rule is derived
from the MISA or other extensions.
'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores
the offs
From: Frank Chang
Introduce helpers to enable the extensions based on the implied rules.
The implied extensions are enabled recursively, so we don't have to
expand all of them manually. This also eliminates the old-fashioned
ordering requirement. For example, Zvksg implies Zvks, Zvks im
From: Frank Chang
Zc extension has special implied rules that need to be handled separately.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/tcg/tcg-cpu.c | 34 ++
1 file
From: Frank Chang
Remove the old-fashioned extension auto-update check statements as
they are replaced by the extension implied rules.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/tcg/tcg-cpu.c | 119
From: Frank Chang
Add multi extension implied rules to enable the implied extensions of
the multi extension recursively.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
Acked-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/cpu.c
From: Frank Chang
Add MISA extension implied rules to enable the implied extensions
of MISA recursively.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
Reviewed-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 50
}
> } else {
> -val &= ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB);
> +mask |= MSECCFG_RLB;
> +val &= ~(mask);
> }
>
> env->mseccfg = val;
> diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
> index f5c10ce85c..ccff0eb
static RISCVException write_menvcfg(CPURISCVState
> *env, int csrno,
> (cfg->ext_sstc ? MENVCFG_STCE : 0) |
> (cfg->ext_svadu ? MENVCFG_ADUE : 0);
> }
> +/* Update PMM field only if the value is valid according to Zjpm v0.8 */
> +if (((val &
From: Frank Chang
Remove the old-fashioned extension auto-update check statements as
they are replaced by the extension implied rules.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
---
target/riscv/tcg/tcg-cpu.c | 115 -
1 file changed, 115
From: Frank Chang
Introduce helpers to enable the extensions based on the implied rules.
The implied extensions are enabled recursively, so we don't have to
expand all of them manually. This also eliminates the old-fashioned
ordering requirement. For example, Zvksg implies Zvks, Zvks im
From: Frank Chang
Add standard extension implied rules to enable the implied extensions of
the standard extension recursively.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
---
target/riscv/cpu.c | 340 +
1 file changed, 340 insertions
From: Frank Chang
Add MISA extension implied rules to enable the implied extensions
of MISA recursively.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
---
target/riscv/cpu.c | 50 +-
1 file changed, 49 insertions(+), 1 deletion(-)
diff
From: Frank Chang
Currently, the implied extensions are enabled and checked in
riscv_cpu_validate_set_extensions(). However, the order of enabling the
implied extensions must follow a strict sequence, which is error-prone.
This patchset introduce extension implied rule helpers to enable the
From: Frank Chang
Zc extension has special implied rules that need to be handled separately.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
---
target/riscv/tcg/tcg-cpu.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/target/riscv/tcg/tcg
From: Frank Chang
RISCVCPUImpliedExtsRule is created to store the implied rules.
'is_misa' flag is used to distinguish whether the rule is derived
from the MISA or other extensions.
'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores
the offs
Reviewed-by: Frank Chang
Fea.Wang 於 2024年6月3日 週一 下午1:48寫道：
>
> Loading a description from memory may cause a bus-error. In this
> case, the DMA should stop working, set the error flag, and return
> the error value.
>
> Signed-off-by: Fea.Wang
> ---
> hw/
Reviewed-by: Frank Chang
Fea.Wang 於 2024年6月3日 週一 下午1:48寫道：
>
> When calling the loading a description function, it should be noticed
> that the function may return a failure value. Breaking the loop is one
> of the possible ways to handle it.
>
> Signed-off-by: Fea.Wan
Reviewed-by: Frank Chang
Fea.Wang 於 2024年6月3日 週一 下午1:49寫道：
>
> Due to a description loading failure, adding a trace log makes observing
> the DMA behavior easy.
>
> Signed-off-by: Fea.Wang
> ---
> hw/dma/trace-events| 3 +++
> hw/dma/xilinx_axidma.c | 3 +
Reviewed-by: Frank Chang
Fea.Wang 於 2024年6月3日 週一 下午1:48寫道：
>
> Fix the transmission return size because not all bytes could be
> transmitted successfully. So, return a successful length instead of a
> constant value.
>
> Signed-off-by: Fea.Wang
> ---
> hw/net/xilinx_ax
於 2024年6月3日 週一 下午2:06寫道：
>
> From: Frank Chang
>
> Introduce helpers to enable the extensions based on the implied rules.
> The implied extensions are enabled recursively, so we don't have to
> expand all of them manually. This also eliminates the old-fashioned
>
From: Frank Chang
Add MISA extension implied rules to enable the implied extensions
of MISA recursively.
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 50 +-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b
From: Frank Chang
Zc extension has special implied rules that need to be handled separately.
Signed-off-by: Frank Chang
---
target/riscv/tcg/tcg-cpu.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg
From: Frank Chang
Introduce helpers to enable the extensions based on the implied rules.
The implied extensions are enabled recursively, so we don't have to
expand all of them manually. This also eliminates the old-fashioned
ordering requirement. For example, Zvksg implies Zvks, Zvks im
From: Frank Chang
Currently, the implied extensions are enabled and checked in
riscv_cpu_validate_set_extensions(). However, the order of enabling the
implied extensions must follow a strict sequence, which is error-prone.
This patchset introduce extension implied rule helpers to enable the
From: Frank Chang
Add standard extension implied rules to enable the implied extensions of
the standard extension recursively.
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 340 +
1 file changed, 340 insertions(+)
diff --git a/target/riscv
From: Frank Chang
RISCVCPUImpliedExtsRule is created to store the implied rules.
'is_misa' flag is used to distinguish whether the rule is derived
from the MISA or other extensions.
'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores
the offs
From: Frank Chang
Remove the old-fashioned extension auto-update check statements as
they are replaced by the extension implied rules.
Signed-off-by: Frank Chang
---
target/riscv/tcg/tcg-cpu.c | 115 -
1 file changed, 115 deletions(-)
diff --git a/target
Patchset resend:
https://lists.gnu.org/archive/html/qemu-riscv/2024-06/msg00130.html
於 2024年6月3日 週一 下午2:07寫道：
> From: Frank Chang
>
> Currently, the implied extensions are enabled and checked in
> riscv_cpu_validate_set_extensions(). However, the order of enabling the
> imp
On Mon, May 13, 2024 at 8:37 PM Daniel Henrique Barboza <
dbarb...@ventanamicro.com> wrote:
> Hi Frank,
>
>
> On 5/8/24 08:15, Daniel Henrique Barboza wrote:
> > Hi Frank,
> >
> > I'll reply with that I've done so far. Still missing some stuff:
>
Reviewed-by: Frank Chang
On Thu, May 16, 2024 at 8:34 PM Jerry Zhang Jian
wrote:
> - According to RISC-V crypto spec, Zvkb extension is a proper subset of
> the Zvbb extension.
>
> - Reference:
> https://github.com/riscv/riscv-crypto/blob/1769c2609bf4535632e0c0fd715778f212bb
Hi Daniel,
On Tue, May 21, 2024 at 12:17 AM Daniel Henrique Barboza <
dbarb...@ventanamicro.com> wrote:
> Hi Frank,
>
> On 5/16/24 04:13, Frank Chang wrote:
> > On Mon, May 13, 2024 at 8:37 PM Daniel Henrique Barboza <
> dbarb...@ventanamicro.com <mailto:dba
gt; +.name = "riscv-iommu",
> +.unmigratable = 1
> +};
> +
> +static void riscv_iommu_pci_init(Object *obj)
> +{
> +RISCVIOMMUStatePci *s = RISCV_IOMMU_PCI(obj);
> +RISCVIOMMUState *iommu = &s->iommu;
> +
> +object_initialize_child(ob
Reviewed-by: Frank Chang
Daniel Henrique Barboza 於 2024年5月24日 週五 上午1:41寫道：
>
> From: Tomasz Jeznach
>
> Add PCIe Address Translation Services (ATS) capabilities to the IOMMU.
> This will add support for ATS translation requests in Fault/Event
> queues, Page-reque
Reviewed-by: Frank Chang
Daniel Henrique Barboza 於 2024年5月24日 週五 上午1:42寫道：
>
> From: Tomasz Jeznach
>
> DBG support adds three additional registers: tr_req_iova, tr_req_ctl and
> tr_response.
>
> The DBG cap is always enabled. No on/off toggle is provided for it.
>
Hi Alistair,
On Tue, Jun 11, 2024 at 9:35 AM Alistair Francis
wrote:
> On Wed, Jun 5, 2024 at 4:35 PM wrote:
> >
> > From: Frank Chang
> >
> > RISCVCPUImpliedExtsRule is created to store the implied rules.
> > 'is_misa' flag is used to distinguish wh
On Wed, Jun 5, 2024 at 2:32 PM wrote:
> From: Frank Chang
>
> Introduce helpers to enable the extensions based on the implied rules.
> The implied extensions are enabled recursively, so we don't have to
> expand all of them manually. This also eliminates the old-fashioned
&g
From: Frank Chang
Currently, the implied extensions are enabled and checked in
riscv_cpu_validate_set_extensions(). However, the order of enabling the
implied extensions must follow a strict sequence, which is error-prone.
This patchset introduce extension implied rule helpers to enable the
From: Frank Chang
Add standard extension implied rules to enable the implied extensions of
the standard extension recursively.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
Acked-by: Alistair Francis
---
target/riscv/cpu.c | 340
From: Frank Chang
Zc extension has special implied rules that need to be handled separately.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
---
target/riscv/tcg/tcg-cpu.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a
From: Frank Chang
Introduce helpers to enable the extensions based on the implied rules.
The implied extensions are enabled recursively, so we don't have to
expand all of them manually. This also eliminates the old-fashioned
ordering requirement. For example, Zvksg implies Zvks, Zvks im
From: Frank Chang
Add MISA extension implied rules to enable the implied extensions
of MISA recursively.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 50 +-
1
From: Frank Chang
Remove the old-fashioned extension auto-update check statements as
they are replaced by the extension implied rules.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
---
target/riscv/tcg/tcg-cpu.c | 119 -
1
From: Frank Chang
RISCVCPUImpliedExtsRule is created to store the implied rules.
'is_misa' flag is used to distinguish whether the rule is derived
from the MISA or other extensions.
'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores
the offs
Reviewed-by: Frank Chang
Max Chou 於 2024年6月14日 週五 上午1:52寫道：
>
> If there are not any QEMU plugin memory callback functions, checking
> before calling the qemu_plugin_vcpu_mem_cb function can reduce the
> function call overhead.
>
> Signed-off-by: Max Chou
> ---
> acc
On Fri, Jun 21, 2024 at 12:15 PM Alistair Francis
wrote:
> On Sun, Jun 16, 2024 at 12:48 PM wrote:
> >
> > From: Frank Chang
> >
> > Introduce helpers to enable the extensions based on the implied rules.
> > The implied extensions are enabled recursively, so w
gt; bool ext_smaia;
> bool ext_ssaia;
> +bool ext_smctr;
> +bool ext_ssctr;
Base on: https://github.com/riscv/riscv-control-transfer-records/pull/29
Smctr and Ssctr depend on both S-mode and Sscsrind.
We should add the implied rules for Smctr and Ssctr.
Regards,
Frank Chang
On Sun, Mar 6, 2022 at 7:42 AM Atish Kumar Patra
wrote:
>
>
> On Sat, Mar 5, 2022 at 10:05 AM Heiko Stuebner wrote:
>
>> Hi,
>>
>> Am Donnerstag, 3. März 2022, 19:58:38 CET schrieb Atish Patra:
>> > On Fri, Feb 25, 2022 at 11:46 PM Frank Chang
>> w
On Sun, Mar 6, 2022 at 2:12 PM Atish Kumar Patra
wrote:
>
>
> On Sat, Mar 5, 2022 at 9:36 PM Frank Chang wrote:
>
>> On Sun, Mar 6, 2022 at 7:42 AM Atish Kumar Patra
>> wrote:
>>
>>>
>>>
>>> On Sat, Mar 5, 2022 at 10:05 AM Heiko Stueb
Typo in patch title:
s/extenstion/extension/g
Regards,
Frank Chang
On Sat, Feb 26, 2022 at 3:45 PM Frank Chang wrote:
>
>
> Atish Patra 於 2022年2月23日 週三 上午6:39寫道：
>
>> The Linux kernel parses the ISA extensions from "riscv,isa" DT
>> property. It used to
ks that.
> So the "does not permit any"-part is wrong, therefore we should raise a
> store page fault.
>
> In fact, I can't predict what will happen, because the code in
> target/riscv/cpu_helper.c does
> not really prioritize page faults or PMP faults. it returns o
xmin
Also, I think "Zifencei" and "Zicsr" should also be covered as well,
and all extensions should follow the order defined in Table 28.11:
https://github.com/riscv/riscv-isa-manual/blob/master/src/naming.tex#L141
"The table also defines the canonical order in which ext
str + snprintf(isa_str, maxlen, "rv%d",
> TARGET_LONG_BITS);
> -for (i = 0; i < sizeof(riscv_exts); i++) {
> -if (cpu->env.misa_ext & RV(riscv_exts[i])) {
> -*p++ = qemu_tolower(riscv_exts[i]);
> +for (i = 0; i < sizeof(riscv_single_
On Fri, Mar 11, 2022 at 2:42 AM Atish Kumar Patra
wrote:
> On Wed, Mar 9, 2022 at 5:47 AM Frank Chang wrote:
> >
> > Atish Patra 於 2022年3月9日 週三 上午8:53寫道：
> >>
> >> The Linux kernel parses the ISA extensions from "riscv,isa" DT
> >> pr
t; },
> +[CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> +[CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32, read_hpmcounterh,
> + write_mhpmcounterh
> },
> #endif /* !CONFIG_USER_ONLY */
> };
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 2a48bcf81d3d..d706a97e65c8 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -300,6 +300,9 @@ const VMStateDescription vmstate_riscv_cpu = {
> VMSTATE_UINTTL(env.scounteren, RISCVCPU),
> VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
> VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
> +VMSTATE_UINTTL_ARRAY(env.mhpmcounter_val, RISCVCPU,
> RV_MAX_MHPMCOUNTERS),
> +VMSTATE_UINTTL_ARRAY(env.mhpmcounterh_val, RISCVCPU,
> RV_MAX_MHPMCOUNTERS),
> +VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU,
> RV_MAX_MHPMEVENTS),
> VMSTATE_UINTTL(env.sscratch, RISCVCPU),
> VMSTATE_UINTTL(env.mscratch, RISCVCPU),
> VMSTATE_UINT64(env.mfromhost, RISCVCPU),
> --
> 2.30.2
>
>
>
Hi Atish,
I encountered the compilation error when compiling user-mode QEMU
checked out from the branch in your repo:
error: ‘CPURISCVState {aka struct CPURISCVState}’ has no member named
‘mhpmevent_val’
error: ‘CPURISCVState {aka struct CPURISCVState}’ has no member named
‘mhpmeventh_val’
error: ‘CPURISCVState {aka struct CPURISCVState}’ has no member named
‘pmu_ctrs’
error: ‘CPURISCVState {aka struct CPURISCVState}’ has no member named ‘priv’
error: ‘CPURISCVState {aka struct CPURISCVState}’ has no member named
‘mcounteren’
Also, some functions are defined but not used in user-mode QEMU:
error: ‘read_scountovf’ defined but not used [-Werror=unused-function]
error: ‘write_mhpmcounterh’ defined but not used [-Werror=unused-function]
error: ‘write_mhpmcounter’ defined but not used [-Werror=unused-function]
... etc
I think you need to add the #if !defined(CONFIG_USER_ONLY) macros
to prevent using the variables which are available only in system-mode QEMU
and excluding the functions which are called only in system-mode QEMU.
Regards,
Frank Chang
de "exec/exec-all.h"
> #include "tcg/tcg-op.h"
> #include "trace.h"
> #include "semihosting/common-semi.h"
> +#include "cpu.h"
>
Redundant: #include "cpu.h"
Regards,
Frank Chang
> +#include "cpu_bits.h"
gt; + cpu->cfg.elen < 8)) {
> error_setg(errp,
> "Vector extension implementation only supports
> ELEN "
> "in the range [8, 64]");
>
;plugin", "output from TCG plugins\n"},
> #endif
> +{ CPU_LOG_TB_VU, "vu",
> + "include vector unit registers in the 'cpu' logging" },
> { LOG_STRACE, "strace",
>"log every user-mode syscall, its input, and its result" },
> { LOG_PER_THREAD, "tid",
> --
> 2.34.0
>
>
Reviewed-by: Frank Chang
From: Frank Chang
"mimpid" cpu option was mistyped to "mipid".
Fixes: 9951ba94 ("target/riscv: Support configuarable marchid, mvendorid, mipid
CSR values")
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 4 ++--
target/riscv/cpu.h | 2 +-
target/riscv/csr.c
From: Frank Chang
"mimpid" cpu option was mistyped to "mipid".
Fixes: 9951ba94 ("target/riscv: Support configuarable marchid, mvendorid, mipid
CSR values")
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 4 ++--
target/riscv/cp
counter_prev, PMUCTRState),
> VMSTATE_UINTTL(mhpmcounterh_prev, PMUCTRState),
> + VMSTATE_UINT8(write_done, PMUCTRState),
> VMSTATE_BOOL(started, PMUCTRState),
> VMSTATE_END_OF_LIST()
> }
> @@ -355,6 +356,9 @@ const VMStateDescription vmsta
break;
> -case CSR_INSTRETH:
> -if (!get_field(env->mcounteren, COUNTEREN_IR)) {
> -return RISCV_EXCP_ILLEGAL_INST;
> -}
> -break;
> -case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
> -
XT)
> #define MIP_SGEIP (1 << IRQ_S_GEXT)
> +#define MIP_LCOFIP (1 << IRQ_PMU_OVF)
>
> /* sip masks */
> #define SIP_SSIP MIP_SSIP
> #define SIP_STIP MIP_STIP
> #defin
if (isa_edata_arr[i].enabled) {
> +new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
> +g_free(old);
> +old = new;
> +}
> +}
> +
> +*isa_str = new;
> +}
> +
> char *riscv_isa_string(RISCVCPU *cpu)
> {
> int i;
> @@ -910,6 +969,7 @@ char *riscv_isa_string(RISCVCPU *cpu)
> }
> }
> *p = '\0';
> +riscv_isa_string_ext(cpu, &isa_str, maxlen);
> return isa_str;
> }
>
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
60 ++
> 1 file changed, 60 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ddda4906ffb7..937ccdda997b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -34,6 +34,11 @@
>
> /* RISC-V C
Reviewed-by: Frank Chang
On Fri, Mar 25, 2022 at 5:00 PM Weiwei Li wrote:
> LEN is not used for GEN_VEXT_VMV_WHOLE macro, so vmvr.v can share
> the same helper
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> ---
> target/riscv/helper.h
Reviewed-by: Frank Chang
On Fri, Mar 25, 2022 at 5:00 PM Weiwei Li wrote:
> for some cases, scale is always equal or less than 0, since lmul is not
> larger than 3
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> ---
> target/riscv/insn_trans/trans_rvv.c.
notifier:
4576704: arm/boot: split load_dtb() from arm_load_kernel()
ac9d32e: hw/arm/boot: arm_load_kernel implemented as a machine init done
notifier
Regards,
Frank Chang
On Thu, Mar 17, 2022 at 6:24 AM Tomasz Jeznach
wrote:
> Enable rivos-iommu device support in riscv:virt machine emulat
Hi Tomasz,
Could you please send this patchset to qemu-ri...@nongnu.org, too?
Regards,
Frank Chang
On Thu, Mar 17, 2022 at 6:24 AM Tomasz Jeznach
wrote:
> This is the series of patches to introduce RISC-V IOMMU emulation in QEMU.
>
> The Rivos IOMMU device implementation is based o
gt; +static const char riscv_single_letter_exts[] = "IEMAFDQLCBJTPVNH";
>
> What about K?
>
> Why not use IEMAFDQCBKJTPVNH instead?
>
> Alistair
>
The RISC-V ISA Manual (version 20191213) is quite old.
Where "L" was not removed and "K" was not i
From: Frank Chang
oprsz and maxsz are passed with the same value in commit: eee2d61e202.
However, vmv.v.v was missed in that commit and should pass the same
value as well in its tcg_gen_gvec_2_ptr() call.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
1 file
NaN && ft2 == NaN.
The IEEE 754 spec allows both implementation and some architecture such
as riscv choose different defintions in two spec versions.
(riscv-spec-v2.2 use original version, riscv-spec-20191213 changes to
alternative)
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
From: Chih-Min Chao
The sNaN propagation behavior has been changed since
cd20cee7 in https://github.com/riscv/riscv-isa-manual
Signed-off-by: Chih-Min Chao
---
target/riscv/fpu_helper.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/fpu_helper.c b/targ
n, riscv-spec-20191213 changes to
> alternative)
>
> Signed-off-by: Chih-Min Chao
> Signed-off-by: Frank Chang
> ---
> fpu/softfloat-parts.c.inc | 19 +++
> fpu/softfloat.c | 18 +-
> include/fpu/softfloat.h | 10 ++
, frs2, &env->fp_status);
> +return float64_maxnum_noprop(frs1, frs2, &env->fp_status);
> }
>
> uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1)
> --
> 2.25.1
>
>
>
I should add the cover letter for this series of patchset, will resend it.
Sorry for the confusion.
Regards,
Frank Chang
From: Frank Chang
In IEEE 754-2019, minNum, maxNum, minNumMag and maxNumMag are removed
and replaced with minimum, minimumNumber, maximum and maximumNumber.
minimumNumber/maximumNumber behavior for SNaN is changed to:
* If both operands are NaNs, a QNaN is returned.
* If either operand is a
From: Chih-Min Chao
The sNaN propagation behavior has been changed since
cd20cee7 in https://github.com/riscv/riscv-isa-manual
Signed-off-by: Chih-Min Chao
---
target/riscv/fpu_helper.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/fpu_helper.c b/targ
NaN && ft2 == NaN.
The IEEE 754 spec allows both implementation and some architecture such
as riscv choose different defintions in two spec versions.
(riscv-spec-v2.2 use original version, riscv-spec-20191213 changes to
alternative)
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
---
target/riscv/fpu_helper.c | 21 +
target/riscv/helper.h | 3 ++
target/riscv/insn32.decode| 3 ++
target/riscv/insn_trans
From: Frank Chang
Zfh - Half width floating point
Zfhmin - Subset of half width floating point
Zfh, Zfhmin v0.1 is now in public review period and is required by
RVV extension:
https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/63gDCinXTwE/m/871Wm9XIBQAJ
Zfh, Zfhmin can be enabled with
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
---
target/riscv/cpu.c| 1 +
target/riscv/cpu.h| 1 +
target/riscv/insn32.decode| 4 ++
target/riscv/insn_trans
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
---
target/riscv/fpu_helper.c | 67 +
target/riscv/helper.h | 12 +
target/riscv/insn32.decode| 19 ++
target/riscv/insn_trans
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