From: Frank Chang
Introduce the concepts of fractional LMUL for RVV 1.0.
In RVV 1.0, LMUL bits are contiguous in vtype register.
Also rearrange rvv bits in TB_FLAGS to skip MSTATUS_VS (0x600)
and MSTATUS_FS (0x6000) bits.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by
From: Frank Chang
Signed-off-by: Frank Chang
Acked-by: Alistair Francis
---
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 4 +++
target/riscv/insn_trans/trans_rvv.c.inc | 40 +
target/riscv/vector_helper.c| 21
From: Frank Chang
Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions is
moved to Section 11.4 in RVV v1.0 spec. Update the comment, no
functional changes.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
1 file
From: Frank Chang
For some vector instructions (e.g. vmv.s.x), the element is loaded with
sign-extended.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 32 +
1 file changed, 22
From: Frank Chang
Sign-extend vsaddu.vi immediate value.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv
Reviewed-by: Frank Chang
On Fri, May 19, 2023 at 2:23 PM Tommy Wu wrote:
> When we receive a packet from the xilinx_axienet and then try to s2mem
> through the xilinx_axidma, if the descriptor ring buffer is full in the
> xilinx axidma driver, we’ll assert the DMASR.HALTED in the
&
xt_svpbmt },
> +{ "svinval", cpu->cfg.ext_svinval },
> +{ "svnapot", cpu->cfg.ext_svnapot },
>
We still have other sub-extensions, e.g. Zfh, Zba, Zbb, Zbc, Zbs... etc.
Do you mind adding them as well?
Also, I think the order of ISA strings sho
On Fri, Jul 2, 2021 at 3:17 PM Alistair Francis
wrote:
> On Fri, Jul 2, 2021 at 4:11 PM LIU Zhiwei wrote:
> >
> >
> > On 2021/7/2 下午1:38, Alistair Francis wrote:
> > > On Thu, Jul 1, 2021 at 6:45 PM Frank Chang
> wrote:
> > >> LIU Zhiwei 於 2021年4月
On Tue, Feb 1, 2022 at 10:34 AM Alistair Francis
wrote:
> On Wed, Jan 26, 2022 at 7:55 PM wrote:
> >
> > From: Frank Chang
> >
> > RISC-V privilege spec defines that mtime is exposed as a memory-mapped
> > machine-mode read-write register. However, as QEMU
From: Frank Chang
RISC-V privilege spec defines that mtime is exposed as a memory-mapped
machine-mode read-write register. However, as QEMU uses host monotonic
timer as timer source, this makes mtime to be read-only in RISC-V
ACLINT.
This patch makes mtime to be writable by recording the time
From: Frank Chang
If device's MemoryRegion doesn't have .impl.[min|max]_access_size
declaration, the default access_size_min would be 1 byte and
access_size_max would be 4 bytes (see: softmmu/memory.c).
This will cause a 64-bit memory access to ACLINT to be splitted into
two 32-
From: Frank Chang
This patchset makes ACLINT mtime to be writable as RISC-V privilege
spec defines that mtime is exposed as a memory-mapped machine-mode
read-write register. Also, mtimecmp and mtime should be 32/64-bit memory
accessible registers.
This patchset is the updated verion of:
https
From: Frank Chang
RISC-V privilege spec defines that:
* In RV32, memory-mapped writes to mtimecmp modify only one 32-bit part
of the register.
* For RV64, naturally aligned 64-bit memory accesses to the mtime and
mtimecmp registers are additionally supported and are atomic.
It's pos
Anup Patel 於 2021年12月30日 週四 下午8:55寫道：
> From: Anup Patel
>
> The RISC-V AIA (Advanced Interrupt Architecture) defines a new
> interrupt controller for wired interrupts called APLIC (Advanced
> Platform Level Interrupt Controller). The APLIC is capabable of
> forwarding wired interupts to RISC-V
於 2021年12月29日 週三 上午10:35寫道：
> From: Frank Chang
>
> In RVV v1.0 spec, several Zve* vector extensions for embedded processors
> are defined in Chapter 18.2:
>
> https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#zve-vector-extensions-for-embedded-processors
>
>
On Tue, Jan 18, 2022 at 6:27 AM Alistair Francis
wrote:
> On Wed, Dec 29, 2021 at 12:34 PM wrote:
> >
> > From: Frank Chang
> >
> > All Zve* extensions support all vector load and store instructions,
> > except Zve64* extensions do not support EEW=64
From: Frank Chang
All Zve* extensions support the vector configuration instructions.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans
From: Frank Chang
In RVV v1.0 spec, several Zve* vector extensions for embedded processors
are defined in Chapter 18.2:
https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#zve-vector-extensions-for-embedded-processors
This patchset implements Zve32f and Zve64f extensions.
The port is
From: Frank Chang
Vector narrowing conversion instructions are provided to and from all
supported integer EEWs for Zve64f extension.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 9 ++---
1 file changed, 6 insertions(+), 3
From: Frank Chang
All Zve* extensions support all vector integer instructions,
except that the vmulh integer multiply variants that return the
high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx,
vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64*.
Signed-off-by: Frank
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c| 4
target/riscv/cpu.h| 1 +
target/riscv/cpu_helper.c | 5 -
target/riscv/csr.c| 6 +-
target/riscv/translate.c | 2 ++
5 files changed, 16 insertions(+), 2
From: Frank Chang
Zve32f extension requires the scalar processor to implement the F
extension and implement all vector floating-point instructions for
floating-point operands with EEW=32 (i.e., no widening floating-point
operations).
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
From: Frank Chang
Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve64f extension.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a
From: Frank Chang
Vector narrowing conversion instructions are provided to and from all
supported integer EEWs for Zve32f extension.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
1 file changed, 3 insertions(+)
diff --git a
From: Frank Chang
Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve32f extension.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv
From: Frank Chang
Zve64f extension requires the scalar processor to implement the F
extension and implement all vector floating-point instructions for
floating-point operands with EEW=32 (i.e., no widening floating-point
operations).
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
From: Frank Chang
All Zve* extensions support all vector load and store instructions,
except Zve64* extensions do not support EEW=64 for index values when
XLEN=32.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 19 +++
1 file changed, 15 insertions
From: Frank Chang
All Zve* extensions support all vector fixed-point arithmetic
instructions, except that vsmul.vv and vsmul.vx are not supported
for EEW=64 in Zve64*.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 27
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0898954c02..33c1df638b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -664,6 +664,7
From: Frank Chang
Vector widening conversion instructions are provided to and from all
supported integer EEWs for Zve64f extension.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 32 +++--
1 file changed, 25
From: Frank Chang
Vector widening conversion instructions are provided to and from all
supported integer EEWs for Zve32f extension.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 18 ++
1 file changed, 18 insertions
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2ba22503da..4bca1cd289 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -664,6 +664,7
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c| 4 ++--
target/riscv/cpu.h| 1 +
target/riscv/cpu_helper.c | 2 +-
target/riscv/csr.c| 2 +-
target/riscv/translate.c | 2 ++
5 files changed, 7 insertions(+), 4
From: Frank Chang
All Zve* extensions support the vector configuration instructions.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans
From: Frank Chang
In SPI-mode, type B ("cleared on valid command") clear condition is not
supported, and as the "In idle state" bit in SPI-mode has type A
("according to current state") clear condition, the CURRENT_STATE bits
in an SPI-mode response should be
;> irq;
> +while (pending) {
> +prio = iprio[irq];
> +if (!prio) {
> +if (irq == extirq) {
> +prio = extirq_def_prio;
> +} else {
> +prio = (riscv_cpu_default_priority(irq) <
> extirq_def_prio) ?
>
Anup Patel 於 2022年1月18日 週二 上午11:41寫道：
> On Tue, Jan 18, 2022 at 9:04 AM Frank Chang
> wrote:
> >
> > Anup Patel 於 2022年1月17日 週一 下午10:28寫道：
> >>
> >> From: Anup Patel
> >>
> >> The AIA spec defines programmable 8-bit priority for each loca
cv_imsic.h
> @@ -0,0 +1,68 @@
> +/*
> + * RISC-V IMSIC (Incoming Message Signal Interrupt Controller) interface
> + *
> + * Copyright (c) 2021 Western Digital Corporation or its affiliates.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
> for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef HW_RISCV_IMSIC_H
> +#define HW_RISCV_IMSIC_H
> +
> +#include "hw/sysbus.h"
> +#include "qom/object.h"
> +
> +#define TYPE_RISCV_IMSIC "riscv.imsic"
> +
> +typedef struct RISCVIMSICState RISCVIMSICState;
> +DECLARE_INSTANCE_CHECKER(RISCVIMSICState, RISCV_IMSIC, TYPE_RISCV_IMSIC)
> +
> +#define IMSIC_MMIO_PAGE_SHIFT 12
> +#define IMSIC_MMIO_PAGE_SZ (1UL << IMSIC_MMIO_PAGE_SHIFT)
> +#define IMSIC_MMIO_SIZE(__num_pages) ((__num_pages) *
> IMSIC_MMIO_PAGE_SZ)
> +
> +#define IMSIC_MMIO_HART_GUEST_MAX_BTIS 6
> +#define IMSIC_MMIO_GROUP_MIN_SHIFT 24
> +
> +#define IMSIC_HART_NUM_GUESTS(__guest_bits) \
> +(1U << (__guest_bits))
> +#define IMSIC_HART_SIZE(__guest_bits) \
> +(IMSIC_HART_NUM_GUESTS(__guest_bits) * IMSIC_MMIO_PAGE_SZ)
> +#define IMSIC_GROUP_NUM_HARTS(__hart_bits)\
> +(1U << (__hart_bits))
> +#define IMSIC_GROUP_SIZE(__hart_bits, __guest_bits) \
> +(IMSIC_GROUP_NUM_HARTS(__hart_bits) * IMSIC_HART_SIZE(__guest_bits))
> +
> +struct RISCVIMSICState {
> +/*< private >*/
> +SysBusDevice parent_obj;
> +qemu_irq *external_irqs;
> +
> +/*< public >*/
> +MemoryRegion mmio;
> +uint32_t num_eistate;
> +uint32_t *eidelivery;
> +uint32_t *eithreshold;
> +uint32_t *eistate;
> +
> +/* config */
> +bool mmode;
> +uint32_t hartid;
> +uint32_t num_pages;
> +uint32_t num_irqs;
> +};
> +
> +DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode,
> +uint32_t num_pages, uint32_t num_ids);
> +
> +#endif
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
= { "sieh", aia_smode32, NULL, NULL, rmw_sieh },
> [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph },
> @@ -2937,6 +3133,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> /* VS-Level Interrupts (H-extension with AIA) */
> [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi },
>
> +/* VS-Level IMSIC Interface (H-extension with AIA) */
> +[CSR_VSSETEIPNUM] = { "vsseteipnum", aia_hmode, NULL, NULL,
> rmw_xsetclreinum },
> +[CSR_VSCLREIPNUM] = { "vsclreipnum", aia_hmode, NULL, NULL,
> rmw_xsetclreinum },
> +[CSR_VSSETEIENUM] = { "vsseteienum", aia_hmode, NULL, NULL,
> rmw_xsetclreinum },
> +[CSR_VSCLREIENUM] = { "vsclreienum", aia_hmode, NULL, NULL,
> rmw_xsetclreinum },
> +[CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL,
> rmw_xtopei },
> +
> /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
> [CSR_HIDELEGH]= { "hidelegh",aia_hmode32, NULL, NULL,
> rmw_hidelegh },
> [CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero,
> write_ignore },
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
id)
> +{
> +type_register_static(&riscv_aplic_info);
> +}
> +
> +type_init(riscv_aplic_register_types)
> +
> +/*
> + * Add a APLIC device to another APLIC device as child for
> + * interrupt delegation.
> + */
> +void riscv_aplic_add_child(DeviceState *parent, DeviceState *child)
> +{
> +RISCVAPLICState *caplic, *paplic;
> +
> +assert(parent && child);
> +caplic = RISCV_APLIC(child);
> +paplic = RISCV_APLIC(parent);
> +
> +assert(paplic->num_irqs == caplic->num_irqs);
> +assert(paplic->num_children <= QEMU_APLIC_MAX_CHILDREN);
> +
> +caplic->parent = paplic;
> +paplic->children[paplic->num_children] = caplic;
> +paplic->num_children++;
> +}
> +
> +/*
> + * Create APLIC device.
> + */
> +DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
> +uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources,
> +uint32_t iprio_bits, bool msimode, bool mmode, DeviceState *parent)
> +{
> +DeviceState *dev = qdev_new(TYPE_RISCV_APLIC);
> +uint32_t i;
> +
> +assert(num_harts < APLIC_MAX_IDC);
> +assert((APLIC_IDC_BASE + (num_harts * APLIC_IDC_SIZE)) <= size);
> +assert(num_sources < APLIC_MAX_SOURCE);
> +assert(APLIC_MIN_IPRIO_BITS <= iprio_bits);
> +assert(iprio_bits <= APLIC_MAX_IPRIO_BITS);
> +
> +qdev_prop_set_uint32(dev, "aperture-size", size);
> +qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
> +qdev_prop_set_uint32(dev, "num-harts", num_harts);
> +qdev_prop_set_uint32(dev, "iprio-mask", ((1U << iprio_bits) - 1));
> +qdev_prop_set_uint32(dev, "num-irqs", num_sources + 1);
> +qdev_prop_set_bit(dev, "msimode", msimode);
> +qdev_prop_set_bit(dev, "mmode", mmode);
> +
> +sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
> +sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
> +
> +if (parent) {
> +riscv_aplic_add_child(parent, dev);
> +}
> +
> +if (!msimode) {
> +for (i = 0; i < num_harts; i++) {
> +CPUState *cpu = qemu_get_cpu(hartid_base + i);
> +
> +qdev_connect_gpio_out_named(dev, NULL, i,
> +qdev_get_gpio_in(DEVICE(cpu),
> +(mmode) ? IRQ_M_EXT :
> IRQ_S_EXT));
> +}
> +}
> +
> +return dev;
> +}
> diff --git a/include/hw/intc/riscv_aplic.h b/include/hw/intc/riscv_aplic.h
> new file mode 100644
> index 00..de8532fbc3
> --- /dev/null
> +++ b/include/hw/intc/riscv_aplic.h
> @@ -0,0 +1,79 @@
> +/*
> + * RISC-V APLIC (Advanced Platform Level Interrupt Controller) interface
> + *
> + * Copyright (c) 2021 Western Digital Corporation or its affiliates.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
> for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef HW_RISCV_APLIC_H
> +#define HW_RISCV_APLIC_H
> +
> +#include "hw/sysbus.h"
> +#include "qom/object.h"
> +
> +#define TYPE_RISCV_APLIC "riscv.aplic"
> +
> +typedef struct RISCVAPLICState RISCVAPLICState;
> +DECLARE_INSTANCE_CHECKER(RISCVAPLICState, RISCV_APLIC, TYPE_RISCV_APLIC)
> +
> +#define APLIC_MIN_SIZE0x4000
> +#define APLIC_SIZE_ALIGN(__x) (((__x) + (APLIC_MIN_SIZE - 1)) & \
> + ~(APLIC_MIN_SIZE - 1))
> +#define APLIC_SIZE(__num_harts) (APLIC_MIN_SIZE + \
> + APLIC_SIZE_ALIGN(32 * (__num_harts)))
> +
> +struct RISCVAPLICState {
> +/*< private >*/
> +SysBusDevice parent_obj;
> +qemu_irq *external_irqs;
> +
> +/*< public >*/
> +MemoryRegion mmio;
> +uint32_t bitfield_words;
> +uint32_t domaincfg;
> +uint32_t mmsicfgaddr;
> +uint32_t mmsicfgaddrH;
> +uint32_t smsicfgaddr;
> +uint32_t smsicfgaddrH;
> +uint32_t genmsi;
> +uint32_t *sourcecfg;
> +uint32_t *state;
> +uint32_t *target;
> +uint32_t *idelivery;
> +uint32_t *iforce;
> +uint32_t *ithreshold;
> +
> +/* topology */
> +#define QEMU_APLIC_MAX_CHILDREN16
> +struct RISCVAPLICState *parent;
> +struct RISCVAPLICState *children[QEMU_APLIC_MAX_CHILDREN];
> +uint16_t num_children;
> +
> +/* config */
> +uint32_t aperture_size;
> +uint32_t hartid_base;
> +uint32_t num_harts;
> +uint32_t iprio_mask;
> +uint32_t num_irqs;
> +bool msimode;
> +bool mmode;
> +};
> +
> +void riscv_aplic_add_child(DeviceState *parent, DeviceState *child);
> +
> +DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
> +uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources,
> +uint32_t iprio_bits, bool msimode, bool mmode, DeviceState *parent);
> +
> +#endif
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
; forwarding wired interupts to RISC-V HARTs directly or as MSIs
> (Message Signaled Interupts).
>
> This patch adds device emulation for RISC-V AIA APLIC.
>
> Signed-off-by: Anup Patel
> Signed-off-by: Anup Patel
> Reviewed-by: Frank Chang
> ---
> hw/intc/Kconfig
t; +irqs, env->siprio);
> +}
> +
> +/* Check VS-mode interrupts */
> +irqs = pending & env->mideleg & env->hideleg & -vsie;
> +if (irqs) {
> +virq = riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S,
> +irqs >> 1, env->hviprio);
> +return (virq <= 0) ? virq : virq + 1;
> +}
> +
> +/* Indicate no pending interrupt */
> +return RISCV_EXCP_NONE;
> }
>
> bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 39b5dbc36b..92536c4a0e 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -92,6 +92,7 @@ static const VMStateDescription vmstate_hyper = {
> VMSTATE_UINTTL(env.hgeie, RISCVCPU),
> VMSTATE_UINTTL(env.hgeip, RISCVCPU),
> VMSTATE_UINT64(env.htimedelta, RISCVCPU),
> +VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64),
>
> VMSTATE_UINT64(env.vsstatus, RISCVCPU),
> VMSTATE_UINTTL(env.vstvec, RISCVCPU),
> @@ -223,6 +224,8 @@ const VMStateDescription vmstate_riscv_cpu = {
> .fields = (VMStateField[]) {
> VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
> VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
> +VMSTATE_UINT8_ARRAY(env.miprio, RISCVCPU, 64),
> +VMSTATE_UINT8_ARRAY(env.siprio, RISCVCPU, 64),
> VMSTATE_UINTTL(env.pc, RISCVCPU),
> VMSTATE_UINTTL(env.load_res, RISCVCPU),
> VMSTATE_UINTTL(env.load_val, RISCVCPU),
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
On Thu, Jan 20, 2022 at 12:20 AM Anup Patel wrote:
> Hi Frank,
>
> On Wed, Jan 19, 2022 at 9:07 PM Frank Chang
> wrote:
> >
> > On Wed, Jan 19, 2022 at 11:27 PM Anup Patel wrote:
> >>
> >> From: Anup Patel
> >>
> >> The RISC-V AIA (A
On Thu, Jan 20, 2022 at 8:05 PM Anup Patel wrote:
> On Thu, Jan 20, 2022 at 1:49 PM Frank Chang
> wrote:
> >
> > On Thu, Jan 20, 2022 at 12:20 AM Anup Patel wrote:
> >>
> >> Hi Frank,
> >>
> >> On Wed, Jan 19, 2022 at 9:07 PM Frank Chang
&
From: Frank Chang
In SPI-mode, unlike SD-mode, card status bits: ILLEGAL_COMMAND and
COM_CRC_ERROR have type C ("cleared by read") clear conditions.
Also, type B ("cleared on valid command") clear condition is not
supported in SPI-mode. As the "In idle state&qu
On Tue, Jan 18, 2022 at 10:35 AM wrote:
> From: Frank Chang
>
> In SPI-mode, type B ("cleared on valid command") clear condition is not
> supported, and as the "In idle state" bit in SPI-mode has type A
> ("according to current state") clear condi
From: Frank Chang
In SPI-mode, CMD58 returns R3 response with the format:
39 32 31 0
++ +---+
| R1 | |OCR|
++ +---+
Where R1
From: Frank Chang
RISC-V privilege spec defines that mtime is exposed as a memory-mapped
machine-mode read-write register. However, as QEMU uses host monotonic
timer as timer source, this makes mtime to be read-only in RISC-V
ACLINT.
This patch makes mtime to be writable by recording the time
From: Frank Chang
* Add vrgatherei16.vv instruction.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 4
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.c.inc | 27 ++---
target
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 92a0e6fe51e..f61eaf7c6ba
From: Frank Chang
For some vector instructions (e.g. vmv.s.x), the element is loaded with
sign-extended.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 32 +
1 file changed, 22
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 26 ++---
target/riscv/insn32.decode | 14 ++---
target/riscv/insn_trans/trans_rvv.c.inc | 33 +++
target/riscv
From: Frank Chang
* Remove "vmv.s.x: dothing if rs1 == 0" constraint.
* Add vmv.x.s instruction.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Acked-by: Alistair Francis
---
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvv.
From: Frank Chang
Add the following instructions:
* vaaddu.vv
* vaaddu.vx
* vasubu.vv
* vasubu.vx
Remove the following instructions:
* vadd.vi
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 16 ++
target/riscv/insn32.decode
From: Frank Chang
NaN-boxed the scalar floating-point register based on RVV 1.0's rules.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 6 +++---
target/riscv/insn_trans/trans_rvv.c.inc | 5 -
target/riscv/vector_helper.c| 4
3 files changed, 7 insertions
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index a3f1101cd63..7548b71efdb 100644
--- a/target/riscv
From: Frank Chang
* Only do carry-in or borrow-in if is masked (vm=0).
* Remove clear function from helper functions as the tail elements
are unchanged in RVV 1.0.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 20
From: Frank Chang
Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_
From: Frank Chang
Sign-extend vsaddu.vi immediate value.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv
From: Frank Chang
NaN-boxed the scalar floating-point register based on RVV 1.0's rules.
Signed-off-by: Frank Chang
Acked-by: Alistair Francis
---
target/riscv/insn32.decode | 4 +--
target/riscv/insn_trans/trans_rvv.c.inc | 38 -
target/
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/vector_helper.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 277a5e4120a..71d7b1e8796 100644
--- a/target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 12 +---
target/riscv/vector_helper.c| 12 ++--
2 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/target/riscv/insn_trans
From: Frank Chang
* Sign-extend vmselu.vi and vmsgtu.vi immediate values.
* Remove "set tail elements to zeros" as tail elements can be unchanged
for either VTA to have undisturbed or agnostic setting.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/
From: Frank Chang
Add the following instructions:
* vzext.vf2
* vzext.vf4
* vzext.vf8
* vsext.vf2
* vsext.vf4
* vsext.vf8
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 14 +
target/riscv/insn32.decode | 8
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
target/riscv/vector_helper.c| 4
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target
From: Frank Chang
* Update and check vstart value for vector instructions.
* Add whole register move instruction helper functions as we have to
call helper function for case where vstart is not zero.
* Remove probe_pages() calls in vector load/store instructions
(except fault-only-first
From: Frank Chang
Add the following instructions:
* vmv1r.v
* vmv2r.v
* vmv4r.v
* vmv8r.v
Signed-off-by: Frank Chang
Acked-by: Alistair Francis
---
target/riscv/insn32.decode | 4
target/riscv/insn_trans/trans_rvv.c.inc | 25 +
2 files changed, 29
From: Frank Chang
Add the following instructions:
* vfslide1up.vf
* vfslide1down.vf
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 7 ++
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvv.c.inc | 16
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 1 -
target/riscv/insn_trans/trans_rvv.c.inc | 23 ---
2 files changed, 24 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32
From: Frank Chang
Implement the floating-point reciprocal square-root estimate to 7 bits
instruction.
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 4 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 24 ++--
target/riscv/insn32.decode | 12 +++---
target/riscv/insn_trans/trans_rvv.c.inc | 12 +++---
target/riscv/vector_helper.c| 52
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 24 +++---
target/riscv/insn32.decode | 12 +++
target/riscv/insn_trans/trans_rvv.c.inc | 42 -
target/riscv
From: Frank Chang
helper_set_rounding_mode() is responsible for SIGILL, and "round to odd"
should be an interface private to translation, so add a new independent
helper_set_rod_rounding_mode().
Signed-off-by: Frank Chang
Acked-by: Alistair Francis
---
target/riscv/fpu_he
From: Frank Chang
Implement the floating-point reciprocal estimate to 7 bits instruction.
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 4 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
target/riscv
From: Frank Chang
* Remove clear function from helper functions as the tail elements
are unchanged in RVV 1.0.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/vector_helper.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 22 ---
target/riscv/insn32.decode | 7 -
target/riscv/insn_trans/trans_rvv.c.inc | 9 --
target/riscv/vector_helper.c| 205
From: Frank Chang
Signed-off-by: Frank Chang
Acked-by: Alistair Francis
---
target/riscv/helper.h | 22 -
target/riscv/insn32.decode | 15 ---
target/riscv/insn_trans/trans_rvv.c.inc | 59 +
target/riscv/vector_helper.c
From: Frank Chang
Add supports of Vector unit-stride mask load/store instructions
(vlm.v, vsm.v), which has:
evl (effective vector length) = ceil(env->vl / 8).
The new instructions operate the same as unmasked byte loads and stores.
Add evl parameter to reuse vext_ldst_us().
Signed-off
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 6 --
target/riscv/insn32.decode | 2 --
target/riscv/insn_trans/trans_rvv.c.inc | 2 --
target/riscv/vector_helper.c| 7 ---
4 files
From: Frank Chang
If the frm field contains an invalid rounding mode (101-111),
attempting to execute any vector floating-point instruction, even
those that do not depend on the rounding mode, will raise an illegal
instruction exception.
Call gen_set_rm() with DYN rounding mode to check and
From: Frank Chang
log(SEW) truncate vssra.vi immediate value.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/vector_helper.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index aed230e1ad8
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/fpu_helper.c | 12 ++--
target/riscv/insn_trans/trans_rvv.c.inc | 18 +-
target/riscv/internals.h| 9 +
3 files changed, 24 insertions
From: Frank Chang
Add the following instructions:
* vfcvt.rtz.xu.f.v
* vfcvt.rtz.x.f.v
Also adjust GEN_OPFV_TRANS() to accept multiple floating-point rounding
modes.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 11 ++--
target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
target/riscv/vector_helper.c| 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a
From: Hsiangkai Wang
Signed-off-by: Hsiangkai Wang
Signed-off-by: Greentime Hu
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 2 +
target/riscv/cpu.h | 1 +
target/riscv/gdbstub.c | 184 +
3 files changed, 187 insertions(+)
diff --git
From: Frank Chang
Add the following instructions:
* vfwcvt.rtz.xu.f.v
* vfwcvt.rtz.x.f.v
Also adjust GEN_OPFV_WIDEN_TRANS() to accept multiple floating-point
rounding modes.
Signed-off-by: Frank Chang
Acked-by: Alistair Francis
---
target/riscv/helper.h | 2 +
target
From: Frank Chang
Rename r2_zimm to r2_zimm11 for the upcoming vsetivli instruction.
vsetivli has 10-bits of zimm but vsetvli has 11-bits of zimm.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 4 ++--
target/riscv/insn32.decode | 4 ++--
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
target/riscv/vector_helper.c| 4 ++--
4 files
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.c.inc | 27 +
2 files changed, 29 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 4 +++
target/riscv/insn_trans/trans_rvv.c.inc | 40 +
target/riscv/vector_helper.c| 21 +
4 files
From: Frank Chang
Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions is
moved to Section 11.4 in RVV v1.0 spec. Update the comment, no
functional changes.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
1 file
On Fri, Oct 22, 2021 at 12:30 AM wrote:
> From: Frank Chang
>
> Zfh - Half width floating point
> Zfhmin - Subset of half width floating point
>
> Zfh, Zfhmin v0.1 is now in public review period and is required by
> RVV extension:
>
> https://groups.google.com/a/g
*val = ctr_val;
> +}
>
> return RISCV_EXCP_NONE;
> }
>
> static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong
> *val)
> {
> -int ctr_index;
> +uint16_t ctr_index;
>
> if (env->priv == PRV_M) {
> -
Reviewed-by: Frank Chang
On Sat, May 14, 2022 at 6:15 AM Atish Patra wrote:
> timecmp update function should be invoked with hartid for which
> timecmp is being updated. The following patch passes the incorrect
> hartid to the update function.
>
> Fixes: e2f01f3c2e13 ("
On Fri, May 13, 2022 at 11:58 PM Atish Kumar Patra
wrote:
> On Thu, May 12, 2022 at 11:29 PM Frank Chang
> wrote:
> >
> > On Thu, May 12, 2022 at 6:01 AM Atish Patra wrote:
> >>
> >> From: Atish Patra
> >>
> >> mcycle/minstret are actually
From: Frank Chang
"mimpid" cpu option was mistyped to "mipid".
Fixes commit: 9951ba94
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 4 ++--
target/riscv/cpu.h | 2 +-
target/riscv/csr.c | 8
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/
On Sat, Oct 16, 2021 at 4:54 PM wrote:
> From: Chih-Min Chao
>
> The sNaN propagation behavior has been changed since
> cd20cee7 in https://github.com/riscv/riscv-isa-manual.
>
> Signed-off-by: Chih-Min Chao
> Signed-off-by: Frank Chang
> ---
> tar
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