n top of the register region for this purpose.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Francisco Iglesias
> ---
> include/hw/watchdog/wdt_aspeed.h | 1 +
> hw/watchdog/wdt_aspeed.c | 6 +-
> 2 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --gi
SoC models for
> consistency.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Francisco Iglesias
> ---
> hw/arm/aspeed_ast2600.c | 36 ++--
> hw/arm/aspeed_soc.c | 36 ++--
> 2 files changed, 36 insertions
ainer is cleaner.
>
> Cc: Philippe Mathieu-Daudé
> Signed-off-by: Cédric Le Goater
Reviewed-by: Francisco Iglesias
> ---
> include/hw/ssi/aspeed_smc.h | 2 +-
> hw/ssi/aspeed_smc.c | 11 +++
> 2 files changed, 8 insertions(+), 5 deletions(-)
>
> diff
es removing one stray useless setting of
> minimum_version_id_old in a VMStateDescription with no load_state_old
> function, which crept in after the global weeding-out of them in
> commit 17e313406126.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Francisco Iglesias
> ---
&g
the same values)
Otherwise:
Reviewed-by: Francisco Iglesias
Best regards,
Francisco Iglesias
>
> Signed-off-by: Anton Kochkov
> Resolves: https://gitlab.com/qemu-projects/qemu/-/issues/1123
> ---
> hw/net/can/xlnx-zynqmp-can.c | 32
> 1
s->needed_bytes = 2;
> +if (s->write_enable) {
> +if (get_man(s) == MAN_NUMONYX) {
> +s->needed_bytes = 2;
> + } else if (get_man(s) == MAN_MICRON) {
> +s->needed_bytes += get_addr_length(s);
> +
ap: 6
Fix by adding the missing Kconfig dependency.
Fixes: acc0b8b05a ("hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers")
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Francisco Iglesias
---
hw/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm
On [2022 Oct 21] Fri 22:47:46, Vikram Garhwal wrote:
> Signed-off-by: Vikram Garhwal
> Reviewed-by: Peter Maydell
Reviewed-by: Francisco Iglesias
> ---
> MAINTAINERS | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/MAINTAINERS b/MAINTAINE
e with CANFD frame.
>
> Signed-off-by: Vikram Garhwal
> Acked-by: Thomas Huth
Reviewed-by: Francisco Iglesias
> ---
> tests/qtest/meson.build | 1 +
> tests/qtest/xlnx-canfd-test.c | 422 ++
> 2 files changed, 423 insertions(+)
>
Hi Vikram,
In the git summary s/zynqmp/versal/.
On [2022 Oct 21] Fri 22:47:44, Vikram Garhwal wrote:
> Connect CANFD0 and CANFD1 on the Versal-virt machine and update
> xlnx-versal-virt
> document with CANFD command line examples.
>
> Signed-off-by: Vikram Garhwal
> ---
> docs/system/arm/xlnx
On [2022 Sep 09] Fri 23:12:48, Vikram Garhwal wrote:
> Signed-off-by: Vikram Garhwal
Reviewed-by: Francisco Iglesias
> ---
> MAINTAINERS | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1729c0901c..1d45
Provide the Micron Xccela flash mt35xu01g with Octal command support.
Signed-off-by: Francisco Iglesias
---
hw/block/m25p80.c | 57 +++
1 file changed, 57 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index a8d2519141..79e26424ec
te *d)
> {
> Flash *s = M25P80(d);
>
> +s->wp_level = true;
> +s->status_register_write_disabled = false;
> +
> reset_memory(s);
> }
>
> @@ -1601,6 +1636,8 @@ static const VMStateDescription vmstate_m25p80 = {
> VMSTATE_U
Hi Iris,
On [2022 Jun 17] Fri 15:02:45, Iris Chen wrote:
> Signed-off-by: Iris Chen
> ---
> Thanks everyone for your comments. This is a v3 patch that addresses all
> suggestions (moving write_enable to decode_new_cmd).
> I am waiting on some feedback from Dan's (dz4l...@gmail.com) patch
> rega
FFF; /* StandBy state SO shall be HiZ */
0xFF should be enough here (since we are dealing with 8 bits, e.g.
m25p80_transfer8). More safe is probably to return 0 though and see this as if
a pulldown was connected to the line instead (this because r has been default
to 0 and was the most likely r
Brown
Reviewed-by: Francisco Iglesias
> ---
> hw/net/can/xlnx-versal-canfd.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/net/can/xlnx-versal-canfd.c b/hw/net/can/xlnx-versal-canfd.c
> index ad0c4da3c8..8968672b84 100644
> --- a/hw/net/can/xl
; bit 0 when applying it, resulting in the IRQ never being delivered.
>
> Signed-off-by: Doug Brown
Reviewed-by: Francisco Iglesias
> ---
> hw/net/can/xlnx-versal-canfd.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/net/can/xlnx-versal-canfd.c
gt; #9 0x55ec8d65c81d in qmp_device_list_properties qom/qom-qmp-cmds.c:144:11
>
> Signed-off-by: Peter Maydell
Reviewed-by: Francisco Iglesias
> ---
> hw/misc/xlnx-versal-cfu.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/hw/misc/xlnx-versal-cfu.c
55f225b0bfe1 in object_new qom/object.c:797:12
> #9 0x55f226309e0d in qmp_device_list_properties qom/qom-qmp-cmds.c:144:11
>
> Signed-off-by: Peter Maydell
Reviewed-by: Francisco Iglesias
> ---
> include/hw/nvram/xlnx-versal-efuse.h | 1 +
> hw/nvram/xlnx-versal-efuse-ct
87aa11 in object_new qom/object.c:797:12
> #9 0x56415507883d in qmp_device_list_properties qom/qom-qmp-cmds.c:144:11
>
> Signed-off-by: Peter Maydell
Reviewed-by: Francisco Iglesias
> ---
> include/hw/nvram/xlnx-bbram.h | 1 +
> hw/nvram/xlnx-bbram.c | 13 ++---
> 2 files cha
533c01 in object_new qom/object.c:797:12
> #9 0x55f402d31a2d in qmp_device_list_properties qom/qom-qmp-cmds.c:144:11
>
> Signed-off-by: Peter Maydell
Reviewed-by: Francisco Iglesias
> ---
> include/hw/nvram/xlnx-zynqmp-efuse.h | 1 +
> hw/nvram/xlnx-zynqmp-efuse.c |
df1 in object_new qom/object.c:797:12
> #9 0x558432427c1d in qmp_device_list_properties qom/qom-qmp-cmds.c:144:11
>
> Signed-off-by: Peter Maydell
Reviewed-by: Francisco Iglesias
> ---
> include/hw/misc/xlnx-versal-trng.h | 1 +
> hw/misc/xlnx-versal-trng.c | 6 +++---
> 2 files c
55f225b0bfe1 in object_new qom/object.c:797:12
> #9 0x55f226309e0d in qmp_device_list_properties qom/qom-qmp-cmds.c:144:11
>
> Signed-off-by: Peter Maydell
Reviewed-by: Francisco Iglesias
> ---
> include/hw/nvram/xlnx-versal-efuse.h | 1 +
> hw/nvram/xlnx-versal-efuse-ct
_frame for all of its ID registers. Correct this problem for
> both RX and TX, including RX filtering.
>
> Signed-off-by: Doug Brown
Reviewed-by: Francisco Iglesias
> ---
> hw/net/can/xlnx-versal-canfd.c | 53 --
> 1 file changed, 50 insertions
the tx queue"
Reviewed-by: Francisco Iglesias
BR,
F
> ---
> hw/net/can/xlnx-versal-canfd.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/hw/net/can/xlnx-versal-canfd.c b/hw/net/can/xlnx-versal-canfd.c
> index 47a14cfe63..5f083c21e9 100644
>
On Thu, Jun 20, 2024 at 04:11:37PM +0530, Sai Pavan Boddu wrote:
> boot-mode property sets user values into BOOT_MODE register, on hardware
> these are derived from board switches.
>
> Signed-off-by: Sai Pavan Boddu
Reviewed-by: Francisco Iglesias
> Reviewed-by: Edgar E. Iglesi
On Thu, Jun 20, 2024 at 04:11:39PM +0530, Sai Pavan Boddu wrote:
> Added the supported device list and an example command.
>
> Signed-off-by: Sai Pavan Boddu
Reviewed-by: Francisco Iglesias
> Reviewed-by: Edgar E. Iglesias
> ---
> MAINTAINERS | 1 +
>
mc = MACHINE_CLASS(oc);
> +ObjectProperty *prop;
> mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
> mc->init = zynq_init;
> mc->max_cpus = ZYNQ_MAX_CPUS;
> @@ -379,6 +404,12 @@ static void zynq_machine_class_init(ObjectCla
both the TX and RX code to put the data in the correct order.
>
> Signed-off-by: Doug Brown
Reviewed-by: Francisco Iglesias
> ---
> hw/net/can/xlnx-versal-canfd.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/hw/net/can/xlnx-vers
On Fri, Aug 16, 2024 at 09:35:05AM -0700, Doug Brown wrote:
> There was no case for handling received CAN FD frames with a DLC of 0-8.
> This was already handled properly with TX. Add similar code for RX.
>
> Signed-off-by: Doug Brown
Reviewed-by: Francisco Iglesias
> ---
>
with a DLC of 0-8, which was broken previously.
>
> Signed-off-by: Doug Brown
Reviewed-by: Francisco Iglesias
> ---
> hw/net/can/xlnx-versal-canfd.c | 67 ++
> 1 file changed, 4 insertions(+), 63 deletions(-)
>
> diff --git a/hw/net/can/xlnx-v
Hi Peter,
On Fri, Sep 06, 2024 at 03:36:10PM +0100, Peter Maydell wrote:
> On Tue, 27 Aug 2024 at 04:51, Doug Brown wrote:
> >
> > This series fixes several problems I ran into while trying to simulate
> > the AMD/Xilinx Versal CANFD controller in the xlnx-versal-virt machine
> > using Xilinx's v
-off-by: Doug Brown
Reviewed-by: Francisco Iglesias
Thanks a lot for the fixes and sorry for the delayed review!
Best regards,
Francisco
> ---
> hw/net/can/xlnx-versal-canfd.c | 36 +++---
> 1 file changed, 3 insertions(+), 33 deletions(-)
>
> dif
Update my xilinx.com email address to my amd.com address.
Signed-off-by: Francisco Iglesias
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index ad957ca5e8..b03952f43e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1055,7 +1055,7
Signed-off-by: Francisco Iglesias
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b03952f43e..a320ce759c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2701,6 +2701,7 @@ F: include/hw/rx/
CAN bus subsystem and hardware
M: Pavel Pisa
+M
amd.com one on the Xilinx Versal
OSPI maintaintership section. In the third I volunteer to replace Vikram as
maintainer for the CAN bus subsystem.
Best regards,
Francisco
Francisco Iglesias (3):
MAINTAINERS: Remove Vikram Garhwal as maintainer
MAINTAINERS: Update Xilinx Versal OSPI mai
Vikram's email is bouncing, pause his maintainership until a new email is
provided.
Signed-off-by: Francisco Iglesias
---
MAINTAINERS | 2 --
1 file changed, 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0c1bc69828..ad957ca5e8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1
On Thu, Aug 29, 2024 at 05:31:17PM +0530, Shiva sagar Myana wrote:
> Add the SFDP table for the Micron Xccela mt35xu01g flash.
>
> Signed-off-by: Shiva sagar Myana
Reviewed-by: Francisco Iglesias
> ---
> V1->V2: Change subject and commit message
>
> hw/block/m25p
0, 1024, ER_4K) },
> +{ INFO("w25q01jvq", 0xef4021, 0, 64 << 10, 2048, ER_4K) },
Reviewed-by: Francisco Iglesias
> };
>
> typedef enum {
> --
> 2.34.1
>
>
gt; #2 0x559a21bf3442 in object_class_foreach_tramp
> /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:1070:5
>
> Fixes: 00f05c02f9e7342f ("hw/dma/xlnx_csu_dma: Support starting a read
> transfer through a class method")
> Signed-off-by: Peter Mayde
Hi Iris
On [2022 Jul 06] Wed 19:16:26, Iris Chen wrote:
> Signed-off-by: Iris Chen
A couple of suggestions below if you would like to go for a v3 but otherwise:
Reviewed-by: Francisco Iglesias
Thanks,
Best regards,
Francisco Iglesias
> ---
> Addressing all comments.
> In rep
On [2022 Jul 08] Fri 09:45:52, Iris Chen wrote:
> Signed-off-by: Iris Chen
Reviewed-by: Francisco Iglesias
> ---
> Cosmetic suggestions addressed.
>
> hw/block/m25p80.c | 102 --
> 1 file changed, 90 insertions(+), 12 deletions(
On [2021 Oct 15] Fri 13:35:30, Tong Ho wrote:
> Signed-off-by: Tong Ho
Reviewed-by: Francisco Iglesias
> ---
> hw/nvram/xlnx-efuse.c | 9 ++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c
> index e
On [2021 Oct 15] Fri 13:35:31, Tong Ho wrote:
> Signed-off-by: Tong Ho
Reviewed-by: Francisco Iglesias
> ---
> hw/nvram/xlnx-versal-efuse-ctrl.c | 20 +++-
> 1 file changed, 15 insertions(+), 5 deletions(-)
>
> diff --git a/hw/nvram/xlnx-versal-efuse-ctrl.c
On [2021 Oct 15] Fri 13:35:32, Tong Ho wrote:
> Signed-off-by: Tong Ho
Reviewed-by: Francisco Iglesias
> ---
> hw/nvram/xlnx-zynqmp-efuse.c | 18 --
> 1 file changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/hw/nvram/xlnx-zynqmp-efuse.c b/hw/nvram/x
On [2022 Apr 01] Fri 00:20:16, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Break out header file to allow embedding of the the TTC.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> incl
On [2022 Apr 01] Fri 00:20:17, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Connect the 4 TTC timers on the ZynqMP.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> include/hw/arm/xlnx-zynqmp.h | 4
>
On [2022 Apr 01] Fri 12:06:31, Tong Ho wrote:
> This adds required initialization of Error * variable.
>
> Signed-off-by: Tong Ho
Reviewed-by: Francisco Iglesias
> ---
> hw/nvram/xlnx-bbram.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw
On [2022 Apr 02] Sat 22:45:23, Pavel Pisa wrote:
> Signed-off-by: Pavel Pisa
Reviewed-by: Francisco Iglesias
> ---
> docs/system/devices/can.rst | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/docs/system/devices/can.rst b/docs/system/devic
On Wed, Apr 06, 2022 at 06:43:00PM +0100, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Create an APU CPU Cluster. This is in preparation to add the RPU.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> h
On Wed, Apr 06, 2022 at 06:43:01PM +0100, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Add the Cortex-R5Fs of the Versal RPU (Real-time Processing Unit)
> subsystem.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
>
On Wed, Apr 06, 2022 at 06:43:02PM +0100, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Add a model of the Xilinx Versal CRL.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> hw/misc/meson.build | 1
On Wed, Apr 06, 2022 at 06:43:03PM +0100, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Connect the CRL (Clock Reset LPD) to the Versal SoC.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> hw
On [2022 Apr 04] Mon 16:46:42, Peter Maydell wrote:
> Now we have removed the only use of TYPE_EXYNOS4210_IRQ_GATE we can
> delete the device entirely.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Francisco Iglesias
> ---
> hw/intc/exyn
According to [1] address bits 27 - 20 are mapped to the bus number (the
TLPs bus number field is 8 bits).
[1] PCI Express® Base Specification Revision 5.0 Version 1.0
Signed-off-by: Francisco Iglesias
---
include/hw/pci/pcie_host.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
Hi Michael,
On [2022 Apr 11] Mon 17:12:47, Michael S. Tsirkin wrote:
> On Mon, Apr 11, 2022 at 09:38:18PM +0200, Francisco Iglesias wrote:
> > According to [1] address bits 27 - 20 are mapped to the bus number (the
> > TLPs bus number field is 8 bits).
> >
> > [1] PCI
Hi,
This series attempts to correct a couple of defines inside pcie_host.h.
Best regards,
Francisco Iglesias
Changelog:
v1->v2:
* Went from RFC to patch proposal
* Added more meat on the commit message of patch 1
Francisco Iglesias (2):
include/hw/pci/pcie_host: Corr
vision 5.0 Version 1.0
Signed-off-by: Francisco Iglesias
---
include/hw/pci/pcie_host.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h
index 076457b270..b3c8ce973c 100644
--- a/include/hw/pci/pcie_host.h
+++ b/incl
found in PPC440
core SoCs")).
[1] PCI Express® Base Specification Revision 5.0 Version 1.0
Signed-off-by: Francisco Iglesias
---
include/hw/pci/pcie_host.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h
index b3c
From: Francisco Iglesias
Connect ZynqMP's USB controllers.
Signed-off-by: Francisco Iglesias
---
hw/arm/xlnx-zynqmp.c | 36
include/hw/arm/xlnx-zynqmp.h | 3 +++
2 files changed, 39 insertions(+)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm
27;extern' in above hdr if we like (also the other patches),
either way:
Reviewed-by: Francisco Iglesias
> +
> +
> #endif
> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
> index 13e7b28fd2b0..028b026d8ba2 100644
> --- a/hw/block/m25p80.c
> +++ b/hw/block/m25p80
On [2022 Jul 22] Fri 08:36:02, Cédric Le Goater wrote:
> A mx25l25635f chip model is generally found on these machines. It's
> newer and uses 4B opcodes which is better to exercise the support in
> the Linux kernel.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by
27;ve found so
might be that you can switch to just INFO and _ext_id 0 above (might be the
same in the previous patch with the similar flash). Otherwise looks good to
me:
Reviewed-by: Francisco Iglesias
> + .sfdp_read = m25p80_sfdp_mx25l25635f },
> { INFO("mx25l25655e", 0xc
nt8_t m25p80_sfdp_mx66l1g45g(uint32_t addr);
(optional -extern)
Reviewed-by: Francisco Iglesias
>
> #endif
> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
> index 6b120ce65212..52df24d24751 100644
> --- a/hw/block/m25p80.c
> +++ b/hw/block/m25p80.c
> @@ -240,7 +240,8 @@
"qemu/osdep.h"
> +#include "qemu/host-utils.h"
> +#include "m25p80_sfdp.h"
> +
> +#define define_sfdp_read(model) \
> +uint8_t m25p80_sfdp_##model(uint32_t addr)\
> +{
tern uint8_t m25p80_sfdp_w25q512jv(uint32_t addr);
(optional -extern)
Reviewed-by: Francisco Iglesias
>
> #endif
> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
> index 220dbc8fb327..8ba9d732a323 100644
> --- a/hw/block/m25p80.c
> +++ b/hw/block/m25p80.c
> @@ -347,7
b/hw/block/m25p80_sfdp.h
> @@ -21,4 +21,6 @@ extern uint8_t m25p80_sfdp_mx25l25635e(uint32_t addr);
> extern uint8_t m25p80_sfdp_mx25l25635f(uint32_t addr);
> extern uint8_t m25p80_sfdp_mx66l1g45g(uint32_t addr);
>
> +extern uint8_t m25p80_sfdp_w25q256(uint32_t addr);
(optional
a2fc..8fb1cd3f8a 100644
> --- a/hw/block/m25p80_sfdp.h
> +++ b/hw/block/m25p80_sfdp.h
> @@ -24,4 +24,6 @@ extern uint8_t m25p80_sfdp_mx66l1g45g(uint32_t addr);
> extern uint8_t m25p80_sfdp_w25q256(uint32_t addr);
> extern uint8_t m25p80_sfdp_w25q512jv(uint32_t addr);
>
> +extern uint8_t m25p80_sfdp_w25q01jvq(uint32_t addr);
(optional -extern)
Reviewed-by: Francisco Iglesias
> +
> #endif
> --
> 2.35.1
>
Hi Cedric,
On [2022 Oct 10] Mon 11:58:40, Michael Walle wrote:
> Am 2022-10-10 08:23, schrieb Cédric Le Goater:
> > On 10/7/22 16:44, Francisco Iglesias wrote:
>
> > > > --- a/hw/block/m25p80.c
> > > > +++ b/hw/block/m25p80.c
> > > > @@ -234,6 +2
On [2022 Oct 13] Thu 18:12:34, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater
Reviewed-by: Francisco Iglesias
> ---
> hw/block/m25p80.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
&g
On [2021 Nov 29] Mon 17:44:37, Peter Maydell wrote:
> On Wed, 24 Nov 2021 at 10:16, Francisco Iglesias
> wrote:
> >
> > Add an interface for controlling DMA models that are reused with other
> > models. This allows a controlling model to start transfers through the
> &g
Implement the DMA control interface for allowing direct control of DMA
operations from inside peripheral models embedding (and reusing) the
Xilinx CSU DMA.
Signed-off-by: Francisco Iglesias
---
hw/dma/xlnx_csu_dma.c | 32
include/hw/dma/xlnx_csu_dma.h
Connect Versal's PMC SLCR (system-level control registers) model.
Signed-off-by: Francisco Iglesias
---
hw/arm/xlnx-versal.c | 17 +
include/hw/arm/xlnx-versal.h | 6 ++
2 files changed, 23 insertions(+)
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-ver
Add a model of Xilinx Versal's OSPI flash memory controller.
Signed-off-by: Francisco Iglesias
---
hw/ssi/meson.build|1 +
hw/ssi/xlnx-versal-ospi.c | 1892 +
include/hw/ssi/xlnx-versal-ospi.h | 86 ++
3 files changed,
Add support for Micron Xccela flash mt35xu01g.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/block/m25p80.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index b77503dc84..c6bf3c6bfa 100644
--- a/hw/block/m25p80.c
+++ b/hw
Add a model of Versal's PMC SLCR (system-level control registers).
Signed-off-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
Acked-by: Edgar E. Iglesias
---
hw/misc/meson.build|5 +-
hw/misc/xlnx-versal-pmc-iou-slcr.c |
Add in the missing includes in the header for being able to build the DMA
model when reusing it.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
include/hw/dma/xlnx_csu_dma.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/hw/dma/xlnx_csu_dma.h b/include/hw
Connect the OSPI flash memory controller model (including the source and
destination DMA).
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal.c | 88
include/hw/arm/xlnx-versal.h | 20 ++
2 files
Connect Micron Xccela mt35xu01g flashes to the OSPI flash memory
controller.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal-virt.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx
completion signaling will be read and catched through the DMA engine
model's register API and signaling.
Signed-off-by: Francisco Iglesias
---
hw/dma/dma-ctrl-if.c | 31 +++
hw/dma/meson.build | 1 +
include/hw/dma/dma
List myself as maintainer for the Xilinx Versal OSPI controller.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7543eb4d59..e52cc94840 100644
--- a/MAINTAINERS
+++ b
Also, since being the author, list myself as maintainer for the file.
Signed-off-by: Francisco Iglesias
---
MAINTAINERS| 1 +
docs/devel/dma-ctrl-if.rst | 320 +
docs/devel/index.rst | 1 +
3 files changed, 322 insertions
a model of
Versal's OSPI controller is added and connected to the Versal virt
machine. The series then ends with adding initial support for the Micron
Xccelera mt35xu01g flash and flashes of this type are connected to the
OSPI in the Versal virt machine.
Best regards,
Francisco Iglesias
Chan
On Fri, Dec 10, 2021 at 03:11:41PM +, Peter Maydell wrote:
> On Wed, 1 Dec 2021 at 15:40, Francisco Iglesias
> wrote:
> >
> > Add a model of Versal's PMC SLCR (system-level control registers).
> >
> > Signed-off-by: Francisco Iglesias
> > Signed-off-b
On Fri, Dec 10, 2021 at 03:16:59PM +, Peter Maydell wrote:
> On Wed, 1 Dec 2021 at 15:40, Francisco Iglesias
> wrote:
> >
> > Connect Versal's PMC SLCR (system-level control registers) model.
> >
> > Signed-off-by: Francisco Iglesias
> > diff --git a/
Add an orgate and 'or' the interrupts from the BBRAM and RTC models.
Signed-off-by: Francisco Iglesias
---
hw/arm/xlnx-versal-virt.c| 2 +-
hw/arm/xlnx-versal.c | 28 ++--
include/hw/arm/xlnx-versal.h | 5 +++--
3 files changed, 30 insert
On Fri, Dec 10, 2021 at 04:02:22PM +, Peter Maydell wrote:
> On Wed, 1 Dec 2021 at 15:40, Francisco Iglesias
> wrote:
> >
> > Add a model of Xilinx Versal's OSPI flash memory controller.
> >
> > Signed-off-by: Francisco Iglesias
>
>
>
Add support for Micron Xccela flash mt35xu01g.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/block/m25p80.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index b77503dc84..c6bf3c6bfa 100644
--- a/hw/block/m25p80.c
+++ b/hw
Add a model of Versal's PMC SLCR (system-level control registers).
Signed-off-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
---
hw/misc/meson.build|5 +-
hw/misc/xlnx-versal-pmc-iou-slcr.c | 1446
include/hw/misc
a model of
Versal's OSPI controller is added and connected to the Versal virt
machine. The series then ends with adding initial support for the Micron
Xccelera mt35xu01g flash and flashes of this type are connected to the
OSPI in the Versal virt machine.
Best regards,
Francisco Iglesias
Chan
Connect Micron Xccela mt35xu01g flashes to the OSPI flash memory
controller.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
---
hw/arm/xlnx-versal-virt.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/hw/arm/xlnx
completion signaling will be read and caught through the DMA engine
model's register API and signaling.
Signed-off-by: Francisco Iglesias
---
hw/dma/dma-ctrl-if.c | 30 ++
hw/dma/meson.build | 1 +
include/hw/dma/dma
Add a model of Xilinx Versal's OSPI flash memory controller.
Signed-off-by: Francisco Iglesias
---
hw/ssi/meson.build|1 +
hw/ssi/xlnx-versal-ospi.c | 1855 +
include/hw/ssi/xlnx-versal-ospi.h | 111 +++
3 files changed,
Connect Versal's PMC SLCR (system-level control registers) model.
Signed-off-by: Francisco Iglesias
---
hw/arm/xlnx-versal.c | 71 +++-
include/hw/arm/xlnx-versal.h | 5
2 files changed, 75 insertions(+), 1 deletion(-)
diff --git a/h
Also, since being the author, list myself as maintainer for the file.
Signed-off-by: Francisco Iglesias
---
MAINTAINERS| 1 +
docs/devel/dma-ctrl-if.rst | 234 +
docs/devel/index.rst | 1 +
3 files changed, 236 insertions
Add in the missing includes in the header for being able to build the DMA
model when reusing it.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
include/hw/dma/xlnx_csu_dma.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/hw/dma/xlnx_csu_dma.h b/include/hw
Implement the DMA control interface for allowing direct control of DMA
operations from inside peripheral models embedding (and reusing) the
Xilinx CSU DMA.
Signed-off-by: Francisco Iglesias
---
hw/dma/xlnx_csu_dma.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/hw/dma
List myself as maintainer for the Xilinx Versal OSPI controller.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7543eb4d59..e52cc94840 100644
Connect the OSPI flash memory controller model (including the source and
destination DMA).
Signed-off-by: Francisco Iglesias
---
hw/arm/xlnx-versal.c | 93
include/hw/arm/xlnx-versal.h | 20 ++
2 files changed, 113 insertions(+)
diff
On Fri, Dec 10, 2021 at 12:21:26PM +, Peter Maydell wrote:
> On Wed, 1 Dec 2021 at 15:41, Francisco Iglesias
> wrote:
> >
> > Also, since being the author, list myself as maintainer for the file.
> >
> > Signed-off-by: Francisco Iglesias
> > ---
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