Re: [RESEND PATCH v2 0/5] target/riscv: Support RISC-V privilege 1.13 spec

Hi Daniel, thank you for your help. I found that only the cover is without many maintainers. I used to send patches by git send-email --dry-run --to 'qemu-devel@nongnu.org, qemu-ri...@nongnu.org' --cc-cmd='scripts/get_maintainer.pl -i' patches/*. Do you have a better script for me? Thank you. Sin

Re: [RESEND PATCH v2 0/5] target/riscv: Support RISC-V privilege 1.13 spec

intainer.pl XXXPATCH/* |sed -e 's/$/,/')" /XXXPATCH/* Sincerely, Fea On Thu, May 30, 2024 at 6:37 PM Andrew Jones wrote: > On Thu, May 30, 2024 at 11:30:28AM GMT, Fea Wang wrote: > > Hi Daniel, > > thank you for your help. > > > > I found that only the cover

Re: [RESEND PATCH v2 2/5] target/riscv: Support the version for ss1p13

Got it. I will fix it in the next version of the patch series. Sincerely, Fea On Tue, Jun 4, 2024 at 8:56 AM Alistair Francis wrote: > On Tue, Jun 4, 2024 at 10:46 AM Alistair Francis > wrote: > > > > On Wed, May 15, 2024 at 6:02 PM Fea.Wang wrote: > > > > > > Add RISC-V privilege 1.13 suppor

Re: [RESEND PATCH v2 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0

Thank you for correcting me. I will fix it in the next version of the patch series. Sincerely, Fea On Tue, Jun 4, 2024 at 8:54 AM Alistair Francis wrote: > On Wed, May 15, 2024 at 6:01 PM Fea.Wang wrote: > > > > Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in > > SMSTATEEN

Re: [PATCH 1/4] hw/dma: Enhance error handling in loading description

Hi Edgar, Thank you for recommending to me. I will make the change in the next version of the patch series. Sincerely, Fea On Mon, Jun 3, 2024 at 6:19 PM Edgar E. Iglesias wrote: > On Mon, Jun 3, 2024 at 7:47 AM Fea.Wang wrote: > >> Loading a description from memory may cause a bus-error. In t

Re: [PATCH 2/4] hw/dma: Break the loop when loading descriptions fails

Hi Edgar, thank you for the advice, I will squash them in the next version of the patch series. Sincerely, Fea On Mon, Jun 3, 2024 at 6:21 PM Edgar E. Iglesias wrote: > On Mon, Jun 3, 2024 at 7:48 AM Fea.Wang wrote: > >> When calling the loading a description function, it should be noticed >>

Re: [PATCH 4/4] hw/net: Fix the transmission return size

I just encountered this issue when running Linux, and the trouble will be fixed after the patches. So I think they work. Sincerely, Fea On Mon, Jun 3, 2024 at 6:31 PM Edgar E. Iglesias wrote: > On Mon, Jun 3, 2024 at 7:48 AM Fea.Wang wrote: > >> Fix the transmission return size because not all

Re: [PATCH v3 3/6] target/riscv: Support the version for ss1p13

Sure, I will reorder the commits in the next patch series. Thank you Sincerely, Fea On Thu, Jun 6, 2024 at 7:58 AM Alistair Francis wrote: > On Tue, Jun 4, 2024 at 4:23 PM Fea.Wang wrote: > > > > Add RISC-V privilege 1.13 support. > > > > Signed-off-by: Fea.Wang > > Signed-off-by: Fea.Wang >

Re: [PATCH 1/5] target/riscv: Reuse the conversion function of priv_spec and string

Thank you, I will correct it in the patch v2. Sincerely, Fea LIU Zhiwei 於 2024年5月13日 週一 上午10:55寫道： > > On 2024/5/10 14:58, Fea.Wang wrote: > > From: Jim Shu > > > > Public the conversion function of priv_spec and string in cpu.h, so that > > tcg-cpu.c could also use it. > > > > Signed-off-by:

Re: [PATCH 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0

Thank you, I will correct it in the patch v2. Sincerely, Fea LIU Zhiwei 於 2024年5月13日 週一 上午10:51寫道： > > On 2024/5/10 14:58, Fea.Wang wrote: > > Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in > > SMSTATEEN0 that controls access to the hedeleg. > > > > Signed-off-by: Fea.Wang

Re: [PATCH 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32

OK, I will correct it in the patch v2. Thank you. Sincerely, Fea LIU Zhiwei 於 2024年5月13日 週一 上午10:49寫道： > > On 2024/5/10 14:58, Fea.Wang wrote: > > Based on privileged spec 1.13, the RV32 needs to implement MEDELEGH > > and HEDELEGH for exception codes 32-47 for reserving and exception codes > >

Re: [PATCH v2 0/5] target/riscv: Support RISC-V privilege 1.13 spec

Sorry that I only put the patch version on the cover letter. I will resend the patches. Sincerely, Fea Fea.Wang 於 2024年5月15日 週三 下午3:48寫道： > Based on the change log for the RISC-V privilege 1.13 spec, add the > support for ss1p13. > > Ref: > https://github.com/riscv/riscv-isa-manual/blob/a7d93c9

Re: [PATCH v2 2/3] hw/dma: Add a trace log for a description loading failure

Sure, I will fix it in the next patch series. Thank you Sincerely, Fea On Mon, Jun 10, 2024 at 7:49 PM Philippe Mathieu-Daudé wrote: > Hi Fea, > > On 4/6/24 09:15, Fea.Wang wrote: > > Due to a description loading failure, adding a trace log makes observing > > the DMA behavior easy. > > > > Sig

Re: [PATCH 4/5] target/riscv: Check memory access to meet svuket rule

Thank you for your advice. I will take them after the spec is more finalized. Sincerely, Fea On Wed, Sep 4, 2024 at 6:18 AM Daniel Henrique Barboza < dbarb...@ventanamicro.com> wrote: > > > On 9/3/24 3:17 AM, Fea.Wang wrote: > > Follow the Svukte spec, do the memory access address checking > > >

Re: [PATCH v2 5/5] target/riscv: Expose svukte ISA extension

Got it, thank you. Sincerely, Fea On Tue, Nov 12, 2024 at 2:33 AM Daniel Henrique Barboza < dbarb...@ventanamicro.com> wrote: > > > On 11/8/24 5:52 AM, Fea.Wang wrote: > > Add "svukte" in the ISA string when svukte extension is enabled. > > > > Signed-off-by: Fea.Wang > > Reviewed-by: Frank Cha

Re: [PATCH v2 4/5] target/riscv: Check memory access to meet svuket rule

Thank you for refining it. I fixed some parts and will put them in the V3 patches. Sincerely, Fea On Tue, Nov 12, 2024 at 2:32 AM Daniel Henrique Barboza < dbarb...@ventanamicro.com> wrote: > > > On 11/8/24 5:52 AM, Fea.Wang wrote: > > Follow the Svukte spec, do the memory access address checkin

Re: [PATCH v4 6/6] target/riscv: Check svukte is not enabled in RV32

OK, thank you. I will refine it in the next patches. On Fri, Nov 22, 2024 at 1:00 PM Alistair Francis wrote: > On Wed, Nov 20, 2024 at 5:47 PM Fea.Wang wrote: > > > > Based on the spec, svukte depends on SV39, so it should not be enabled > > in RV32. > > The spec explicitly says it doesn't supp

Re: [PATCH v3 5/5] target/riscv: Expose svukte ISA extension

OK, I will add a new commit for checking the extension in RV32. Thank you. Sincerely, Fea On Tue, Nov 19, 2024 at 11:34 AM Alistair Francis wrote: > On Tue, Nov 12, 2024 at 7:14 PM Fea.Wang wrote: > > > > Add "svukte" in the ISA string when svukte extension is enabled. > > > > Signed-off-by: F

Re: [PATCH v3 4/5] target/riscv: Check memory access to meet svukte rule

Thanks for the advice. I will fix them in the next patch version. Sincerely, Fea On Tue, Nov 19, 2024 at 11:33 AM Alistair Francis wrote: > On Tue, Nov 12, 2024 at 7:13 PM Fea.Wang wrote: > > > > Follow the Svukte spec, do the memory access address checking > > > > 1. Include instruction fetch

Re: [PATCH 1/1] hw/net: Support Marvell 88E1111 phy driver

Ping On Fri, Nov 15, 2024 at 9:44 AM Fea.Wang wrote: > When the ethernet PHY's compatible string is 'ethernet-phy-id0141.0cc2', > it will be matched with the Marvell driver in Linux instead of the > generic driver. They differ from reading the PHY register17.11 bit which > is for 'Speed and Dupl