On Sun, May 22, 2016 at 08:58:51 +0100, Alex Bennée wrote:
> For tsan runs you need to re-build with:
>
> ./configure --cc=gcc --extra-cflags="-pie -fPIE -fsanitize=thread"
> --with-coroutine=gthread
>
> Specifically the coroutine ucontext messing really confuses TSAN.
With your configure arg
ARRAY_SIZE is defined in osdep.h so having an unconditional
definition here is fragile.
Signed-off-by: Emilio G. Cota
---
tests/i440fx-test.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tests/i440fx-test.c b/tests/i440fx-test.c
index d0bc8de..d610e66 100644
--- a/tests/i440fx-test.c
On Thu, Apr 30, 2015 at 23:14:06 +0300, Michael Tokarev wrote:
> 30.04.2015 22:16, Emilio G. Cota wrote:
> > ARRAY_SIZE is defined in osdep.h so having an unconditional
> > definition here is fragile.
>
> Fragile in what sense? Nothing in that file includes osdep.h.
F
On Wed, May 06, 2015 at 17:38:02 +0200, Alvise Rigo wrote:
> This patch series provides an infrastructure for atomic
> instruction implementation in QEMU, paving the way for TCG multi-threading.
> The adopted design does not rely on host atomic
> instructions and is intended to propose a 'legacy' s
Hi all,
These are patches I've been working on for some time now.
Since emulation of atomic instructions is recently getting
attention([1], [2]), I'm submitting them for comment.
[1] http://thread.gmane.org/gmane.comp.emulators.qemu/314406
[2] http://thread.gmane.org/gmane.comp.emulators.qemu/33
Having the physical address in the TLB entry will allow us
to portably obtain the physical address of a memory access,
which will prove useful when implementing a scalable emulation
of atomic instructions.
Signed-off-by: Emilio G. Cota
---
cputlb.c| 1 +
include/exec/cpu-defs.h
This will be used by the atomic instruction emulation code.
Signed-off-by: Emilio G. Cota
---
include/qemu/tiny_set.h | 90 +
1 file changed, 90 insertions(+)
create mode 100644 include/qemu/tiny_set.h
diff --git a/include/qemu/tiny_set.h b
Signed-off-by: Emilio G. Cota
---
aie-helper.c | 179 ++
include/exec/cpu-defs.h | 5 ++
include/qemu/aie-helper.h | 21 ++
3 files changed, 205 insertions(+)
create mode 100644 aie-helper.c
create mode 100644 include/qemu/aie
Signed-off-by: Emilio G. Cota
---
linux-user/main.c | 89 -
target-arm/helper.c| 2 +
target-arm/helper.h| 2 +
target-arm/op_helper.c | 5 ++
target-arm/translate.c | 172 ++---
5 files changed, 86
This will be used by the atomic instruction emulation code.
Signed-off-by: Emilio G. Cota
---
softmmu_template.h | 48
tcg/tcg.h | 5 +
2 files changed, 53 insertions(+)
diff --git a/softmmu_template.h b/softmmu_template.h
index
Signed-off-by: Emilio G. Cota
---
target-i386/helper.h | 6 +-
target-i386/mem_helper.c | 19 +++--
target-i386/translate.c | 176 ---
3 files changed, 122 insertions(+), 79 deletions(-)
diff --git a/target-i386/helper.h b/target-i386/helper.h
This will be used by atomic instruction emulation code.
Signed-off-by: Emilio G. Cota
---
include/qemu/radix-tree.h | 29 ++
util/Makefile.objs| 2 +-
util/radix-tree.c | 77 +++
3 files changed, 107 insertions(+), 1
Signed-off-by: Emilio G. Cota
---
Makefile.target| 1 +
aie.c | 52
include/qemu/aie.h | 48
translate-all.c| 2 ++
4 files changed, 103 insertions(+)
create mode 100644
On Fri, May 08, 2015 at 17:02:11 -0400, Emilio G. Cota wrote:
> +++ b/aie.c
(snip)
> +static inline void *aie_entry_init(unsigned long index)
> +{
> +AIEEntry *entry;
> +
> +entry = qemu_memalign(64, sizeof(*entry));
> +tiny_set_init(&entry->ts);
> +
zeof(CPUTLBEntry)=pow2 constraint
Breaks all non-i386 TCG backends! Do not apply.
Signed-off-by: Emilio G. Cota
---
include/exec/cpu-defs.h | 23 +--
tcg/i386/tcg-target.c | 12 +++-
2 files changed, 24 insertions(+), 11 deletions(-)
diff --git a/include/exec/c
On Fri, May 10, 2019 at 11:36:33 +0100, Alex Bennée wrote:
> Ping Emilio/Mark
>
> Would you be able to re-run your tests to check there are no other
> regressions? I can then get the PR prepared for merging ;-)
I'll try to run some tests next week, but I am not sure I'll
have time to do so. If I
On Sat, Mar 09, 2019 at 13:53:32 +0800, Li Qiang wrote:
> Hi all,
>
> Today I ‘git clone’ && configure && make && make check
>
> And get following error,
>
> fp-test.c:50:10: fatal error: fail.h: No such file or directory
> #include "fail.h"
> ^~~~
>
> I look at the commit:
>
Looks like support for this was not fully added; my apologies for
closing this bug too early.
Adding full support for strong-on-weak emulation would be simple, at
least when it comes to memory ordering. The slowdown would be huge
though, see Figure 12 in
http://www.cs.columbia.edu/~cota/pubs/cota_
OK, looks like I cannot reopen the bug, probably because the bug tracker
moved to gitlab.
If you care about this feature, please file a bug over there:
https://gitlab.com/qemu-project/qemu/-/issues
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscri
On Tue, Oct 25, 2016 at 16:35:48 -0400, Pranith Kumar wrote:
> On Tue, Oct 25, 2016 at 4:02 PM, Paolo Bonzini wrote:
> >
> >
> >> I've written a patch (see below) to take the per-bucket sequence locks.
> >
> > What's the performance like?
> >
>
> Applying only this patch, the perf numbers are sim
On Tue, Oct 25, 2016 at 11:35:06 -0400, Pranith Kumar wrote:
> Using perf, I see that sequence lock is being a bottleneck since it is
> being read by everyone. Giving it its own cache-line seems to help
> things quite a bit.
>
> Using qht-bench, I measured the following for:
>
> $ ./tests/qht-ben
On Wed, Sep 14, 2016 at 14:53:14 +0100, Alex Bennée wrote:
> Richard Henderson writes:
> > From: "Emilio G. Cota"
> > QEMU_CFLAGS += -I$(SRC_PATH)/tests
> > @@ -465,6 +466,7 @@ tests/test-qdist$(EXESUF): tests/test-qdist.o
> > $(test-util-obj-y)
> >
On Fri, Sep 16, 2016 at 10:46:48 -0700, Richard Henderson wrote:
> From: "Emilio G. Cota"
>
> With this microbenchmark we can measure the overhead of emulating atomic
> instructions with a configurable degree of contention.
>
> The benchmark spawns $n threads, e
are 64b long) that is randomly selected from a range [0, $r).
[ Note: each $foo corresponds to a -foo flag ]
Signed-off-by: Emilio G. Cota
Signed-off-by: Richard Henderson
Message-Id: <1467054136-10430-20-git-send-email-c...@braap.org>
---
tests/.gitignore | 1 +
On Fri, Sep 16, 2016 at 10:46:52 -0700, Richard Henderson wrote:
(snip)
> +/* Returns 0 on success; 1 otherwise. */
> +uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr,
> + uint64_t new_lo, uint64_t new_hi)
> +{
> +uintptr_t ra = GETPC();
On Mon, Sep 19, 2016 at 16:51:38 +0100, Alex Bennée wrote:
> ThreadSanitizer detects a possible race between reading/writing the
> hashes. As ordering semantics are already documented for qht we just
> need to ensure a race can't tear the hash value so we can use the
> relaxed atomic_set/read funct
On Mon, Sep 19, 2016 at 20:37:06 +0200, Paolo Bonzini wrote:
> On 19/09/2016 20:06, Emilio G. Cota wrote:
> > On Mon, Sep 19, 2016 at 16:51:38 +0100, Alex Bennée wrote:
> >> > ThreadSanitizer detects a possible race between reading/writing the
> >> > hashes.
On Mon, Sep 19, 2016 at 14:50:57 +0200, Paolo Bonzini wrote:
> We have to run safe work items outside the BQL; for now keep other
> work items within the BQL, though this can be changed relatively
> easily as a follow-up.
>
> Signed-off-by: Paolo Bonzini
> ---
> cpus-common.c | 33 ++
On Mon, Sep 19, 2016 at 14:50:58 +0200, Paolo Bonzini wrote:
> From: Sergey Fedorov
>
> Use async_safe_run_on_cpu() to make tb_flush() thread safe. This is
> possible now that code generation does not happen in the middle of
> execution.
>
> It can happen that multiple threads schedule a safe w
On Mon, Sep 19, 2016 at 14:50:56 +0200, Paolo Bonzini wrote:
> It is not necessary to hold qemu_cpu_list_mutex throughout the
> exclusive section, because no other exclusive section can run
> while pending_cpus != 0.
>
> exclusive_idle() is called in cpu_exec_start(), and that prevents
> any CPUs
On Mon, Sep 19, 2016 at 14:50:47 +0200, Paolo Bonzini wrote:
> From: Sergey Fedorov
>
> Convert pthread_mutex_t and pthread_cond_t to QemuMutex and QemuCond.
> This will allow to make some locks and conditional variables common
> between user and system mode emulation.
>
> Signed-off-by: Sergey
On Mon, Sep 19, 2016 at 14:50:50 +0200, Paolo Bonzini wrote:
> From: Sergey Fedorov
>
> Make CPU work core functions common between system and user-mode
> emulation. User-mode does not use run_on_cpu, so do not implement it.
>
> Signed-off-by: Sergey Fedorov
> Signed-off-by: Sergey Fedorov
> R
On Mon, Sep 19, 2016 at 14:50:59 +0200, Paolo Bonzini wrote:
> Set cpu->running without taking the cpu_list lock, only look at it if
> there is a concurrent exclusive section. This requires adding a new
> field to CPUState, which records whether a running CPU is being counted
> in pending_cpus. W
On Mon, Sep 19, 2016 at 14:50:43 +0200, Paolo Bonzini wrote:
> In addition to fixing some of the issues found by Alex, safe work items
> need not run anymore with a mutex taken. Of course, cpu_exec_start/end
> and start_exclusive/end_exclusive are essentially the read and write
> side of a special
On Wed, Sep 21, 2016 at 18:19:26 +0200, Paolo Bonzini wrote:
>
>
> On 21/09/2016 18:05, Emilio G. Cota wrote:
> >> > +tb_lock();
> >> > +
> >> > +/* If it's already been done on request of another CPU,
> >> > +
On Wed, Sep 21, 2016 at 20:19:18 +0200, Paolo Bonzini wrote:
(snip)
> No, this is not true. Barriers order stores and loads within a thread
> _and_ establish synchronizes-with edges.
>
> In the example above you are violating causality:
>
> - cpu0 stores cpu->running before loading pending_cpus
On Mon, Sep 19, 2016 at 14:50:59 +0200, Paolo Bonzini wrote:
(snip)
> @@ -212,24 +216,75 @@ void end_exclusive(void)
> /* Wait for exclusive ops to finish, and begin cpu execution. */
> void cpu_exec_start(CPUState *cpu)
> {
> -qemu_mutex_lock(&qemu_cpu_list_mutex);
> -exclusive_idle();
On Mon, Nov 07, 2016 at 15:03:23 +, Peter Maydell wrote:
> On 5 November 2016 at 18:42, Peter Maydell wrote:
> > With a little luck I may be able to put something up
> > on Monday as a sort of minimal-demonstration of how
> > this would look in QEMU.
>
> Generated documentation:
> http://pe
On Tue, Jul 19, 2016 at 01:44:41 +0300, Michael S. Tsirkin wrote:
> From: Peter Xu
>
> This patch translates all IOAPIC interrupts into MSI ones. One pseudo
> ioapic address space is added to transfer the MSI message. By default,
> it will be system memory address space. When IR is enabled, it wi
On Fri, Nov 11, 2016 at 12:18:04 -0500, Emilio G. Cota wrote:
> This commit (which sits between 2.6 and 2.7)
Forgot to add the commit id -- cb135f59b8059c3a3
E.
On Fri, Nov 11, 2016 at 18:17:05 -0500, Peter Xu wrote:
> > This commit (which sits between 2.6 and 2.7) doesn't let me boot a
> > buildroot-generated x86_64 image when QEMU is configured with
> > --with-coroutine=gthread (it deadlocks on the BQL shortly after
> > the framebuffer comes up.)
> >
>
On Mon, Oct 03, 2016 at 10:32:55 +0100, Alex Bennée wrote:
(snip)
> However the series as a whole does have value. As you can see from the
> other patches there are some real races being picked up by the sanitizer
> which only really become visible when a) you remove the noise of the
> "false" posi
On Mon, Oct 03, 2016 at 20:42:43 +0100, Alex Bennée wrote:
>
> Richard Henderson writes:
>
> > Add all of cmpxchg, op_fetch, fetch_op, and xchg.
> > Handle both endian-ness, and sizes up to 8.
> > Handle expanding non-atomically, when emulating in serial.
> >
> > Signed-off-by: Richard Henderson
On Fri, Sep 16, 2016 at 10:46:56 -0700, Richard Henderson wrote:
(snip)
> - QEMU does not currently properly distinguish between code/data when
> - looking up addresses. To avoid having to address this issue, our
> - emulated PALcode will cheat and use the KSEG mapping for its code+data
> -
On Fri, Sep 16, 2016 at 10:46:57 -0700, Richard Henderson wrote:
> Emulating LL/SC with cmpxchg is not correct, since it can
> suffer from the ABA problem. However, portable parallel
> code is writting assuming only cmpxchg which means that in
> practice this is a viable alternative.
s/writting/w
ady performs a reset without taking
ht->lock.
Reported-by: Peter Maydell
Reported-by: Daniel P. Berrange
Signed-off-by: Emilio G. Cota
---
util/qht.c | 49 -
1 file changed, 28 insertions(+), 21 deletions(-)
diff --git a/util/qht.c b/util/qht.c
Sometimes gcc doesn't pick up the fact that 'new' is properly
set if 'resize == true', which may generate an unnecessary
build warning.
Fix it by removing 'resize' and directly checking that 'new'
is non-NULL.
Signed-off-by: Emilio G. Cota
--
y the
rcu_after_fork hook, and therefore duplicating it here would
be a bug.
Signed-off-by: Emilio G. Cota
---
tests/test-qht.c | 4
1 file changed, 4 insertions(+)
diff --git a/tests/test-qht.c b/tests/test-qht.c
index 46a64b6..9b7423a 100644
--- a/tests/test-qht.c
+++ b/tests/test-qht.c
@@ -6,6
Patch 1 fixes a warning that gcc may unnecessarily emit.
Patch 2 fixes a real bug that sometimes shows up as a segfault in test-qht.
Daniel reported it yesterday on IRC; the trick to easily trigger it is to
run on RHEL6 (or CentOS6).
It is very likely that this is the test-qht failure that Peter r
pting to improve that yet---also because I could only really do
> that for x86.
Very happy with this update!
Reviewed-by: Emilio G. Cota
for the whole patchset.
Thanks,
Emilio
On Thu, Oct 06, 2016 at 17:24:22 +0200, Paolo Bonzini wrote:
> Drop most the device emulation part and merge the rest into the description
> of the MMU. Make some bits more up-to-date.
>
> Signed-off-by: Paolo Bonzini
(snip)
> The host SIGSEGV and SIGBUS signal handlers are used to get invalid
On Thu, Oct 06, 2016 at 17:24:18 +0200, Paolo Bonzini wrote:
> Unlike the other sections, they are pretty specific to a particular CPU.
>
> Signed-off-by: Paolo Bonzini
> ---
> qemu-tech.texi | 25 -
> target-cris/cpu.h | 7 +++
> target-i386/cpu.h | 7 +++
On Wed, Oct 12, 2016 at 10:58:43 +0200, Stefan Hajnoczi wrote:
> Hi Pranith,
> I was curious about the status of your MTTCG GSoC work:
>
> I saw your fence series which implements the noop memory barrier/fence
> instructions on various architectures, but I wasn't sure if that also
> covers the cas
On Mon, Oct 10, 2016 at 15:59:02 +0200, Paolo Bonzini wrote:
> See each patch. My attempt at fixing whatever I did when I obviously
> didn't know enough^W about the C11 memory model, and at setting a
> better example for future generations...
Just for context. Building on this patchset, is it now
On Mon, Oct 10, 2016 at 15:59:04 +0200, Paolo Bonzini wrote:
> There is a data race if the variable is written concurrently to the
> read. In C11 this has undefined behavior. Use atomic_read. The
> write side does not need atomic_set, because it is protected by a
> mutex.
Is tsan happy with the
the atomic_mb's, at least there should be a good reason for their
use--this is not the case below.
Emilio
commit cffdc51df4a6346f2b38425f1f1251aa12866fa8
Author: Emilio G. Cota
Date: Thu Oct 13 15:06:07 2016 -0400
qht-bench: relax test_start/stop atomic accesses
On Tue, Oct 11, 2016 at 14:40:52 -0500, Richard Henderson wrote:
> From: "Emilio G. Cota"
>
> With this microbenchmark we can measure the overhead of emulating atomic
> instructions with a configurable degree of contention.
>
> The benchmark spawns $n threads, e
(Adding Richard to Cc)
On Sat, Oct 15, 2016 at 23:53:48 +0800, Heiher wrote:
> From: Heiher
>
> test case: http://pastebin.com/raw/x2GW4xNW
You should check out this patchset and use it as a base for working on this
topic:
http://lists.nongnu.org/archive/html/qemu-devel/2016-10/msg02341.html
On Tue, Oct 11, 2016 at 14:40:39 -0500, Richard Henderson wrote:
> Add all of cmpxchg, op_fetch, fetch_op, and xchg.
> Handle both endian-ness, and sizes up to 8.
> Handle expanding non-atomically, when emulating in serial.
>
> Signed-off-by: Richard Henderson
> ---
> Makefile.objs | 2
06 for which I reviewed 1bfe0cdf8
from your atomic-4 branch on github):
Reviewed-by: Emilio G. Cota
I just tested the patchset by running concurrencykit's ck_pr regression test
(which
tests lock'ed ops) for [guest-on-host bits, all x86] 64-on-64, 32-on-32 and
64-on-32. I ran it with T
On Sun, Oct 16, 2016 at 18:40:05 -0700, Richard Henderson wrote:
> On 10/16/2016 03:17 PM, Emilio G. Cota wrote:
> >>+#if DATA_SIZE == 1
> >>> +# define END
> >>> +#elif defined(HOST_WORDS_BIGENDIAN)
> >>> +# define END _be
> >>> +#else
On Mon, Oct 17, 2016 at 09:17:35 +0100, Alex Bennée wrote:
>
> Emilio G. Cota writes:
>
> > On Tue, Oct 11, 2016 at 14:40:26 -0500, Richard Henderson wrote:
> >> Sixth time is the charm, right? This time I'm certain that it
> >> compiles with centos6, and
On Tue, Oct 18, 2016 at 09:28:10 +0100, Alex Bennée wrote:
> Emilio G. Cota writes:
> > I have not tested the ARM bits. I just tested aarch64 and it works, though.
> >
> > I put the scripts online so that others can easily generate natively the
> > ck_pr
> > tes
On Tue, Oct 18, 2016 at 10:56:20 -0400, Pranith Kumar wrote:
> gcc does not warn about the wrong type since it is a void pointer
> which can be cast to any type.
>
> Signed-off-by: Pranith Kumar
> ---
> translate-all.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tra
On Mon, Oct 24, 2016 at 10:39:12 -0700, Richard Henderson wrote:
> Making these functional rather than object macros will
> prevent later problems with complex macro expansion.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Emilio G. Cota
E.
-by: Richard Henderson
Reviewed-by: Emilio G. Cota
E.
On Mon, Oct 24, 2016 at 10:39:11 -0700, Richard Henderson wrote:
> Changes v7-v8:
> * Atomics fix for gcc 4.2 (centos6)
> * All atomic.h changes split out from 'tcg: Add atomic helpers',
> as requested by ... someone (Emilio?)
Yep that was me, thanks for doing it.
> * Unused function re
occ. Histogram: (null)
TB hash avg chain nan buckets. Histogram: (null)
[...]
Reported by: Changlong Xie
Signed-off-by: Emilio G. Cota
---
tests/test-qht.c | 4
util/qht.c | 7 ++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/tests/test-qht.c b/tests/test-qht
On Sat, Jul 23, 2016 at 12:54:51 +0200, Paolo Bonzini wrote:
> On 23/07/2016 12:01, Peter Maydell wrote:
> > On 22 July 2016 at 17:36, Emilio G. Cota wrote:
> > This looks like we're passing NULL pointers to
> > printf %s specifiers. This is undefined behaviour at least
Printf'ing a NULL string is undefined behaviour. Avoid it.
Reported-by: Peter Maydell
Signed-off-by: Emilio G. Cota
---
tests/test-qdist.c | 10 --
util/qdist.c | 6 --
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/tests/test-qdist.c b/tests/test-qd
While fixing the return of a NULL string when printing an empty
dist (patch 3) (see background here [*]), I noticed there was
a leak in qdist (patch 1). Patch 2 is trivial.
Thanks,
Emilio
[*] https://lists.gnu.org/archive/html/qemu-devel/2016-07/msg05494.html
In qdist_bin__internal(), to->entries is initialized to a 1-element array,
which we then leak when n == from->n. Fix it.
Signed-off-by: Emilio G. Cota
---
util/qdist.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/qdist.c b/util/qdist.c
index 56f5738..eb2236c
While at it, remove the unnecessary parentheses around dist->size.
Signed-off-by: Emilio G. Cota
---
util/qdist.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/util/qdist.c b/util/qdist.c
index eb2236c..cc31140 100644
--- a/util/qdist.c
+++ b/util/qdist.c
@@ -6
On Tue, Aug 02, 2016 at 18:27:44 +0100, Alex Bennée wrote:
> Under times of high memory stress the additional small mallocs by a
> linked list are source of potential memory fragmentation. As we have
> worked hard to avoid mallocs elsewhere when queuing work we might as
> well do the same for the l
On Tue, Aug 02, 2016 at 18:27:42 +0100, Alex Bennée wrote:
> From: Sergey Fedorov
>
> This patch is based on the ideas found in work of KONRAD Frederic [1],
> Alex Bennée [2], and Alvise Rigo [3].
>
> This mechanism allows to perform an operation safely in a quiescent
> state. Quiescent state me
On Wed, Aug 03, 2016 at 22:02:04 +0100, Alex Bennée wrote:
> Emilio G. Cota writes:
>
> > On Tue, Aug 02, 2016 at 18:27:42 +0100, Alex Bennée wrote:
(snip)
> >> +void wait_safe_cpu_work(void)
> >> +{
> >> +while (can_wait_for_safe() &a
On Tue, Jul 05, 2016 at 17:18:10 +0100, Alex Bennée wrote:
> Well this is the first re-spin of the series posted last week. I've
> added a bunch of additional patches to be more aggressive with
> avoiding bouncing locks but to be honest the numbers don't seem to
> make it worth it.
How many thread
On Fri, Jul 01, 2016 at 10:04:26 -0700, Richard Henderson wrote:
> I spent a couple evenings this week tweaking Emilio's patch set.
>
> The first major change is to "qemu/int128.h", so that we can use
> that type in the context of a 16-byte cmpxchg. I have yet to teach
> TCG code generation about
On Fri, Jul 01, 2016 at 10:04:36 -0700, Richard Henderson wrote:
> Force the use of cmpxchg16b on x86_64.
>
> Wikipedia suggests that only very old AMD64 (circa 2004) did not have
> this instruction. Further, it's required by Windows 8 so no new cpus
> will ever omit it.
>
> If we truely care ab
On Fri, Jul 01, 2016 at 10:04:37 -0700, Richard Henderson wrote:
> From: "Emilio G. Cota"
>
> The diff here is uglier than necessary. All this does is to turn
>
> FOO
>
> into:
>
> if (s->prefix & PREFIX_LOCK) {
> BAR
> } else {
> FOO
On Thu, Jul 07, 2016 at 23:08:17 -0400, Emilio G. Cota wrote:
> On Fri, Jul 01, 2016 at 10:04:37 -0700, Richard Henderson wrote:
> > From: "Emilio G. Cota"
> >
> > The diff here is uglier than necessary. All this does is to turn
> >
> > FOO
> >
On Fri, Jul 01, 2016 at 10:04:50 -0700, Richard Henderson wrote:
(snip)
> [rth: Rearrange 128-bit cmpxchg helper. Enforce alignment on LL.]
>
> Signed-off-by: Emilio G. Cota
> Message-Id: <1467054136-10430-28-git-send-email-c...@braap.org>
> Signed-off-by: Richard Henderson
On Tue, Jul 12, 2016 at 23:13:36 +0300, Sergey Fedorov wrote:
> From: Sergey Fedorov
> It is naturally expected that some memory ordering should be provided
> around qht_insert(), qht_remove(), and qht_lookup(). Document these
> assumptions in the header file and put some comments in the source to
en with `-accel accel=tcg,thread=single' (i.e. MTTCG disabled).
I isolated the problem to the MSR handler. This patch forces an exit
after the handler is executed, which fixes the regression.
Signed-off-by: Emilio G. Cota
---
target/arm/translate-a64.c | 6 +-
1 file changed, 5 insertio
use a variable for the tb_jmp_cache hash and get rid
of the goto's.
Suggested-by: Richard Henderson
Suggested-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
tcg-runtime.c | 20
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/tcg-runtime.c b/tcg-runtime.c
IRQ to move things on
> [ Message-Id: <20170614140209.29847-1-alex.ben...@linaro.org> ]
Fix it by enforcing an exit to the main loop right after 'msr daifclr'
is executed.
Signed-off-by: Emilio G. Cota
---
target/arm/translate-a64.c | 7 ++-
1 file changed, 6 insertions
tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUAlphaState, ps));
> tcg_temp_free(tmp);
> -break;
> +
> +/* Allow interrupts to be recognized right away. */
> +tcg_gen_movi_i64(cpu_pc, ctx.pc);
ctx->pc though
Tested-by: Emilio G. Cota
Thanks!
E.
.
Note that under "safe async" work (e.g. do_tb_flush) we could use memset
because no other vcpus are running. However I'm keeping these accesses
atomic as well to keep things simple and to avoid confusing analysis
tools such as ThreadSanitizer.
Signed-off-by: Emilio G. Cota
---
On Wed, Jun 14, 2017 at 18:20:29 -0700, Richard Henderson wrote:
> On 06/14/2017 01:33 PM, Emilio G. Cota wrote:
> >On Wed, Jun 14, 2017 at 12:48:21 -0700, Richard Henderson wrote:
> >>Exit to cpu loop so we reevaluate cpu_arm_hw_interrupts.
> >>
> >>Cc: qemu-
On Mon, Jun 12, 2017 at 17:53:47 +0300, Lluís Vilanova wrote:
> This series proposes a generic (target-agnostic) instruction translation
> framework.
>
> It basically provides a generic main loop for instruction disassembly, which
> calls target-specific functions when necessary. This generalizati
d aarch64
have been converted.
This applies on top of this series:
https://lists.gnu.org/archive/html/qemu-devel/2017-06/msg02833.html
Signed-off-by: Emilio G. Cota
---
Makefile.target| 2 +-
include/exec/exec-all.h| 2 +-
include/exec/gen-icount.h | 6 +-
include/ex
Some minor nits below.
On Mon, Jun 12, 2017 at 17:54:09 +0300, Lluís Vilanova wrote:
> Signed-off-by: Lluís Vilanova
> ---
> +/**
> + * BreakpointHitType:
> + * @BH_MISS: No hit
> + * @BH_HIT_INSN: Hit, but continue translating instruction
> + * @BH_HIT_TB: Hit, stop translating TB
> + *
> + * Ho
t by explicitly passing cpu_env to the gen_*
inlines that need it. This change also helps paving the way for
the upcoming "translation loop common to all targets" work.
Signed-off-by: Emilio G. Cota
---
include/exec/gen-icount.h | 6 +++---
target/alpha/translate.c | 14 +
Signed-off-by: Emilio G. Cota
---
include/exec/gen-icount.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h
index 62d462e..547c979 100644
--- a/include/exec/gen-icount.h
+++ b/include/exec/gen-icount.h
@@ -44,7 +44,7
On Thu, Jun 15, 2017 at 18:19:11 -0400, Emilio G. Cota wrote:
> (snip)
> > +/**
> > + * DisasContextBase:
> > + * @tb: Translation block for this disassembly.
> > + * @pc_first: Address of first guest instruction in this TB.
> > + * @pc_next: Address of next gues
On Mon, Jun 12, 2017 at 17:54:30 +0300, Lluís Vilanova wrote:
> Signed-off-by: Lluís Vilanova
> ---
> target/arm/translate-a64.c | 346 ++---
> target/arm/translate.c | 720
> ++--
> target/arm/translate.h | 46 ++-
> 3 files ch
On Fri, Jun 16, 2017 at 10:32:14 +0200, Paolo Bonzini wrote:
> On 16/06/2017 01:04, Emilio G. Cota wrote:
> > va = dest_gpr(ctx, ra);
> > if (ctx->tb->cflags & CF_USE_ICOUNT) {
> > -gen_io_start();
> >
Reviewed-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
include/exec/gen-icount.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h
index 62d462e..547c979 100644
--- a/include/exec/gen-icount.h
+++ b/include/exec
v1: https://lists.gnu.org/archive/html/qemu-devel/2017-06/msg03771.html
Changes from v1:
- Use tcg_ctx.tcg_env instead of passing cpu_env around as suggested
by Richard.
- Added Richard's R-b tag to patch 1.
Thanks,
Emilio
tcg_ctx.tcg_env, which all targets set in their
translate_init function. This change also helps paving the way
for the upcoming "translation loop common to all targets" work.
Signed-off-by: Emilio G. Cota
---
include/exec/gen-icount.h | 10 ++
1 file changed, 6 insertions(+), 4 d
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