On 2/1/24 23:14, Alistair Francis wrote:
On Thu, Feb 1, 2024 at 5:15 AM Daniel Henrique Barboza
wrote:
On 1/29/24 22:10, Alistair Francis wrote:
On Fri, Jan 26, 2024 at 5:54 AM Daniel Henrique Barboza
wrote:
The RVA22U64 and RVA22S64 profiles mandates certain extensions that,
until
On 1/31/24 15:24, Palmer Dabbelt wrote:
Right now we just report 0 for marchid/mvendorid in QEMU. That's legal,
but it's tricky for users that want to check if they're running on QEMU
to do so. This sets marchid to 42, which I've proposed as the QEMU
architecture ID (mvendorid remains 0, jus
Alistair,
I think we should just queue this up since it's all acked. It's still
applicable in riscv-to-apply.next.
Thanks,
Daniel
On 1/22/24 09:33, Daniel Henrique Barboza wrote:
Hi,
This v3 has the same patches from v2 rebased with a newer
riscv-to-apply.next branch (@ 096b6b0
("target/riscv: Add *envcfg.HADE related check in address
translation")
Fixes: ed67d63798f2 ("target/riscv: Update CSR bits name for svadu extension")
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Andrew Jones
---
target/riscv/cpu.c | 3 +--
target/riscv/csr.c | 2 +-
2 fil
ch to hardware updating
(this behavior change fixes [2])
Fixes: 0af3f115e68e ("target/riscv: Add *envcfg.HADE related check in address
translation") [1]
Fixes: 48531f5adb2a ("target/riscv: implement svade") [2]
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Andrew
7;rva22s64' CPU:
# cat /proc/device-tree/cpus/cpu@0/riscv,isa
rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_
zicntr_zicsr_zifencei_zihintpause_zihpm_za64rs_zfhmin_zca_zcd_zba_zbb_
zbs_zkt_ssccptr_sscounterenw_sstvala_sstvecd_svade_svinval_svpbmt#
Signed-o
7;mmu' in this case.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
target/riscv/tcg/tcg-cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index da437975b4..88f92d1c7d 100644
--- a/target/riscv/tcg/tc
d
priv_spec versions;
- skip name feature check in cpu_bump_multi_ext_priv_ver(). Now that
named features have a riscv,isa and an entry in isa_edata_arr[] we
don't need to gate the call to cpu_cfg_ext_get_min_version() anymore.
[1] https://github.com/riscv/riscv-profiles/issues/121
[2] ht
ernel.org/qemu-riscv/20240125195319.329181-1-dbarb...@ventanamicro.com/
Andrew Jones (3):
target/riscv: Reset henvcfg to zero
target/riscv: Gate hardware A/D PTE bit updating
target/riscv: Promote svade to a normal extension
Daniel Henrique Barboza (3):
target/riscv/tcg: set 'mmu' with '
for the max
cpu type, since QEMU has always implemented hardware A/D PTE bit
updating, so users must opt into svade (or get it from a CPU type
which enables it by default).
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Andrew Jones
---
target/riscv/cpu.c | 9 ++---
target/risc
On 2/5/24 04:00, Alexandre Ghiti wrote:
Currently, the initrd is placed at 128MB, which overlaps with the kernel
when it is large (for example syzbot kernels are). From the kernel side,
there is no reason we could not push the initrd further away in memory
to accomodate large kernels, so move
On 2/6/24 06:41, Alexandre Ghiti wrote:
Hi Daniel,
On Mon, Feb 5, 2024 at 2:36 PM Alexandre Ghiti wrote:
Hi Daniel,
On Mon, Feb 5, 2024 at 1:17 PM Daniel Henrique Barboza
wrote:
On 2/5/24 04:00, Alexandre Ghiti wrote:
Currently, the initrd is placed at 128MB, which overlaps with
ff-by: Alexandre Ghiti
---
Reviewed-by: Daniel Henrique Barboza
Changes in v2:
- Fix typos in commit log (Daniel) and title
- Added to the commit log why using the kernel size does not work
(Daniel)
hw/riscv/boot.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
*SEW(16/32)
Signed-off-by: Max Chou
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/insn_trans/trans_rvv.c.inc | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
convert single width
integer to double width float, so the opfxv_widen_check function doesn’t
need require_rvf for the single width operator(integer).
Signed-off-by: Max Chou
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/insn_trans/trans_rvv.c.inc | 5 +
1 file changed, 5
On 3/20/24 04:25, Max Chou wrote:
The opfv_narrow_check needs to check the single width float operator by
require_rvf.
Signed-off-by: Max Chou
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/target
On 3/20/24 04:25, Max Chou wrote:
If the checking functions check both the single and double width
operators at the same time, then the single width operator checking
functions (require_rvf[min]) will check whether the SEW is 8.
Signed-off-by: Max Chou
---
Reviewed-by: Daniel Henrique
On 3/20/24 14:28, Irina Ryapolova wrote:
Need to convert mmu_idx to privilege mode for PMP function.
Please add:
Fixes: b297129ae1 ("target/riscv: propagate PMP permission to TLB page")
Signed-off-by: Irina Ryapolova
---
Reviewed-by: Daniel Henrique Barboza
ta
Hi,
This patch doesn't apply in master or alistair/riscv-to-apply.next. Can you
please re-send?
Thanks,
Daniel
On 3/20/24 13:42, Irina Ryapolova wrote:
CSR hvictl (Hypervisor Virtual Interrupt Control) provides further flexibility
for injecting interrupts into VS level in situations not fu
On 3/6/24 14:08, Jason Chien wrote:
Signed-off-by: Jason Chien
Reviewed-by: Frank Chang
Reviewed-by: Max Chou
---
Please add the following tag in this commit msg:
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
The link is a feature request named "target/riscv: zve32x/zve
t least. Thanks,
Daniel
Thanks,
/mjt
--------
Daniel Henrique Barboza (10):
target/riscv: do not enable all named features by default
target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
trans
On 3/24/24 12:07, Michael Tokarev wrote:
22.03.2024 22:46, Daniel Henrique Barboza :
On 3/22/24 14:16, Michael Tokarev wrote:
22.03.2024 11:53, Alistair Francis :
RISC-V PR for 9.0
* Do not enable all named features by default
* A range of Vector fixes
* Update APLIC IDC after claiming
V_SBI exit")
Signed-off-by: Alexei Filippov
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/kvm/kvm-cpu.c | 5 +++--
target/riscv/sbi_ecall_interface.h | 11 +++
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/riscv/kvm/kvm-cpu.c b/targe
On 3/25/24 06:20, Thomas Huth wrote:
On 08/03/2024 12.11, Alistair Francis wrote:
From: Daniel Henrique Barboza
Add a RISC-V 'virt' machine to the graph. This implementation is a
modified copy of the existing arm machine in arm-virt-machine.c
It contains a virtio-mmio and
On 3/26/24 06:56, Alistair Francis wrote:
On Tue, Mar 26, 2024 at 7:53 PM Michael Tokarev wrote:
On 24.03.2024 21:12, Daniel Henrique Barboza wrote:
On 3/24/24 12:07, Michael Tokarev wrote:
Unfortunately this doesn't quite work, the following changes
fail to apply to 8.2:
929e5
Gitlab pipeline:
https://gitlab.com/danielhb/qemu/-/pipelines/1227953967
[1] https://mail.gnu.org/archive/html/qemu-devel/2024-03/msg05807.html
[2] https://lists.nongnu.org/archive/html/qemu-devel/2020-11/msg05510.html
Daniel Henrique Barboza (3):
qtest/virtio-9p-test.c: consolidate create dir, f
-v machine
nodes faced the same issue [1]. We're now able to run these tests with
'make check' in the CI.
This reverts commit 558f5c42efded3e0d0b20a90bce2a9a14580d824.
[1] https://mail.gnu.org/archive/html/qemu-devel/2024-03/msg05807.html
Signed-off-by: Daniel Henrique Barboza
-
symlink(). Both "real_file" and the "06" dir it
creates is now being removed.
We're still missing the 'hardlink' tests. We'll do it in the next patch
since it's less trivial to consolidate than these.
[1] https://mail.gnu.org/archive/html/qemu-devel/
] https://mail.gnu.org/archive/html/qemu-devel/2024-03/msg05807.html
Reported-by: Thomas Huth
Signed-off-by: Daniel Henrique Barboza
---
tests/qtest/virtio-9p-test.c | 55 +++-
1 file changed, 22 insertions(+), 33 deletions(-)
diff --git a/tests/qtest/virtio-9p-tes
On 3/26/24 12:55, Greg Kurz wrote:
Bom dia Daniel !
Bonne après-midi !
On Tue, 26 Mar 2024 10:26:03 -0300
Daniel Henrique Barboza wrote:
Hi,
Thomas reported in [1] a problem that happened with the RISC-V machine
where some tests from virtio-9p-test.c were failing with '-m slow&
On 3/26/24 14:05, Greg Kurz wrote:
On Tue, 26 Mar 2024 10:26:04 -0300
Daniel Henrique Barboza wrote:
The local 9p driver in virtio-9p-test.c its temporary dir right at the
start of qos-test (via virtio_9p_create_local_test_dir()) and only
deletes it after qos-test is finished (via
hange fs_create_unlinkat_file() to also remove the created dir.
The remaining tests got their dir changed to reflect that we're now with
one less test.
Reported-by: Thomas Huth
Signed-off-by: Daniel Henrique Barboza
---
tests/qtest/virtio-9p-test.c | 42 ++
patch.
Signed-off-by: Daniel Henrique Barboza
---
tests/qtest/virtio-9p-test.c | 64
1 file changed, 35 insertions(+), 29 deletions(-)
diff --git a/tests/qtest/virtio-9p-test.c b/tests/qtest/virtio-9p-test.c
index 65e69491e5..23edca05c5 100644
--- a/tests/qtes
rg/archive/html/qemu-devel/2024-03/msg05807.html
Reported-by: Thomas Huth
Signed-off-by: Daniel Henrique Barboza
---
tests/qtest/virtio-9p-test.c | 52 +++-
1 file changed, 16 insertions(+), 36 deletions(-)
diff --git a/tests/qtest/virtio-9p-test.c b/tests/qt
ly:
- fs_create_dir() is removed. s_unlinkat_dir() is renamed to
fs_create_unlinkat_dir();
- update the dir names for every other test since we have 1 less test.
[1] https://mail.gnu.org/archive/html/qemu-devel/2024-03/msg05807.html
Reported-by: Thomas Huth
Signed-off-by: Daniel Henrique Barboza
---
tests/qt
-v machine
nodes faced the same issue [1]. We're now able to run these tests with
'make check' in the CI.
This reverts commit 558f5c42efded3e0d0b20a90bce2a9a14580d824.
[1] https://mail.gnu.org/archive/html/qemu-devel/2024-03/msg05807.html
Signed-off-by: Daniel Henrique Barboza
-
e changes, changing the val of "new_dir" will change all dir
references the test uses.
Signed-off-by: Daniel Henrique Barboza
---
tests/qtest/virtio-9p-test.c | 108 +++
1 file changed, 72 insertions(+), 36 deletions(-)
diff --git a/tests/qtest/virtio-
x27; name
- patches 3, 4, 5, 6 (new):
- individual test consolidation
- v1 link: https://mail.gnu.org/archive/html/qemu-devel/2024-03/msg06146.html
Daniel Henrique Barboza (7):
qtest/virtio-9p-test.c: add '_path' in path vars
qtest/virtio-9p-test.c: parametrize 'dir' name in
named
fs_create_unlinkat_symlink();
- remove 'real_file' and the created dir at the end of
fs_create_unlinkat_symlink().
The hardlink tests dir names were updated because now we have one less
test.
Reported-by: Thomas Huth
Signed-off-by: Daniel Henrique Barboza
---
tests/qtest
On 3/27/24 05:47, Christian Schoenebeck wrote:
On Tuesday, March 26, 2024 6:47:17 PM CET Daniel Henrique Barboza wrote:
On 3/26/24 14:05, Greg Kurz wrote:
On Tue, 26 Mar 2024 10:26:04 -0300
Daniel Henrique Barboza wrote:
The local 9p driver in virtio-9p-test.c its temporary dir right at
On 3/27/24 07:14, Christian Schoenebeck wrote:
On Wednesday, March 27, 2024 10:33:27 AM CET Daniel Henrique Barboza wrote:
On 3/27/24 05:47, Christian Schoenebeck wrote:
On Tuesday, March 26, 2024 6:47:17 PM CET Daniel Henrique Barboza wrote:
On 3/26/24 14:05, Greg Kurz wrote:
On Tue, 26
On 3/27/24 09:26, Christian Schoenebeck wrote:
On Wednesday, March 27, 2024 12:28:17 PM CET Daniel Henrique Barboza wrote:
On 3/27/24 07:14, Christian Schoenebeck wrote:
On Wednesday, March 27, 2024 10:33:27 AM CET Daniel Henrique Barboza wrote:
On 3/27/24 05:47, Christian Schoenebeck
ble them.
This reverts commit 558f5c42efded3e0d0b20a90bce2a9a14580d824.
[1] https://mail.gnu.org/archive/html/qemu-devel/2024-03/msg05807.html
Signed-off-by: Daniel Henrique Barboza
---
tests/qtest/virtio-9p-test.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/tests/qtest/virtio-9p-
oach taken for other qtests like vhost-user-test.c where each test
requires a setup() and a subsequent cleanup(), all of those instantiated
in the .before callback.
[1] https://mail.gnu.org/archive/html/qemu-devel/2024-03/msg05807.html
Reported-by: Thomas Huth
Signed-off-by: Daniel Henriq
hive/html/qemu-devel/2024-03/msg06400.html
Daniel Henrique Barboza (2):
qtest/virtio-9p-test.c: create/remove temp dirs after each test
qtest/virtio-9p-test.c: remove g_test_slow() gate
tests/qtest/virtio-9p-test.c | 32 +++-
1 file changed, 11 insertions(+), 21 deletions(-)
--
2.44.0
On 3/25/24 05:33, Jason Chien wrote:
Add support for Zve32x extension and replace some checks for Zve32f with
Zve32x, since Zve32f depends on Zve32x.
Signed-off-by: Jason Chien
Reviewed-by: Frank Chang
Reviewed-by: Max Chou
---
Reviewed-by: Daniel Henrique Barboza
target/riscv
I think this patch should be squashed into patch 1. Patch 1 as is
does nothing since there's no way of enabling the flag without this
patch.
Same thing with patch 4: I think it should be squashed into patch 3.
Thanks,
Daniel
On 3/25/24 05:33, Jason Chien wrote:
Signed-off-by: Jason Chien
R
On 3/25/24 05:33, Jason Chien wrote:
Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
enabling Zve64x enables Zve32x according to their dependency.
Signed-off-by: Jason Chien
Reviewed-by: Frank Chang
Reviewed-by: Max Chou
---
Reviewed-by: Daniel Henrique Barboza
On 3/27/24 15:53, Christian Schoenebeck wrote:
On Wednesday, March 27, 2024 3:20:09 PM CET Daniel Henrique Barboza wrote:
Hi,
In this new version we took a different approach after the discussions
we had in [1]. The tests are now untouched, and we're addressing the root
cause directly
c_realize() and we won't create
the adequate IRQ lines.
Signed-off-by: yang.zhang
---
Please add:
Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
And:
Reviewed-by: Daniel Henrique Barboza
hw/intc/riscv_aplic.c | 8
1 file changed, 4
Hi Jason,
We're in the middle of code freeze for the incoming 9.0 release. In this
period the maintainer will only queue bug fixes.
Your support is a new feature, so it'll only be pushed after the release is
done. Current ETA for the release is Apr 16th if there's no rc4. A safe
bet is to expec
On 3/29/24 10:45, Alexei Filippov wrote:
Successed two stage translation, but failed pmp check can cause guest
page fault instead of regular page fault.
In case of execution ld instuction in VS mode we can
face situation when two stages of translation was passed successfully,
and if PMP check
xception() to prioritize it.
Reported-by: Joseph Chan
Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU
translation stage")
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu_helper.c | 22 --
1 file changed, 12 insertions(+), 10 deleti
On 3/22/24 00:59, Alistair Francis wrote:
On Wed, Mar 20, 2024 at 7:33 PM Daniel Henrique Barboza
wrote:
We're not setting (s/m)tval when triggering breakpoints of type 2
(mcontrol) and 6 (mcontrol6). According to the debug spec section
5.7.12, "Match Control Type 6":
"
translation. If the helper is setting
vstart = 0 the helper must also deal with any invalid value of vstart
accordingly.
Thanks,
Daniel
I will review this patch set in more details later.
Thanks,
Zhiwei
On 2024/3/7 1:19, Daniel Henrique Barboza wrote:
Most of the vector translations has this
On 3/8/24 08:13, Alistair Francis wrote:
On Fri, Mar 8, 2024 at 8:40 PM Daniel Henrique Barboza
wrote:
On 3/8/24 00:34, LIU Zhiwei wrote:
Hi Daniel and Alistair,
Hope it is not too late. I think there are two bugs in this patch.
1) The first is for instruction vfmv.s.f. vfmv.s.f
t after the helper from now on.
We'll enforce the use of this helper to update tail elements on all
instructions, making everyone able to skip the tail update if vstart
isn't adequate.
Let's also simplify the API a little by removing the 'nf' argument since
it
o
mandate a mark_vs_dirty() too.
Fixes: dedc53cbc9 ("target/riscv: rvv-1.0: integer scalar move instructions")
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvv.c.inc | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/target/
at a lot of 'vta' local variables got
unused. The reason is that 'vta' was being fetched to be used with
vext_set_elems_1s() but vext_set_tail_elems_1s() doesn't use it - 'vta' is
retrieve inside the helper using 'desc'.
Signed-off-by: Dan
start = 0 after vext_set_elems_1s() now to make the
conversion easier.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/vector_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index db1d3f77ce..54423
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1976
Signed-off-by: Ivan Klokov
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvbf16.c.inc | 6 +-
target/riscv/insn_trans/trans_rvv.c.in
The helper isn't setting env->vstart = 0 after its execution, as it is
expected from every vector instruction that completes successfully.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/vector_helper.c | 1 +
1 file
trans_vmv_v_i , trans_vfmv_v_f and the trans_##NAME macro from
GEN_VMV_WHOLE_TRANS() are calling mark_vs_dirty() in both branches of
their 'ifs'. conditionals.
Call it just once in the end like other functions are doing.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard
move the (vl == 0) brconds from trans_rvbf16.c.inc
too since they're unneeded.
Suggested-by: Richard Henderson
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvbf16.c.inc | 12 ---
target/riscv/
Change the for loops in ldst helpers to do a single increment in the
counter, and assign it env->vstart, to avoid re-reading from vstart
every time.
Suggested-by: Richard Henderson
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
tar
cond.
- patches 4 and 5 from v7: dropped. We're not removing all brconds, so
we can't get rid of cpu_vstart and cpu_vl.
Series based on alistair/riscv-to-apply.next.
Patches missing review: 2, 3, 4, 5, 6.
Daniel Henrique Barboza (9):
target/riscv/vector_helper.c: set vstart = 0
ter setting the
tail.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/vcrypto_helper.c | 63 -
target/riscv/vector_helper.c| 25 -
target/riscv/vector_internals.c | 28 +++
target/riscv/vector_internals.h | 4 +++
4 files chan
On 3/9/24 17:14, Richard Henderson wrote:
On 3/8/24 11:53, Daniel Henrique Barboza wrote:
- patch 7 (patch 3 from v7): do not remove brconds from scalar move
insns
trans_vmv_s_x() and trans_vfmv_s_f() does not have a helper that will
handle vstart >= vl for them, so they need th
_us()
and vext_ldst_index() if vstart >= vl
- patch 6:
- vec_set_vstart_zero() removed
- set cpu_vstart directly using tcg_gen_movi_tl()
- v8 link:
https://lore.kernel.org/qemu-riscv/20240308215402.117405-1-dbarb...@ventanamicro.com/
Daniel Henrique Barboza (9):
target/riscv/vector_helper.
start = 0 after vext_set_elems_1s() now to make the
conversion easier.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/vector_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index a3b496b6e9..86b99
The helper isn't setting env->vstart = 0 after its execution, as it is
expected from every vector instruction that completes successfully.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/vector_helper.c | 1 +
1 file
o
mandate a mark_vs_dirty() too.
Fixes: dedc53cbc9 ("target/riscv: rvv-1.0: integer scalar move instructions")
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvv.c.inc | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/target/riscv/i
rest after the next
patches.
Let's also simplify the API a little by removing the 'nf' argument since
it can be derived from 'desc'.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/vector_helper.c | 59 ++--
1 file changed, 4
at a lot of 'vta' local variables got
unused. The reason is that 'vta' was being fetched to be used with
vext_set_elems_1s() but vext_set_tail_elems_1s() doesn't use it - 'vta' is
retrieve inside the helper using 'desc'.
Signed-off-by: Dan
move the (vl == 0) brconds from trans_rvbf16.c.inc
too since they're unneeded.
Suggested-by: Richard Henderson
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvbf16.c.inc | 12 ---
target/riscv/
trans_vmv_v_i , trans_vfmv_v_f and the trans_##NAME macro from
GEN_VMV_WHOLE_TRANS() are calling mark_vs_dirty() in both branches of
their 'ifs'. conditionals.
Call it just once in the end like other functions are doing.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard
ter setting the
tail.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/vcrypto_helper.c | 63 -
target/riscv/vector_helper.c| 30
target/riscv/vector_internals.c | 29 +++
target/riscv/vector_internals.h | 4 +++
4 fi
Change the for loops in ldst helpers to do a single increment in the
counter, and assign it env->vstart, to avoid re-reading from vstart
every time.
Suggested-by: Richard Henderson
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
tar
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1976
Signed-off-by: Ivan Klokov
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvbf16.c.inc | 6 +-
target/riscv/insn_trans/trans_rvv.c.in
On 3/10/24 04:41, Richard Henderson wrote:
On 3/9/24 10:43, Daniel Henrique Barboza wrote:
Change all code that updates tail elems to use vext_set_tail_elems_1s()
instead of vext_set_elems_1s().
Setting 'env->vstart=0' needs to be the very last thing a helper does
because e
On 3/10/24 04:47, Richard Henderson wrote:
On 3/9/24 10:43, Daniel Henrique Barboza wrote:
From: Ivan Klokov
The vstart_qe_zero flag is set at the beginning of the translation
Here and subject, s/qe/ne/.
H ... the flag name is correct - vstart_qe_zero. But the patch isn't
cle
27; in the end of insns"
- changed first line of the commit msg from:
"The vstart_qe_zero flag is set at the beginning of the translation"
to:
"The vstart_qe_zero flag is updated at the beginning of the translation"
- v9 link:
https://lore.kernel.org/qemu
o
mandate a mark_vs_dirty() too.
Fixes: dedc53cbc9 ("target/riscv: rvv-1.0: integer scalar move instructions")
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 10 --
1 file changed, 8 insertions(+), 2 dele
start = 0 after vext_set_elems_1s() now to make the
conversion easier.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
---
target/riscv/vector_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/
The helper isn't setting env->vstart = 0 after its execution, as it is
expected from every vector instruction that completes successfully.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/vector_helper.c | 1 +
1 file
at a lot of 'vta' local variables got
unused. The reason is that 'vta' was being fetched to be used with
vext_set_elems_1s() but vext_set_tail_elems_1s() doesn't use it - 'vta' is
retrieve inside the helper using 'desc'.
Signed-off-by: Daniel Henriq
ter setting the
tail.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
---
target/riscv/vcrypto_helper.c | 63 -
target/riscv/vector_helper.c| 30
target/riscv/vector_internals.c | 29 +++
target/ri
trans_vmv_v_i , trans_vfmv_v_f and the trans_##NAME macro from
GEN_VMV_WHOLE_TRANS() are calling mark_vs_dirty() in both branches of
their 'ifs'. conditionals.
Call it just once in the end like other functions are doing.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard
move the (vl == 0) brconds from trans_rvbf16.c.inc
too since they're unneeded.
Suggested-by: Richard Henderson
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvbf16.c.inc | 12 ---
target/riscv/
Change the for loops in ldst helpers to do a single increment in the
counter, and assign it env->vstart, to avoid re-reading from vstart
every time.
Suggested-by: Richard Henderson
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
tar
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1976
Signed-off-by: Ivan Klokov
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvbf16.c.inc | 6 +-
target/riscv/insn_trans/trans_rvv.c.in
rest after the next
patches.
Let's also simplify the API a little by removing the 'nf' argument since
it can be derived from 'desc'.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
---
target/riscv/vector_helper.c | 59 +++
On 3/10/24 15:04, Richard Henderson wrote:
On 3/10/24 00:17, Daniel Henrique Barboza wrote:
On 3/10/24 04:47, Richard Henderson wrote:
On 3/9/24 10:43, Daniel Henrique Barboza wrote:
From: Ivan Klokov
The vstart_qe_zero flag is set at the beginning of the translation
Here and subject
exit in vector helpers if vstart >= vl
- patch 6 (former patch 9):
- fix 'vstart_qe_zero' commit msg references to 'vstart_eq_zero'
- v10 link:
https://lore.kernel.org/qemu-riscv/20240310115315.187283-1-dbarb...@ventanamicro.com/
Daniel Henrique Barboza (6):
target/riscv/
trans_vmv_v_i , trans_vfmv_v_f and the trans_##NAME macro from
GEN_VMV_WHOLE_TRANS() are calling mark_vs_dirty() in both branches of
their 'ifs'. conditionals.
Call it just once in the end like other functions are doing.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard
The helper isn't setting env->vstart = 0 after its execution, as it is
expected from every vector instruction that completes successfully.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/vector_helper.c | 1 +
1 file
move the (vl == 0) brconds from trans_rvbf16.c.inc
too since they're unneeded.
Suggested-by: Richard Henderson
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvbf16.c.inc | 12 ---
target/riscv/
o
mandate a mark_vs_dirty() too.
Fixes: dedc53cbc9 ("target/riscv: rvv-1.0: integer scalar move instructions")
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 10 --
1 file changed, 8 insertions(+), 2 dele
arly exit in every single
vector helper if vstart >= vl. We can worry about unifying the tail
update process later.
[1]
https://lore.kernel.org/qemu-riscv/1590234b-0291-432a-a0fa-c5a687609...@linux.alibaba.com/
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/vcrypto_helper.c | 3
Change the for loops in ldst helpers to do a single increment in the
counter, and assign it env->vstart, to avoid re-reading from vstart
every time.
Suggested-by: Richard Henderson
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
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