[PATCH 1/7] vfio/igd: return an invalid generation for unknown devices

g a random generation value and hoping that everthing works fine, we should verify that different devices are working and add them to our list of known devices. Signed-off-by: Corvin Köhne --- hw/vfio/igd.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/vfio/igd.c b/hw/

[PATCH 0/7] vfio/igd: add passthrough support for IGDs of gen 11 and later

. I've tested the patch series on an ElkhartLake and TigerLake device. On the guest side, I've tested an EFI environment (GOP driver), a Linux guest and a Windows VM. The driver of all guests are able to use the GPU and produce an output on the connected display. Corvin Köhne (7): vfio/igd:

[PATCH 3/7] vfio/igd: use new BDSM register location and size for gen 11 and later

Intel changed the location and size of the BDSM register for gen 11 devices and later. We have to adjust our emulation for these devices to properly support them. Signed-off-by: Corvin Köhne --- hw/vfio/igd.c | 31 --- 1 file changed, 24 insertions(+), 7 deletions

[PATCH 4/7] vfio/igd: add new bar0 quirk to emulate BDSM mirror

i/passthrough.c#L650-L653 Signed-off-by: Corvin Köhne --- hw/vfio/igd.c| 97 hw/vfio/pci-quirks.c | 1 + hw/vfio/pci.h| 1 + 3 files changed, 99 insertions(+) diff --git a/hw/vfio/igd.c b/hw/vfio/igd.c index 0b6533bbf7..863b58565e 10064

[PATCH 2/7] vfio/igd: support legacy mode for all known generations

tion. Signed-off-by: Corvin Köhne --- hw/vfio/igd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/vfio/igd.c b/hw/vfio/igd.c index 650a323dda..d5e57656a8 100644 --- a/hw/vfio/igd.c +++ b/hw/vfio/igd.c @@ -416,7 +416,7 @@ void vfio_probe_igd_bar4_quirk(VFIOPCI

[PATCH 7/7] vfio/igd: correctly calculate stolen memory size for gen 9 and later

450ba/arch/x86/kernel/early-quirks.c#L455-L460 Signed-off-by: Corvin Köhne --- hw/vfio/igd.c | 15 +++ 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/hw/vfio/igd.c b/hw/vfio/igd.c index 122432e6a6..70c60fe7bc 100644 --- a/hw/vfio/igd.c +++ b/hw/vfio/igd.c @@ -487,11 +4

[PATCH 5/7] vfio/igd: add ID's for ElkhartLake and TigerLake

ElkhartLake and TigerLake devices were tested in legacy mode with Linux and Windows VMs. Both are working properly. It's likely that other Intel GPUs of gen 11 and 12 like IceLake device are working too. However, we're only adding known good devices for now. Signed-off-by: Corvin Köhn

[PATCH 6/7] vfio/igd: don't set stolen memory size to zero

rwrite the stolen memory size. It's true that this wastes some VM memory. In the worst case, the stolen memory can take up more than a GB. However, that's uncommon. Additionally, it's likely that a bunch of RAM is assigned to VMs making use of GPU passthrough. Signed-off-by: Corvin Köhne

[PATCH v2 1/7] vfio/igd: return an invalid generation for unknown devices

g a random generation value and hoping that everthing works fine, we should verify that different devices are working and add them to our list of known devices. Signed-off-by: Corvin Köhne --- hw/vfio/igd.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/vfio/igd.c b/hw/

[PATCH v2 4/7] vfio/igd: add new bar0 quirk to emulate BDSM mirror

i/passthrough.c#L650-L653 Signed-off-by: Corvin Köhne --- v2: * omit unnecessary leXX_to_cpu calls * make use of IGD_BDSM_MMIO_OFFSET define hw/vfio/igd.c| 98 hw/vfio/pci-quirks.c | 1 + hw/vfio/pci.h| 1 + 3 fil

[PATCH v2 2/7] vfio/igd: support legacy mode for all known generations

tion. Signed-off-by: Corvin Köhne --- hw/vfio/igd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/vfio/igd.c b/hw/vfio/igd.c index 650a323dda..d5e57656a8 100644 --- a/hw/vfio/igd.c +++ b/hw/vfio/igd.c @@ -416,7 +416,7 @@ void vfio_probe_igd_bar4_quirk(VFIOPCI

[PATCH v2 0/7] vfio/igd: add passthrough support for IGDs of gen 11 and later

. I've tested the patch series on an ElkhartLake and TigerLake device. On the guest side, I've tested an EFI environment (GOP driver), a Linux guest and a Windows VM. The driver of all guests are able to use the GPU and produce an output on the connected display. Corvin Köhne (7): vfio/igd:

[PATCH v2 3/7] vfio/igd: use new BDSM register location and size for gen 11 and later

Intel changed the location and size of the BDSM register for gen 11 devices and later. We have to adjust our emulation for these devices to properly support them. Signed-off-by: Corvin Köhne --- hw/vfio/igd.c | 31 --- 1 file changed, 24 insertions(+), 7 deletions

[PATCH v2 6/7] vfio/igd: don't set stolen memory size to zero

rwrite the stolen memory size. It's true that this wastes some VM memory. In the worst case, the stolen memory can take up more than a GB. However, that's uncommon. Additionally, it's likely that a bunch of RAM is assigned to VMs making use of GPU passthrough. Signed-off-by: Corvin Köhne

[PATCH v2 7/7] vfio/igd: correctly calculate stolen memory size for gen 9 and later

450ba/arch/x86/kernel/early-quirks.c#L455-L460 Signed-off-by: Corvin Köhne --- hw/vfio/igd.c | 15 +++ 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/hw/vfio/igd.c b/hw/vfio/igd.c index 0751c43eae..a95d441f68 100644 --- a/hw/vfio/igd.c +++ b/hw/vfio/igd.c @@ -488,11 +4

[PATCH v2 5/7] vfio/igd: add ID's for ElkhartLake and TigerLake

ElkhartLake and TigerLake devices were tested in legacy mode with Linux and Windows VMs. Both are working properly. It's likely that other Intel GPUs of gen 11 and 12 like IceLake device are working too. However, we're only adding known good devices for now. Signed-off-by: Corvin Köhn

Re: [PATCH 4/7] vfio/igd: add new bar0 quirk to emulate BDSM mirror

On Wed, 2024-08-28 at 12:40 +0200, Corvin Köhne wrote: > On Mon, 2024-08-26 at 10:35 -0600, Alex Williamson wrote: > > > > PS - please drop the confidential email warning signature when > > posting > > to public lists. > > > > Sry for the noise. I can'

Re: [PATCH 4/7] vfio/igd: add new bar0 quirk to emulate BDSM mirror

On Mon, 2024-08-26 at 10:35 -0600, Alex Williamson wrote: > CAUTION: External Email!! > On Thu, 22 Aug 2024 13:08:29 +0200 > Corvin Köhne wrote: > > > The BDSM register is mirrored into MMIO space at least for gen 11 > > and > > later devices. Unfortunately

[PATCH v3 5/7] vfio/igd: add ID's for ElkhartLake and TigerLake

ElkhartLake and TigerLake devices were tested in legacy mode with Linux and Windows VMs. Both are working properly. It's likely that other Intel GPUs of gen 11 and 12 like IceLake device are working too. However, we're only adding known good devices for now. Signed-off-by: Corvin Köhn

[PATCH v3 2/7] vfio/igd: support legacy mode for all known generations

tion. Signed-off-by: Corvin Köhne --- hw/vfio/igd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/vfio/igd.c b/hw/vfio/igd.c index 650a323dda..d5e57656a8 100644 --- a/hw/vfio/igd.c +++ b/hw/vfio/igd.c @@ -416,7 +416,7 @@ void vfio_probe_igd_bar4_quirk(VFIOPCI

[PATCH v3 7/7] vfio/igd: correctly calculate stolen memory size for gen 9 and later

450ba/arch/x86/kernel/early-quirks.c#L455-L460 Signed-off-by: Corvin Köhne --- hw/vfio/igd.c | 15 +++ 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/hw/vfio/igd.c b/hw/vfio/igd.c index 0751c43eae..a95d441f68 100644 --- a/hw/vfio/igd.c +++ b/hw/vfio/igd.c @@ -488,11 +4

[PATCH v3 0/7] vfio/igd: add passthrough support for IGDs of gen 11 and later

. I've tested the patch series on an ElkhartLake and TigerLake device. On the guest side, I've tested an EFI environment (GOP driver), a Linux guest and a Windows VM. The driver of all guests are able to use the GPU and produce an output on the connected display. Corvin Köhne (7): vfio/igd:

[PATCH v3 3/7] vfio/igd: use new BDSM register location and size for gen 11 and later

Intel changed the location and size of the BDSM register for gen 11 devices and later. We have to adjust our emulation for these devices to properly support them. Signed-off-by: Corvin Köhne --- hw/vfio/igd.c | 31 --- 1 file changed, 24 insertions(+), 7 deletions

[PATCH v3 4/7] vfio/igd: add new bar0 quirk to emulate BDSM mirror

i/passthrough.c#L650-L653 Signed-off-by: Corvin Köhne --- v2: * omit unnecessary leXX_to_cpu calls * make use of IGD_BDSM_MMIO_OFFSET define hw/vfio/igd.c| 98 hw/vfio/pci-quirks.c | 1 + hw/vfio/pci.h| 1 + 3 fil

[PATCH v3 1/7] vfio/igd: return an invalid generation for unknown devices

g a random generation value and hoping that everthing works fine, we should verify that different devices are working and add them to our list of known devices. Signed-off-by: Corvin Köhne --- hw/vfio/igd.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/vfio/igd.c b/hw/

[PATCH v3 6/7] vfio/igd: don't set stolen memory size to zero

the stolen memory size. It's true that this wastes some VM memory. In the worst case, the stolen memory can take up more than a GB. However, that's uncommon. Additionally, it's likely that a bunch of RAM is assigned to VMs making use of GPU passthrough. Signed-off-by: Corvin Köhne

[PATCH] vfio/igd: add pci id for Coffee Lake

From: Corvin Köhne I've tested and verified that Coffee Lake devices are working properly. Signed-off-by: Corvin Köhne --- hw/vfio/igd.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/vfio/igd.c b/hw/vfio/igd.c index a95d441f68..c5282827ec 100644 --- a/hw/vfio/igd.c +++ b/hw

[PATCH] hw/igd: fix calculation of graphics stolen memory

From: Corvin Köhne When copying the calculation of the stolen memory size for Intels integrated graphics device of gen 9 and later from the Linux kernel [1], we missed subtracting 0xf0 from the graphics mode select value for values above 0xf0. This leads to QEMU reporting a very large size of

Re: [PATCH 5/8] vfio/igd: add Alder/Raptor/Rocket/Ice/Jasper Lake device ids

Lake */ > case 0x4500:    /* Elkhart Lake */ > +    case 0x4E00:    /* Jasper Lake */ > return 11; > case 0x9A00:    /* Tiger Lake */ > +    case 0x4C00:    /* Rocket Lake */ > +    case 0x4600:    /* Alder Lake */ > +    case 0xA700:    /* Raptor Lake

Re: [PATCH 2/8] vfio/igd: canonicalize memory size calculations

On Sun, 2024-12-01 at 22:28 -0700, Alex Williamson wrote: > CAUTION: External Email!! > On Mon,  2 Dec 2024 00:09:32 +0800 > Tomita Moeko wrote: > > > Add helper functions igd_gtt_memory_size() and igd_stolen_size() for > > calculating GTT stolen memory and Data stolen memory size in bytes, > > a

Re: [PATCH 6/8] vfio/igd: emulate GGC register in mmio bar0

On Mon, 2024-12-02 at 00:09 +0800, Tomita Moeko wrote: > CAUTION: External Email!! > The GGC register at 0x50 of pci config space is a mirror of the same > register at 0x108040 of mmio bar0 [1]. i915 driver also reads that > register from mmio bar0 instead of config space. As GGC is programmed > a

Re: [PATCH 7/8] vfio/igd: emulate BDSM in mmio bar0 for gen 6-10 devices

On Mon, 2024-12-02 at 00:09 +0800, Tomita Moeko wrote: > CAUTION: External Email!! > A recent commit in i915 driver [1] claims the BDSM register at 0x1080c0 > of mmio bar0 has been there since gen 6. Mirror this register to the 32 > bit BDSM register at 0x5c in pci config space for gen6-10 devices

Re: [PATCH 1/8] vfio/igd: fix GTT stolen memory size calculation for gen 7

On Mon, 2024-12-02 at 00:09 +0800, Tomita Moeko wrote: > CAUTION: External Email!! > Both intel documentation [1][2] and i915 driver shows GGMS represents > GTT stolen memory size in multiple of 1MB, not 2MB starting from gen > 8. > > [1] > https://www.intel.com/content/dam/www/public/us/en/docum

Re: [PATCH 8/8] vfio/igd: add x-igd-gms option back to set DSM region size for guest

On Mon, 2024-12-02 at 00:09 +0800, Tomita Moeko wrote: > CAUTION: External Email!! > DSM region is likely to store framebuffer in Windows, a small DSM > region may cause display issues (e.g. half of the screen is black). > By default, QEMU uses host's original value, which is determined by > DVMT

Re: [PATCH 3/8] vfio/igd: remove unsupported device ids

00) { > > -    /* Old, untested, unavailable, unknown */ > > -    case 0x: > > -    case 0x2500: > > -    case 0x2700: > > -    case 0x2900: > > -    case 0x2a00: > > -    case 0x2e00: > > -    case 0x3500: > > -    case 0xa000: > > -  

Re: [PATCH v2 4/9] vfio/igd: add Gemini Lake and Comet Lake device ids

  /* Gemini Lake */ > case 0x5900:    /* Kaby Lake */ > case 0x3e00:    /* Coffee Lake */ > +    case 0x9B00:    /* Comet Lake */ > return 9; >      case 0x4500:    /* Elkhart Lake */ > return 11; Reviewed-by: Corvin Köhne signature.asc Description: This is a digitally signed message part

Re: [PATCH v2 6/9] vfio/igd: add macro for declaring mirrored registers

On Tue, 2024-12-03 at 21:35 +0800, Tomita Moeko wrote: > CAUTION: External Email!! > igd devices have multipe registers mirroring mmio address and pci > config space, more than a single BDSM register. To support this, > the read/write functions are made common and a macro is defined to > simplify

Re: [PATCH v2 3/9] vfio/igd: canonicalize memory size calculations

IRRNT- > tIucgsQHKYe8WitBfoANcxBM2L6i4Sg4fLLMkXL_LDVUSEswEqsunuGsAr4DjgOogXtNMivhsyeaj9 > xYl9AgydV4QqrKMV29P7y3uAuqQcYz1GacVJRg1 ); >      } >   > -    trace_vfio_pci_igd_bdsm_enabled(vdev- > >https://nospamproxywebp.beckhoff.com/enQsig/link?id=BAgDIUcZasZ36mwAAABM0 > 01Yig6LNmON7mS202pDuIRRNT- > tIucgsQHKYe8WitBfoANcxBM2L6i4Sg4fLLMkXL_LDVUSEswEqsunuGsAr4DjgOogXtNMivhsyeaj9 > xYl9AgydV4QqrKMV29P7y3uAuqQcYz1GacVJRg1 , ggms_mb + gms_mb); > +    trace_vfio_pci_igd_bdsm_enabled(vdev- > >https://nospamproxywebp.beckhoff.com/enQsig/link?id=BAgDIUcZasZ36mwAAABM0 > 01Yig6LNmON7mS202pDuIRRNT- > tIucgsQHKYe8WitBfoANcxBM2L6i4Sg4fLLMkXL_LDVUSEswEqsunuGsAr4DjgOogXtNMivhsyeaj9 > xYl9AgydV4QqrKMV29P7y3uAuqQcYz1GacVJRg1 , > +    (ggms_size + gms_size) / MiB); >  } Reviewed-by: Corvin Köhne signature.asc Description: This is a digitally signed message part

Re: [PATCH v2 8/9] vfio/igd: emulate BDSM in mmio bar0 for gen 6-10 devices

bdsm64, vdev, > +  "vfio-igd-bdsm-quirk", 8); > +    memory_region_add_subregion_overlap(vdev->bars[0].region.mem, > +    IGD_BDSM_MMIO_OFFSET, > +    &quirk->mem[1], 1); > +    } >   > QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); >  } Reviewed-by: Corvin Köhne signature.asc Description: This is a digitally signed message part

Re: [PATCH v2 2/9] vfio/igd: align generation with i915 kernel driver

> 6) { > +    if (gen >= 8) { > ggms = 1 << ggms; > } >   > @@ -668,7 +668,7 @@ void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, int > nr) >   > /* Determine the size of stolen memory needed for GTT */ > ggms_mb = (gmch >> (gen < 8 ? 8 : 6)) & 0x3; > -    if (gen > 6) { > +    if (gen >= 8) { > ggms_mb = 1 << ggms_mb; > } >   Reviewed-by: Corvin Köhne signature.asc Description: This is a digitally signed message part

Re: [PATCH v2 5/9] vfio/igd: add Alder/Raptor/Rocket/Ice/Jasper Lake device ids

ke */ > case 0x4500:    /* Elkhart Lake */ > +    case 0x4E00:    /* Jasper Lake */ > return 11; > case 0x9A00:    /* Tiger Lake */ > +    case 0x4C00:    /* Rocket Lake */ > +    case 0x4600:    /* Alder Lake */ > +    case 0xA700:    /* Raptor Lake */ >

Re: [PATCH v2 9/9] vfio/igd: add x-igd-gms option back to set DSM region size for guest

On Tue, 2024-12-03 at 21:35 +0800, Tomita Moeko wrote: > CAUTION: External Email!! > DSM region is likely to store framebuffer in Windows, a small DSM > region may cause display issues (e.g. half of the screen is black). > By default, QEMU uses host's original value, which is determined by > DVMT

[PATCH 4/4] vfio/igd: sync GPU generation with i915 kernel driver

From: Corvin Köhne We're currently missing some GPU IDs already supported by the i915 kernel driver. Additionally, we've treated IvyBridge as gen 6 in the past. According to i915 it's gen 7 [1]. It shouldn't cause any issues yet because we treat gen 6 and gen 7 the same w

[PATCH 0/4] vfio/igd: sync PCI IDs with i915

From: Corvin Köhne Hi, we're currently maintaining an own list of PCI IDs to match the generation of Intels integrated graphic devices. Linux maintains a list too. It's list is more recent, contains the full PCI ID of all devices and ships some macros to easily match them. This pa

[PATCH 3/4] vfio/igd: use PCI ID defines to detect IGD gen

From: Corvin Köhne We've recently imported the PCI ID list of knwon Intel GPU devices from Linux. It allows us to properly match GPUs to their generation without maintaining an own list of PCI IDs. Signed-off-by: Corvin Köhne --- hw/vfio/igd.c

[PATCH 2/4] scripts/update-linux-headers: include PCI ID header for Intel GPUs

From: Corvin Köhne We've recently imported the PCI ID header for Intel GPUs into our tree. Add it to our helper script to make it easier for us to sync this file in the future. Signed-off-by: Corvin Köhne --- scripts/update-linux-headers.sh | 6 ++ 1 file changed, 6 insertions(+)

[PATCH 1/4] include/standard-headers: add PCI IDs for Intel GPUs

From: Corvin Köhne Intels integrated graphics devices do require many quirks to pass them to a VM as passthrough device. Unfortunately, those quirks are device specific and we have to check the device IDs to apply quirks properly. In the past, we've maintained an own list of PCI IDs. Ho

Re: [PATCH 3/4] vfio/igd: use PCI ID defines to detect IGD gen

On Thu, 2025-02-06 at 14:26 -0700, Alex Williamson wrote: > On Thu,  6 Feb 2025 13:13:39 +0100 > Corvin Köhne wrote: > > > From: Corvin Köhne > > > > We've recently imported the PCI ID list of knwon Intel GPU devices from > > Linux. It allows us to p

Re: [PATCH 3/4] vfio/igd: use PCI ID defines to detect IGD gen

On Fri, 2025-02-07 at 08:47 +0100, Corvin Köhne wrote: > On Thu, 2025-02-06 at 14:26 -0700, Alex Williamson wrote: > > On Thu,  6 Feb 2025 13:13:39 +0100 > > Corvin Köhne wrote: > > > > > From: Corvin Köhne > > > > > > We've recently imp

Re: [PATCH v2] vfio: Add property documentation

On Thu, 2025-02-13 at 14:45 -0700, Alex Williamson wrote: > On Thu, 13 Feb 2025 14:50:50 +0100 > Cédric Le Goater wrote: > > +    /* > > + * IGD > > + */ > > + > > +    object_class_property_set_description(klass, /* 2.7 */ > > +  "x-igd-opregion", >

Re: [PATCH v3 00/10] vfio/igd: Decoupling quirks with legacy mode

t;   current behavior. > > * Added a new patch to solve the possible KVMGT/GVT-g fail. > > Link: > > https://lore.kernel.org/all/20250303175220.74917-1-tomitamo...@gmail.com/ > > See comment on 07/ but otherwise works for me with GVT-d and GVT-g on > my i7-7700: > > Reviewed-by: Alex Williamson > Tested-by: Alex Williamson > Reviewed-by: Corvin Köhne signature.asc Description: This is a digitally signed message part

Re: [PATCH v2 2/9] vfio/igd: Do not include GTT stolen size in etc/igd-bdsm-size

On Tue, 2025-03-04 at 01:52 +0800, Tomita Moeko wrote: > Though GTT Stolen Memory (GSM) is right below Data Stolen Memory (DSM) > in host address space, direct access to GSM is prohibited, and it is > not mapped to guest address space. Both host and guest accesses GSM > indirectly through the secon

Re: [PATCH v2 7/9] vfio/igd: Decouple common quirks from legacy mode

On Tue, 2025-03-04 at 01:52 +0800, Tomita Moeko wrote: > So far, IGD-specific quirks all require enabling legacy mode, which is > toggled by assigning IGD to 00:02.0. However, some quirks, like the BDSM > and GGC register quirks, should be applied to all supported IGD devices. > A new feature bit,

Re: [PATCH v2 7/9] vfio/igd: Decouple common quirks from legacy mode

On Tue, 2025-03-04 at 09:07 +0100, Corvin Köhne wrote: > On Tue, 2025-03-04 at 01:52 +0800, Tomita Moeko wrote: > > So far, IGD-specific quirks all require enabling legacy mode, which is > > toggled by assigning IGD to 00:02.0. However, some quirks, like the BDSM > > an

Re: [PATCH] vfio/igd: Update IGD passthrough docoumentation

  | > +    | | Data Stolen | +-+ > +    | |   (Host)    | > +        +>+-+<--Host BDSM > +  Non-    | |   "real" one in HW > +  Passthrough | |   Programmed by host FW > +  +-+ >   >  Footnotes >  = > -[1] Nothing precludes adding additional emulated or assigned graphics devices > -    as non-primary, other than the combination typically not working.  I only > -    intend to set user expectations, others are welcome to find working > -    combinations or fix whatever issues prevent this from working in the > common > -    case. > +[1] > https://www.intel.com/content/www/us/en/docs/graphics-for-linux/developer-reference/1-0/dump-video-bios.html >  [2] # echo "vfio-pci" > /sys/bus/pci/devices/:00:02.0/driver_override > +[3] > https://web.archive.org/web/20240827012422/https://bugzilla.tianocore.org/show_bug.cgi?id=935 > +    Tianocore bugzilla was down since Jan 2025 :( > +[4] https://eci.intel.com/docs/3.3/components/kvm-hypervisor.html, Patch > 0001-0004 > +[5] https://github.com/tomitamoeko/VfioIgdPkg > +[6] > https://winraid.level1techs.com/t/tool-guide-news-uefi-bios-updater-ubu/30357 Reviewed-by: Corvin Köhne signature.asc Description: This is a digitally signed message part

[PATCH 00/21] Hi,

From: Corvin Köhne Beckhoff has build a board, called CX7200, based on the Xilinx Zynq A9 platform. This commit series adds the Beckhoff CX7200 as new board variant to QEMU. The emulation is able to successfully boot an CX7200 image. The image includes some self tests executed on every boot

[PATCH 00/21] Hi,

From: Corvin Köhne Beckhoff has build a board, called CX7200, based on the Xilinx Zynq A9 platform. This commit series adds the Beckhoff CX7200 as new board variant to QEMU. The emulation is able to successfully boot an CX7200 image. The image includes some self tests executed on every boot

[PATCH 01/21] hw/timer: Make frequency configurable

From: YannickV The a9 global timer and arm mp timers rely on the PERIPHCLK as their clock source. The current implementation does not take that into account. That causes problems for applications assuming other frequencies than 1 GHz. We can now configure frequencies for the a9 global timer and

[PATCH 02/21] hw/timer: Make PERIPHCLK period configurable

From: YannickV The a9 global timer and arm mp timer rely on the PERIPHCLK as their clock source. The period of PERIPHCLK (denoted as N) must be a multiple of the core CLK period, with N being equal to or greater than two. However, the current implementation does not take the PERIPHCLK period into

[PATCH 06/21] hw/dma/zynq-devcfg: Simulate dummy PL reset

From: YannickV Setting PCFG_PROG_B should reset the PL. After a reset PCFG_INIT should indicate that the reset is finished successfully. In order to add a MMIO-Device as part of the PL in the Zynq, the reset logic must succeed. The PCFG_INIT flag is now set when the PL reset is triggered by PCFG

[PATCH 03/21] hw/dma/zynq-devcfg: Handle bitstream loading via DMA to 0xffffffff

From: YannickV A DMA transfer to destination address `0x` should trigger a bitstream load via the PCAP interface. Currently, this case is not intercepted, causing loaders to enter an infinite loop when polling the status register. This commit adds a check for `0x` as the destinat

[PATCH 05/21] hw/dma/zynq: Notify devcfg on FPGA reset via SLCR control

From: YannickV When the FPGA_RST_CTRL register in the SLCR (System Level Control Register) is written to, the devcfg (Device Configuration) should indicate the finished reset. Problems occure when Loaders trigger a reset via SLCR and poll for the done flag in devcfg. Since the flag will never be

[PATCH 07/21] hw/dma/zynq-devcfg: Indicate power-up status of PL

From: YannickV It is assumed, that the programmable logic (PL) is always powered during emulation. Therefor the PCFG_POR_B bit in the MCTRL register is set. This commit is necessary for the Beckhoff CX7200 board emulation that has a FPGA implemented in the PL. Signed-off-by: Yannick Voßen ---

[PATCH 15/21] hw/arm/beckhoff_CX7200: Adjust Flashes and Busses

From: YannickV The CX7200 has one QSPI flash connected to the QSPI bus. The defines are adjusted accordingly. The QSPI flash is a is25lp016d. There is no parallel flash. Signed-off-by: Yannick Voßen --- hw/arm/beckhoff_CX7200.c | 20 1 file changed, 4 insertions(+), 16 del

[PATCH 04/21] hw/arm/zynq-devcfg: Prevent unintended unlock during initialization

From: YannickV During the emulation startup, all registers are reset, which triggers the `r_unlock_post_write` function with a value of 0. This led to an unintended memory access disable, making the devcfg unusable. To address this, a property 'is_initialized' is introduced. It is set to false d

[PATCH 11/21] hw/misc: Add Beckhoff CCAT device

From: YannickV This adds the Beckhoff Communication Controller (CCAT). The information block, EEPROM interface and DMA controller are currently implemented. The EEPROM provides production information for Beckhoff Devices. An EEPORM binary must therefor be handed over. It should be aligned to a

[PATCH 21/21] MAINTAINERS: add myself as reviewer for Beckhoff devices

From: Corvin Köhne I don't have commit privileges, so I can't merge any changes. However, someone from Beckhoff should review changes made to their board emulations. Signed-off-by: Corvin Köhne --- MAINTAINERS | 7 +++ 1 file changed, 7 insertions(+) diff --git a/MAI

[PATCH 00/21] Hi,

From: Corvin Köhne Beckhoff has build a board, called CX7200, based on the Xilinx Zynq A9 platform. This commit series adds the Beckhoff CX7200 as new board variant to QEMU. The emulation is able to successfully boot an CX7200 image. The image includes some self tests executed on every boot

[PATCH 10/21] hw/misc/zynq_slcr: Add logic for DCI configuration

From: YannickV The registers for the digitally controlled impedance (DCI) clock are part of the system level control registers (SLCR). The DONE bit in the status register indicates a successfull DCI calibration. An description of the calibration process can be found here: https://docs.amd.com/r/e

[PATCH 13/21] hw/arm/beckhoff_CX7200: Remove second SD controller

From: YannickV The CX7200 has one SD controller connected to address 0xE0101000. The controller connected to address 0xE010 can be removed. Signed-off-by: Yannick Voßen --- hw/arm/beckhoff_CX7200.c | 48 ++-- 1 file changed, 21 insertions(+), 27 deletion

[PATCH 08/21] hw/dma/zynq-devcfg: Fix register memory

From: YannickV Registers are always 32 bit aligned. R_MAX is not the maximum register address, it is the maximum register number. The memory size can be determined by 4 * R_MAX. Currently every register with an offset bigger than 0x40 will be ignored, because the memory size is set wrong. This e

[PATCH 17/21] hw/arm/beckhoff_CX7200: Remove unimplemented devices

From: YannickV Some unimplemented devices do not exist for the CX7200. All unimplemented devices have been removed for better overview and the fact that they are not necessary for a CX7200 emulation. Signed-off-by: Yannick Voßen --- hw/arm/beckhoff_CX7200.c | 69 ---

[PATCH 18/21] hw/arm/beckhoff_CX7200: Set CPU frequency and PERIPHCLK period

From: YannickV The CPU frequency for the CX7200 is set to 720 MHz, with the peripheral clock running at half of the CPU frequency. That is why the PERIPHCLK_PERIOD is set to two. These values are forwarded to the A9 global timer, watchdog timer and MP Timer. Signed-off-by: Yannick Voßen --- hw

[PATCH 19/21] hw/arm/beckhoff_CX7200: Add CCAT to CX7200

From: YannickV The Beckhoff CX7200 is based on the Xilinx Zynq-7000 SoC. It integrates the Beckhoff Communication Controller (CCAT), which is implemented as an FPGA within the Zynq's programmable logic (PL). This commit adds the CCAT as an MMIO device to the CX7200 machine in QEMU, enabling its

[PATCH 12/21] hw/arm: Add new machine based on xilinx-zynq-a9 for Beckhoff CX7200

From: YannickV This commit introduces a new machine, derived from xilinx-zynq-a9, as a starting point for the Beckhoff CX7200 integration. Functions and structs are renamed to delimit the CX7200 board emulation from the existing Zynq emulation. At this stage, the new machine is a direct copy of

[PATCH 20/21] hw/arm/beckhoff_CX7200: Add dummy DDR CTRL to CX7200

From: YannickV The CX7200 polls for statusregisters in the DDR Controller. To avaid endless polling loops, a dummy DDR Controller is added. Signed-off-by: Yannick Voßen --- hw/arm/beckhoff_CX7200.c | 13 + 1 file changed, 13 insertions(+) diff --git a/hw/arm/beckhoff_CX7200.c b/hw

[PATCH 09/21] hw/misc: Add dummy ZYNQ DDR controller

From: YannickV A dummy DDR controller for ZYNQ has been added. While all registers are present, not all are functional. Read and write access is validated, and the user mode can be set. This provides a basic DDR controller initialization, preventing system hangs due to endless polling or similar