Hello,
I would greatly appreciate the review comments/suggestions on PATCH V1.
Thank You and Regards,
Chalapathi
On 07-02-2024 21:38, Chalapathi V wrote:
Hello,
In this series of patchset, SPI controller and responder models
for Power10 processor are modelled.
Serial peripheral interface
On 01-03-2024 22:06, Cédric Le Goater wrote:
Chalapathi,
On 3/1/24 17:17, Chalapathi V wrote:
Hello,
I would greatly appreciate the review comments/suggestions on PATCH V1.
Thank You and Regards,
I didn't forget but I lacked the time in this release cycle. Sorry
about that.
I hav
is modelled
which contains all SPI configuration and status registers as well as the hold
registers for data to be sent or having been received.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_spi_controller.h | 43
include/hw/ppc/pnv_xscom.h | 3 +
hw/ppc/pnv_spi_controller.c
This commit creates SPI controller to p10 chip and create the keystore seeprom
device on spi_bus2 of PIB_SPIC[2].
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_chip.h | 4
hw/ppc/pnv.c | 32
2 files changed, 36 insertions(+)
diff --git a
OM registers.
PATCH3: SPI controller model: implement sequencer FSM and shift engine.
PATCH4: create SPI SEEPROM model.
PATCH5: Connect SPI controllers to p10 chip and create keystore seeprom
device on spi_bus2 of PIB_SPIC[2].
Thank You,
Chalapathi
Chalapathi V (5):
hw/ppc: SPI resp
that single responder is connected to
bus, hence chip_select is not modelled.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_spi_responder.h | 109 +++
hw/ppc/pnv_spi_responder.c | 166 +
hw/ppc/meson.build | 1 +
3 files
24288 bytes of 8 bits each (512Kbyte) and
is optimized for use in consumer and industrial applications where reliable
and dependable nonvolatile memory storage is essential.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_spi_seeprom.h | 70 +++
hw/ppc/pnv_spi_seeprom.c
data transmit and data receive control of the shift engine.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_spi_controller.h | 58 ++
hw/ppc/pnv_spi_controller.c | 1274 ++-
2 files changed, 1331 insertions(+), 1 deletion(-)
diff --git a/include/hw/ppc
data transmit and data receive control of the shift engine.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_spi_controller.h | 72 ++
hw/ppc/pnv_spi_controller.c | 1311 ++-
2 files changed, 1382 insertions(+), 1 deletion(-)
diff --git a/include/hw/ppc
-- Empty commit to align the patch numbers between PATCH v1 and PATCH v2.
SPI responder model is removed as pnv spi controller and seeprom is
implemented using QEMU SSI framework.
Signed-off-by: Chalapathi V
_SPIC[2].
PATCH6: Write a qtest pnv-spi-seeprom-test to check the SPI transactions
between spi controller and seeprom device.
Test covered:
Ran make check.
Thank You,
Chalapathi
Chalapathi V (6):
hw/ppc: remove SPI responder model
hw/ppc: SPI controller model - registers implementation
is modelled
which contains all SPI configuration and status registers as well as the hold
registers for data to be sent or having been received.
An existing QEMU SSI framework is used and SSI_BUS is created.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_spi_controller.h | 55
24288 bytes of 8 bits each (512Kbyte) and
is optimized for use in consumer and industrial applications where reliable
and dependable nonvolatile memory storage is essential.
This seeprom device is created from a parent "ssi-peripheral".
Signed-off-by: Chalapathi V
---
include/hw/misc/se
In this commit Write a qtest pnv-spi-seeprom-test to check the
SPI transactions between spi controller and seeprom device.
Signed-off-by: Chalapathi V
---
tests/qtest/pnv-spi-seeprom-test.c | 126 +
tests/qtest/meson.build| 1 +
2 files changed, 127
_bus"
"/machine/chip[0]/pib_spic[2]/bus/pnv-spi-bus.2"
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_chip.h | 3 +++
hw/ppc/pnv.c | 36 +++-
2 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/include/hw/ppc/pnv_chip.h b/i
On 15-04-2024 20:44, Cédric Le Goater wrote:
Hello Chalapathi
The subject could be rephrased to : "ppc/pnv: Add SPI controller model".
On 4/9/24 19:56, Chalapathi V wrote:
SPI controller device model supports a connection to a single SPI
responder.
This provide access to SPI see
On 16-04-2024 15:09, Cédric Le Goater wrote:
Hello,
Please rephrase the subject to something like:
"ppc/pnv: Extend SPI model ..."
Using a verb is preferable.
Sure. Will update. Thank You.
On 4/9/24 19:56, Chalapathi V wrote:
In this commit SPI shift engine and sequence
Hello Cedric,
Thank You for reviewing v2 patches.
Regards,
Chalapathi
On 22-04-2024 20:33, Cédric Le Goater wrote:
On 4/9/24 19:56, Chalapathi V wrote:
In this commit
Creates SPI controller on p10 chip.
Create the keystore seeprom of type "seeprom-25csm04"
Connect the cs of
)
/peripheral-anon (container)
/device[0] (25csm04)
/WP#[0] (irq)
/ssi-gpio-cs[0] (irq)
(qemu) qom-get /machine/peripheral-anon /device[76] "parent_bus"
"/machine/chip[0]/pib_spic[2]/pnv-spi-bus.2"
Signed-off-by: Chalapathi V
Reviewed-by: Glenn Miles
Reviewed-
In this commit target specific dependency from include/hw/ppc/pnv_xscom.h
has been removed so that pnv_xscom.h can be included outside hw/ppc.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_xscom.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/ppc
is modelled
which contains all SPI configuration and status registers as well as the hold
registers for data to be sent or having been received.
An existing QEMU SSI framework is used and SSI_BUS is created.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_xscom.h| 3 +
include/hw/ssi
ATCH5: Connect SPI controllers to p10 chip and connect cs lines.
PATCH6: Write a qtest pnv-spi-seeprom-test to check the SPI transactions
between spi controller and seeprom device.
Test covered:
make check
make check-avocado
Thank You,
Chalapathi
Chalapathi V (6):
ppc/pnv: Remove ppc t
In this commit Write a qtest pnv-spi-seeprom-test to check the
SPI transactions between spi controller and seeprom device.
Signed-off-by: Chalapathi V
Acked-by: Cédric Le Goater
---
tests/qtest/pnv-spi-seeprom-test.c | 110 +
tests/qtest/meson.build| 1
data transmit and data receive control of the shift engine.
Signed-off-by: Chalapathi V
---
include/hw/ssi/pnv_spi.h | 27 +
include/hw/ssi/pnv_spi_regs.h | 68 ++-
hw/ssi/pnv_spi.c | 1045 +
hw/ssi/trace-events | 15 +
4 files
where reliable
and dependable nonvolatile memory storage is essential.
Signed-off-by: Chalapathi V
Reviewed-by: Glenn Miles
Reviewed-by: Cédric Le Goater
---
hw/block/m25p80.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index 8dec134832..824a6c5c60 1
In this commit the following coverity scan defect has been fixed.
CID 1558827:(OVERRUN)
Overrunning array "s->seq_op" of 8 bytes at byte offset 16
using index "get_seq_index(s) + 1" (which evaluates to 16).
Signed-off-by: Chalapathi V
---
hw/ssi/pnv_spi.c | 6 ++
t;s->seq_op" of 8 bytes at byte offset 16 using index
"get_seq_index(s) + 1" (which evaluates to 16).
Tested:
passed make check and make check-avocado
Chalapathi V (2):
Fixes: Coverity CID 1558827
Fixes: Coverity CID 1558831
hw/ssi/pnv_spi.c | 7 ---
1 file chan
In this commit the following coverity scan defect has been fixed
CID 1558831: Resource leaks (RESOURCE_LEAK)
Variable "rsp_payload" going out of scope leaks the storage it
points to.
Signed-off-by: Chalapathi V
---
hw/ssi/pnv_spi.c | 1 +
1 file changed, 1 insertion(+)
diff
where reliable
and dependable nonvolatile memory storage is essential.
Signed-off-by: Chalapathi V
---
hw/block/m25p80.c | 3 +++
hw/ppc/Kconfig| 1 +
2 files changed, 4 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index 8dec134832..824a6c5c60 100644
--- a/hw/block/m25p80.c
+++
is modelled
which contains all SPI configuration and status registers as well as the hold
registers for data to be sent or having been received.
An existing QEMU SSI framework is used and SSI_BUS is created.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_xscom.h| 3 +
include/hw/ssi
seeprom-test to check the SPI transactions
between spi controller and seeprom device.
Test covered:
Ran make check.
Thank You,
Chalapathi
Chalapathi V (5):
ppc/pnv: Add SPI controller model
ppc/pnv: Extend SPI model
hw/block: Add Microchip's 25CSM04 to m25p80
hw/ppc: SPI cont
)
/machine (powernv10-machine)
/peripheral-anon (container)
/device[0] (25csm04)
/WP#[0] (irq)
/ssi-gpio-cs[0] (irq)
(qemu) qom-get /machine/peripheral-anon /device[76] "parent_bus"
"/machine/chip[0]/pib_spic[2]/pnv-spi-bus.2"
Signed-off-by: Chalapathi V
In this commit Write a qtest pnv-spi-seeprom-test to check the
SPI transactions between spi controller and seeprom device.
Signed-off-by: Chalapathi V
---
tests/qtest/pnv-spi-seeprom-test.c | 129 +
tests/qtest/meson.build| 1 +
2 files changed, 130
data transmit and data receive control of the shift engine.
Signed-off-by: Chalapathi V
---
include/hw/ssi/pnv_spi.h| 28 +
hw/ppc/pnv_spi_controller.c | 1074 +++
hw/ppc/trace-events | 15 +
3 files changed, 1117 insertions(+)
diff --git a/include
Hello Glen,
Thank You for reviewing the patch.
Regards,
Chalapathi
On 17-05-2024 21:57, Miles Glenn wrote:
Hi Chalapathi,
Looks good. Just some suggestions on readability and some
simplifications (see below).
Thanks,
Glenn
On Thu, 2024-05-16 at 11:33 -0500, Chalapathi V wrote:
SPI
tch 1/5 will make it big. Hence made a
logical partition.
On Thu, 2024-05-16 at 11:33 -0500, Chalapathi V wrote:
In this commit SPI shift engine and sequencer logic is implemented.
Shift engine performs serialization and de-serialization according to
the
control by the sequencer and according t
On 20-05-2024 11:19, Cédric Le Goater wrote:
On 5/15/24 19:41, Chalapathi V wrote:
SPI controller device model supports a connection to a single SPI
responder.
This provide access to SPI seeproms, TPM, flash device and an ADC
controller.
All SPI function control is mapped into the SPI
Hello Cedric,
Thank You for reviewing the patch v3
Regards,
Chalapathi
On 20-05-2024 11:19, Cédric Le Goater wrote:
On 5/15/24 19:41, Chalapathi V wrote:
SPI controller device model supports a connection to a single SPI
responder.
This provide access to SPI seeproms, TPM, flash device and
On 20-05-2024 11:43, Cédric Le Goater wrote:
On 5/15/24 19:41, Chalapathi V wrote:
In this commit Write a qtest pnv-spi-seeprom-test to check the
SPI transactions between spi controller and seeprom device.
Signed-off-by: Chalapathi V
---
tests/qtest/pnv-spi-seeprom-test.c | 129
On 20-05-2024 11:19, Cédric Le Goater wrote:
On 5/15/24 19:41, Chalapathi V wrote:
SPI controller device model supports a connection to a single SPI
responder.
This provide access to SPI seeproms, TPM, flash device and an ADC
controller.
All SPI function control is mapped into the SPI
On 14-06-2024 16:57, Cédric Le Goater wrote:
On 6/13/24 3:45 PM, Chalapathi V wrote:
On 20-05-2024 11:19, Cédric Le Goater wrote:
On 5/15/24 19:41, Chalapathi V wrote:
SPI controller device model supports a connection to a single SPI
responder.
This provide access to SPI seeproms, TPM
data transmit and data receive control of the shift engine.
Signed-off-by: Chalapathi V
---
include/hw/ssi/pnv_spi.h | 27 +
hw/ssi/pnv_spi.c | 1039 ++
hw/ssi/trace-events | 15 +
3 files changed, 1081 insertions(+)
diff --git a/include/hw/ssi
where reliable
and dependable nonvolatile memory storage is essential.
Signed-off-by: Chalapathi V
Reviewed-by: Glenn Miles
Reviewed-by: Cédric Le Goater
---
hw/block/m25p80.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index 8dec134832..824a6c5c60 1
t SPI controllers to p10 chip and connect cs lines.
PATCH5: Write a qtest pnv-spi-seeprom-test to check the SPI transactions
between spi controller and seeprom device.
Test covered:
make check
make check-avocado
Thank You,
Chalapathi
Chalapathi V (5):
ppc/pnv: Add SPI model
ppc/pnv: Extend SPI
In this commit Write a qtest pnv-spi-seeprom-test to check the
SPI transactions between spi controller and seeprom device.
Signed-off-by: Chalapathi V
---
tests/qtest/pnv-spi-seeprom-test.c | 110 +
tests/qtest/meson.build| 1 +
2 files changed, 111
is modelled
which contains all SPI configuration and status registers as well as the hold
registers for data to be sent or having been received.
An existing QEMU SSI framework is used and SSI_BUS is created.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_xscom.h| 5 +-
include/hw/ssi
-machine)
/peripheral-anon (container)
/device[0] (25csm04)
/WP#[0] (irq)
/ssi-gpio-cs[0] (irq)
(qemu) qom-get /machine/peripheral-anon /device[76] "parent_bus"
"/machine/chip[0]/pib_spic[2]/pnv-spi-bus.2"
Signed-off-by: Chalapathi V
Reviewed-by: Glenn Miles
Re
Hello Cedric,
Thank You for reviewing this patch series.
Regards,
Chalapathi
On 18-06-2024 21:18, Cédric Le Goater wrote:
Hello Chalapathi,
On 6/17/24 6:54 PM, Chalapathi V wrote:
SPI controller device model supports a connection to a single SPI
responder.
This provide access to SPI
n
Hello Glenn,
Thank You for the review and suggestions. I will address them and update
in next revision ASAP.
Thank You,
Chalapathi
On Mon, 2024-06-17 at 11:54 -0500, Chalapathi V wrote:
In this commit SPI shift engine and sequencer logic is implemented.
Shift engine performs seria
review comments from initial v1
patchset and send the v2 patchset ASAP.
Thank You,
Chalapathi
Chalapathi V (1):
hw/ssi/pnv_spi: Fixes Coverity CID 1558831
Philippe Mathieu-Daudé (3):
MAINTAINERS: Cover PowerPC SPI model in PowerNV section
hw/ssi/pnv_spi: Match _xfer_buffer_free(
On 13-09-2024 19:07, Cédric Le Goater wrote:
Hello,
On 9/13/24 15:24, Chalapathi V wrote:
On 12-09-2024 22:25, Cédric Le Goater wrote:
Chalapthi,
On 8/7/24 22:28, Philippe Mathieu-Daudé wrote:
v2:
- Cover PowerNV SSI in MAINTAINERS
- Use GLib API in pnv_spi_xfer_buffer_free()
- Simplify
-Create nest1 chiplet model and add nest1 chiplet control scoms.
-Implementation of chiplet control scoms are put in pnv_pervasive.c
as control scoms are common for all chiplets.
Signed-off-by: Chalapathi V
---
hw/ppc/meson.build| 2 +
hw/ppc/pnv.c | 11
This part of the patchset creates a common pervasive chiplet model where it
houses the common units of a chiplets.
The chiplet control unit is common across chiplets and this commit implements
the chiplet control registers.
Signed-off-by: Chalapathi V
---
hw/ppc/meson.build | 1
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V
---
hw/ppc/pnv.c | 11 +++
include/hw/ppc/pnv_chip.h | 2 ++
2 files changed, 13 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index eb54f93986..0e1c944753 100644
The nest1 chiplet handle the high speed i/o traffic over PCIe and others.
The nest1 chiplet consists of PowerBus Fabric controller,
nest Memory Management Unit, chiplet control unit and more.
This commit implements nest1 chiplet control registers.
Signed-off-by: Chalapathi V
---
hw/ppc
individually.
In this series, we create a nest1 chiplet model and implements the chiplet
control scom registers on nest1 chiplet. The chiplet control registers does
the initialization and configuration of a chiplet.
Thank You,
Chalapathi
Chalapathi V (3):
hw/ppc: Add pnv pervasive common
This part of the patchset creates a common pervasive chiplet model where it
houses the common units of a chiplets.
The chiplet control unit is common across chiplets and this commit implements
the pervasive chiplet model with chiplet control registers.
Signed-off-by: Chalapathi V
---
include
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_chip.h | 2 ++
hw/ppc/pnv.c | 14 ++
2 files changed, 16 insertions(+)
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index
.
Thank You,
Chalapathi
Chalapathi V (3):
hw/ppc: Add pnv pervasive common chiplet units
hw/ppc: Add nest1 chiplet model
hw/ppc: Nest1 chiplet wiring
include/hw/ppc/pnv_chip.h | 2 +
include/hw/ppc/pnv_nest_chiplet.h | 36 +
include/hw/ppc/pnv_pervasive.h| 37
chiplet control registers are implemented.
This commit also implement the read/write method for the powerbus scom
registers
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_nest_chiplet.h | 36 ++
include/hw/ppc/pnv_xscom.h| 6 +
hw/ppc/pnv_nest1_chiplet.c| 197
On 24-11-2023 16:42, Nicholas Piggin wrote:
On Fri Nov 24, 2023 at 8:15 PM AEST, Chalapathi V wrote:
This part of the patchset creates a common pervasive chiplet model where it
houses the common units of a chiplets.
The chiplet control unit is common across chiplets and this commit
On Fri Nov 24, 2023 at 8:15 PM AEST, Chalapathi V wrote:
The nest1 chiplet handle the high speed i/o traffic over PCIe and others.
The nest1 chiplet consists of PowerBus Fabric controller,
nest Memory Management Unit, chiplet control unit and more.
This commit creates a nest1 chiplet model and in
chiplet control scoms for N1 chiplet.
PATCH3: Connect N1 chiplet model to p10 chip.
Test covered:
These changes are tested on a single socket and 2 socket P10 machine.
Thank You,
Chalapathi
Chalapathi V (3):
hw/ppc: Add pnv nest pervasive common chiplet model
hw/ppc: Add N1 chiplet model
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_chip.h | 2 ++
hw/ppc/pnv.c | 15 +++
2 files changed, 17 insertions(+)
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index
ters.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_nest_pervasive.h | 36 +
include/hw/ppc/pnv_xscom.h | 3 +
hw/ppc/pnv_nest_pervasive.c | 219
hw/ppc/meson.build | 1 +
4 files changed, 259 insertions(+)
create mode 1
control registers are implemented.
This commit also implement the read/write method for the powerbus scom
registers
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_n1_chiplet.h | 35 +++
include/hw/ppc/pnv_xscom.h | 6 ++
hw/ppc/pnv_n1_chiplet.c | 171
On 28-11-2023 12:18, Cédric Le Goater wrote:
On 11/27/23 18:13, Chalapathi V wrote:
The N1 chiplet handle the high speed i/o traffic over PCIe and others.
The N1 chiplet consists of PowerBus Fabric controller,
nest Memory Management Unit, chiplet control unit and more.
This commit creates a
check-avocado and found no obvious issues.
Thank You,
Chalapathi
Chalapathi V (3):
hw/ppc: Add pnv nest pervasive common chiplet model
hw/ppc: Add N1 chiplet model
hw/ppc: N1 chiplet wiring
include/hw/ppc/pnv_chip.h | 2 +
include/hw/ppc/pnv_n1_chiplet.h | 33 +++
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_chip.h | 2 ++
hw/ppc/pnv.c | 15 +++
2 files changed, 17 insertions(+)
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index
control registers are implemented.
This commit also implement the read/write method for the powerbus scom
registers
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_n1_chiplet.h | 33 ++
include/hw/ppc/pnv_xscom.h | 6 ++
hw/ppc/pnv_n1_chiplet.c | 173
ters.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_nest_pervasive.h | 32 +
include/hw/ppc/pnv_xscom.h | 3 +
hw/ppc/pnv_nest_pervasive.c | 208
hw/ppc/meson.build | 1 +
4 files changed, 244 insertions(+)
create mode 1
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_chip.h | 2 ++
hw/ppc/pnv.c | 15 +++
2 files changed, 17 insertions(+)
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index
control registers are implemented.
This commit also implement the read/write method for the powerbus scom
registers
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_n1_chiplet.h | 32 ++
include/hw/ppc/pnv_xscom.h | 6 ++
hw/ppc/pnv_n1_chiplet.c | 173
ters.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_nest_pervasive.h | 32 +
include/hw/ppc/pnv_xscom.h | 3 +
hw/ppc/pnv_nest_pervasive.c | 208
hw/ppc/meson.build | 1 +
4 files changed, 244 insertions(+)
create mode 1
covered:
Ran make check && make check-avocado and found no obvious issues.
Thank You,
Chalapathi
Chalapathi V (3):
hw/ppc: Add pnv nest pervasive common chiplet model
hw/ppc: Add N1 chiplet model
hw/ppc: N1 chiplet wiring
include/hw/ppc/pnv_chip.h | 2 +
includ
ters.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_nest_pervasive.h | 32 +
include/hw/ppc/pnv_xscom.h | 3 +
hw/ppc/pnv_nest_pervasive.c | 208
hw/ppc/meson.build | 1 +
4 files changed, 244 insertions(+)
create mode 1
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_chip.h | 2 ++
hw/ppc/pnv.c | 15 +++
2 files changed, 17 insertions(+)
diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index
control registers are implemented.
This commit also implement the read/write method for the powerbus scom
registers
Signed-off-by: Chalapathi V
---
include/hw/ppc/pnv_n1_chiplet.h | 32 ++
include/hw/ppc/pnv_xscom.h | 6 ++
hw/ppc/pnv_n1_chiplet.c | 173
From: Chalapathi V
Hello,
For modularity reasons the P10 processor chip is split into multiple
chiplets individually controlled and managed by the pervasive logic.
The boundaries of these chiplets are defined based on physical design
parameters like clock grids, the nature of the functional
From: Chalapathi V
The nest1 chiplet handle the high speed i/o traffic over PCIe and others.
The nest1 chiplet consists of PowerBus Fabric controller,
nest Memory Management Unit, chiplet control unit and more.
This commit creates a nest1 chiplet model and initialize and realize the
pervasive
From: Chalapathi V
This part of the patchset creates a common pervasive chiplet model where it
houses the common units of a chiplets.
The chiplet control unit is common across chiplets and this commit implements
the pervasive chiplet model with chiplet control registers.
Signed-off-by
From: Chalapathi V
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V
---
hw/ppc/pnv.c | 14 ++
include/hw/ppc/pnv_chip.h | 2 ++
2 files changed, 16 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V
---
hw/ppc/pnv.c | 11 +++
include/hw/ppc/pnv_chip.h | 2 ++
2 files changed, 13 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index eb54f93986..a5abaf5608 100644
This part of the patchset creates a common pervasive chiplet model where it
houses the common units of a chiplets.
The chiplet control unit is common across chiplets and this commit implements
the pervasive chiplet model with chiplet control registers.
Signed-off-by: Chalapathi V
---
hw/ppc
model for pervasive chiplet and initialize and realize in nest1 chiplet model.
/nest1_chiplet (pnv-nest1-chiplet)
/perv_chiplet (pnv-pervasive-chiplet)
/xscom-chiplet-control-regs[0] (memory-region)
Chalapathi V (3):
hw/ppc: Add pnv pervasive common chiplet units
hw/ppc: Add
chiplet control registers are implemented.
Signed-off-by: Chalapathi V
---
hw/ppc/meson.build| 1 +
hw/ppc/pnv_nest1_chiplet.c| 104 ++
include/hw/ppc/pnv_nest_chiplet.h | 39 +++
3 files changed, 144 insertions(+)
create mode 100644
On 29-07-2024 17:38, Cédric Le Goater wrote:
On 7/26/24 01:53, Nicholas Piggin wrote:
+static void transfer(PnvSpi *s, PnvXferBuffer *payload)
+{
+ uint32_t tx;
+ uint32_t rx;
+ PnvXferBuffer *rsp_payload = NULL;
+
+ rsp_payload = pnv_spi_xfer_buffer_new();
+ for (int offset = 0
data transmit and data receive control of the shift engine.
Signed-off-by: Chalapathi V
Reviewed-by: Caleb Schlossin
Reviewed-by: Glenn Miles
---
include/hw/ssi/pnv_spi.h | 27 +
include/hw/ssi/pnv_spi_regs.h | 68 ++-
hw/ssi/pnv_spi.c | 1047
.
Test covered:
make check
make check-avocado
Thank You,
Chalapathi
Chalapathi V (6):
ppc/pnv: Remove ppc target dependency from pnv_xscom.h
hw/ssi: Add SPI model
hw/ssi: Extend SPI model
hw/block: Add Microchip's 25CSM04 to m25p80
hw/ppc: SPI controller wiring to P10 chip
tests/qtest:
In this commit target specific dependency from include/hw/ppc/pnv_xscom.h
has been removed so that pnv_xscom.h can be included outside hw/ppc.
Signed-off-by: Chalapathi V
Reviewed-by: Cédric Le Goater
Reviewed-by: Caleb Schlossin
---
include/hw/ppc/pnv_xscom.h | 2 +-
1 file changed, 1
In this commit Write a qtest pnv-spi-seeprom-test to check the
SPI transactions between spi controller and seeprom device.
Signed-off-by: Chalapathi V
Acked-by: Cédric Le Goater
Reviewed-by: Caleb Schlossin
---
tests/qtest/pnv-spi-seeprom-test.c | 110 +
tests
where reliable
and dependable nonvolatile memory storage is essential.
Signed-off-by: Chalapathi V
Reviewed-by: Glenn Miles
Reviewed-by: Cédric Le Goater
---
hw/block/m25p80.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index 8dec134832..824a6c5c60 1
)
/peripheral-anon (container)
/device[0] (25csm04)
/WP#[0] (irq)
/ssi-gpio-cs[0] (irq)
(qemu) qom-get /machine/peripheral-anon /device[76] "parent_bus"
"/machine/chip[0]/pib_spic[2]/pnv-spi-bus.2"
Signed-off-by: Chalapathi V
Reviewed-by: Glenn Miles
Reviewed-
is modelled
which contains all SPI configuration and status registers as well as the hold
registers for data to be sent or having been received.
An existing QEMU SSI framework is used and SSI_BUS is created.
Signed-off-by: Chalapathi V
Reviewed-by: Caleb Schlossin
Reviewed-by: Cédric Le Goater
On 08-10-2024 13:29, Nicholas Piggin wrote:
On Thu Sep 19, 2024 at 2:50 AM AEST, Chalapathi V wrote:
In PnvXferBuffer dynamically allocating and freeing is a
process overhead. Hence used an existing Fifo8 buffer with
capacity of 16 bytes.
Signed-off-by: Chalapathi V
---
include/hw/ssi
On 08-10-2024 13:14, Nicholas Piggin wrote:
On Thu Sep 19, 2024 at 2:50 AM AEST, Chalapathi V wrote:
From: "Philippe Mathieu-Daudé"
It is unfair to let the PowerNV SPI model to the SSI
maintainers. Also include the PowerNV ones.
Fixes: 29318db133 ("hw/ssi: Add SPI model&
On 08-10-2024 13:43, Nicholas Piggin wrote:
On Thu Sep 19, 2024 at 2:50 AM AEST, Chalapathi V wrote:
Use a local variable seq_index instead of repeatedly caling
get_seq_index() method.
Signed-off-by: Chalapathi V
---
hw/ssi/pnv_spi.c | 61
On 08-10-2024 18:14, Cédric Le Goater wrote:
On 10/8/24 09:43, Nicholas Piggin wrote:
On Thu Sep 19, 2024 at 2:50 AM AEST, Chalapathi V wrote:
Hello,
v3:
1. Update the PowerNV maintainer section to include hw/ssi/pnv_spi*
2. Use of PnvXferBuffer results in a additonal process overhead due
Use a local variable seq_index instead of repeatedly calling
get_seq_index() method and open-code next_sequencer_fsm().
Signed-off-by: Chalapathi V
---
hw/ssi/pnv_spi.c | 93 +---
1 file changed, 48 insertions(+), 45 deletions(-)
diff --git a/hw/ssi
er.
2. Use a local variable seq_index and use it with in while loop instead
of repeatedly calling get_seq_index() and make sure s->seq_op doesn't
overrun when seq_index is incremented.
Tested:
passed make check and make check-avocado
Chalapathi V (2):
hw/ssi/pnv_spi: Replace PnvXferBuff
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