[PATCH ats_vtd v5 10/22] pci: add IOMMU operations to get address spaces and memory regions with PASID

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/pci/pci.c | 19 +++ include/hw/pci/pci.h | 34 ++ 2 files changed, 53 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 51feede3cf..3fe47d4002 100644 --- a

[PATCH ats_vtd v5 11/22] memory: store user data pointer in the IOMMU notifiers

From: Clément Mathieu--Drif This will help developers of svm devices to track a state Signed-off-by: Clément Mathieu--Drif --- include/exec/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/memory.h b/include/exec/memory.h index 0067b2266a..359bca2ae2 100644 --- a/inclu

[PATCH ats_vtd v5 21/22] intel_iommu: set the address mask even when a translation fails

From: Clément Mathieu--Drif Implements the behavior defined in section 10.2.3.5 of PCIe spec rev 5. This is needed by devices that support ATS. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/i386/

[PATCH ats_vtd v5 04/22] intel_iommu: do not consider wait_desc as an invalid descriptor

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif Reviewed-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 772b1cea88..7b0c22fc07 100644 --- a/hw/i386/intel_iommu.c +++ b/hw

[PATCH ats_vtd v5 03/22] intel_iommu: return page walk level even when the translation fails

From: Clément Mathieu--Drif We use this information in vtd_do_iommu_translate to populate the IOMMUTLBEntry and indicate the correct page mask. This prevents ATS devices from sending many useless translation requests when a megapage or gigapage iova is not mapped to a physical address. Signed-of

[PATCH ats_vtd v5 12/22] pci: add a pci-level initialization function for iommu notifiers

From: Clément Mathieu--Drif We add a convenient way to initialize an device-iotlb notifier. This is meant to be used by ATS-capable devices. pci_device_iommu_memory_region_pasid is introduces in this commit and will be used in several other SVM-related functions exposed in the PCI API. Signed-o

[PATCH ats_vtd v5 05/22] memory: add permissions in IOMMUAccessFlags

From: Clément Mathieu--Drif This will be necessary for devices implementing ATS. We also define a new macro IOMMU_ACCESS_FLAG_FULL in addition to IOMMU_ACCESS_FLAG to support more access flags. IOMMU_ACCESS_FLAG is kept for convenience and backward compatibility. Here are the flags added (define

[PATCH ats_vtd v5 22/22] intel_iommu: add support for ATS

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 75 -- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 73 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index

[PATCH ats_vtd v5 06/22] pcie: add helper to declare PASID capability for a pcie device

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/pci/pcie.c | 24 +++ include/hw/pci/pcie.h | 6 +- include/hw/pci/pcie_regs.h| 3 +++ include/standard-headers/linux/pci_regs.h | 1

[PATCH ats_vtd v5 07/22] pcie: helper functions to check if PASID and ATS are enabled

From: Clément Mathieu--Drif ats_enabled and pasid_enabled check whether the capabilities are present or not. If so, we read the configuration space to get the status of the feature (enabled or not). Signed-off-by: Clément Mathieu--Drif --- hw/pci/pcie.c | 18 ++ include

[PATCH ats_vtd v5 16/22] intel_iommu: fill the PASID field when creating an instance of IOMMUTLBEntry

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 9 + 1 file changed, 9 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index d607562de2..0f3bd5978e 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2

[PATCH ats_vtd v5 15/22] memory: Allow to store the PASID in IOMMUTLBEntry

From: Clément Mathieu--Drif This will be useful for devices that support ATS Signed-off-by: Clément Mathieu--Drif --- include/exec/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/memory.h b/include/exec/memory.h index 359bca2ae2..56ef48780f 100644 --- a/include/exec/m

[PATCH ats_vtd v5 18/22] atc: add unit tests

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- tests/unit/meson.build | 1 + tests/unit/test-atc.c | 527 + 2 files changed, 528 insertions(+) create mode 100644 tests/unit/test-atc.c diff --git a/tests/unit/meson.build b/tests/

[PATCH ats_vtd v5 20/22] pci: add a pci-level API for ATS

From: Clément Mathieu--Drif Devices implementing ATS can send translation requests using pci_ats_request_translation_pasid. The invalidation events are sent back to the device using the iommu notifier managed with pci_register_iommu_tlb_event_notifier and pci_unregister_iommu_tlb_event_notifier

[PATCH ats_vtd v5 08/22] intel_iommu: declare supported PASID size

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 2 +- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 7b0c22fc07..fb6c7d1e33 100644 --- a

[PATCH ats_vtd v5 13/22] intel_iommu: implement the get_address_space_pasid iommu operation

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 13 ++--- include/hw/i386/intel_iommu.h | 2 +- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index fb6c7d1e33..6a68df015

[PATCH ats_vtd v5 14/22] intel_iommu: implement the get_memory_region_pasid iommu operation

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 6a68df0154..d607562de2 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu

[PATCH ats_vtd v5 00/22] ATS support for VT-d

From: Clément Mathieu--Drif This series belongs to a list of series that add SVM support for VT-d. As a starting point, we use the series called 'intel_iommu: Enable stage-1 translation' (rfc2) by Zhenzhong Duan and Yi Liu. Here we focus on the implementation of ATS support in the IOMMU and on

[PATCH ats_vtd v5 09/22] pci: cache the bus mastering status in the device

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/pci/pci.c| 24 ++-- include/hw/pci/pci_device.h | 1 + 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index c8a8aab306..51feede3cf 100644 --

[PATCH ats_vtd v5 17/22] atc: generic ATC that can be used by PCIe devices that support SVM

From: Clément Mathieu--Drif As the SVM-capable devices will need to cache translations, we provide an first implementation. This cache uses a two-level design based on hash tables. The first level is indexed by a PASID and the second by a virtual addresse. Signed-off-by: Clément Mathieu--Drif

[PATCH ats_vtd v5 02/22] intel_iommu: make types match

From: Clément Mathieu--Drif The 'level' field in vtd_iotlb_key is an unsigned integer. We don't need to store level as an int in vtd_lookup_iotlb. VTDIOTLBPageInvInfo.mask is used in binary operations with addresses. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 2

Re: [PATCH v6 18/19] intel_iommu: Implement [set|unset]_iommu_device() callbacks

On 03/06/2024 08:10, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > From: Yi Liu > > Implement [set|unset]_iommu_device() callbacks in Intel vIOMMU. > In set call, a ne

Re: [PATCH intel_iommu 0/7] FLTS for VT-d

t is safe. > > > Hi Clement, > > Sorry for late response, just back from vacation. > I saw your rebased version and thanks for your work. > I'll schedule a timeslot to review them. > > Thanks > Zhenzhong > >> -Original Message- >> From: CLEMENT

Re: [PATCH intel_iommu 0/7] FLTS for VT-d

omments this week. > > Thanks > Zhenzhong > >> -Original Message- >> From: CLEMENT MATHIEU--DRIF >> Subject: Re: [PATCH intel_iommu 0/7] FLTS for VT-d >> >> Hi Zhenzhong >> >> Have you had time to review the ATS series rebased on you

Re: [PATCH ats_vtd v1 03/24] intel_iommu: check if the input address is canonical

Hi zhenzhong, On 14/05/2024 09:34, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Hi Clement, > >> -Original Message- >&g

[PATCH ats_vtd v2 05/25] intel_iommu: return page walk level even when the translation fails

We use this information in vtd_do_iommu_translate to populate the IOMMUTLBEntry and indicate the correct page mask. This prevents ATS devices from sending many useless translation requests when a megapage or gigapage iova is not mapped to a physical address. Signed-off-by: Clément Mathieu--Drif -

[PATCH ats_vtd v2 09/25] pcie: add helper to declare PASID capability for a pcie device

Signed-off-by: Clément Mathieu--Drif --- hw/pci/pcie.c | 24 +++ include/hw/pci/pcie.h | 6 +- include/hw/pci/pcie_regs.h| 3 +++ include/standard-headers/linux/pci_regs.h | 1 + 4 files changed, 33 inserti

[PATCH ats_vtd v2 02/25] intel_iommu: make types match

The 'level' field in vtd_iotlb_key is an uint8_t. We don't need to store level as an int in vtd_lookup_iotlb (avoids a 'loosing precision' warning). VTDIOTLBPageInvInfo.mask is used in binary operations with addresses. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 2

[PATCH ats_vtd v2 12/25] intel_iommu: add an internal API to find an address space with PASID

This will be used to implement the device IOTLB invalidation Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 39 --- 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 3bb4d385a8

[PATCH ats_vtd v2 20/25] intel_iommu: fill the PASID field when creating an instance of IOMMUTLBEntry

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 53f17d66c0..c4ebd4569e 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2299,6 +2299,7 @@ out: entry

[PATCH ats_vtd v2 17/25] intel_iommu: implement the get_address_space_pasid iommu operation

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 13 ++--- include/hw/i386/intel_iommu.h | 2 +- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index fd4710ba28..e48b169cda 100644 --- a/hw/i386/intel_i

[PATCH ats_vtd v2 16/25] pci: add a pci-level initialization function for iommu notifiers

We add a convenient way to initialize an device-iotlb notifier. This is meant to be used by ATS-capable devices. pci_device_iommu_memory_region_pasid is introduces in this commit and will be used in several other SVM-related functions exposed in the PCI API. Signed-off-by: Clément Mathieu--Drif

[PATCH ats_vtd v2 00/25] ATS support for VT-d

This series belongs to a list of series that add SVM support for VT-d. As a starting point, we use the series called 'intel_iommu: Enable stage-1 translation' (rfc2) by Zhenzhong Duan and Yi Liu. Here we focus on the implementation of ATS support in the IOMMU and on a PCI-level API for ATS to b

[PATCH ats_vtd v2 04/25] intel_iommu: set accessed and dirty bits during first stage translation

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 25 + hw/i386/intel_iommu_internal.h | 3 +++ 2 files changed, 28 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 0ecf00f37a..252364893b 100644 --- a/hw/i386/intel_io

[PATCH ats_vtd v2 19/25] memory: Allow to store the PASID in IOMMUTLBEntry

This will be useful for devices that support ATS Signed-off-by: Clément Mathieu--Drif --- include/exec/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/memory.h b/include/exec/memory.h index 2c0e964c07..198b71e9af 100644 --- a/include/exec/memory.h +++ b/include/exec/mem

[PATCH ats_vtd v2 01/25] intel_iommu: fix FRCD construction macro.

The constant must be unsigned, otherwise the two's complement overrides the other fields when a PASID is present Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu_internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/in

[PATCH ats_vtd v2 13/25] intel_iommu: add support for PASID-based device IOTLB invalidation

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 42 ++ hw/i386/intel_iommu_internal.h | 10 2 files changed, 47 insertions(+), 5 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 166103510e..fd4710ba28

[PATCH ats_vtd v2 21/25] atc: generic ATC that can be used by PCIe devices that support SVM

As the SVM-capable devices will need to cache translations, we provide an first implementation. This cache uses a two-level design based on hash tables. The first level is indexed by a PASID and the second by a virtual addresse. Signed-off-by: Clément Mathieu--Drif --- tests/unit/meson.build |

[PATCH ats_vtd v2 24/25] intel_iommu: set the address mask even when a translation fails

Implements the behavior defined in section 10.2.3.5 of PCIe spec rev 5. This is needed by devices that support ATS. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_

[PATCH ats_vtd v2 25/25] intel_iommu: add support for ATS

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 75 -- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 73 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 67b9ff4934..7421a99373 100644

[PATCH ats_vtd v2 18/25] intel_iommu: implement the get_memory_region_pasid iommu operation

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index e48b169cda..53f17d66c0 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -5997,9 +5997,24 @@ stat

[PATCH ats_vtd v2 07/25] intel_iommu: do not consider wait_desc as an invalid descriptor

Signed-off-by: Clément Mathieu--Drif Reviewed-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index dbdf13470d..373f3d254a 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3362,6

[PATCH ats_vtd v2 22/25] memory: add an API for ATS support

IOMMU have to implement iommu_ats_request_translation to support ATS. Devices can use IOMMU_TLB_ENTRY_TRANSLATION_ERROR to check the tlb entries returned by a translation request. Signed-off-by: Clément Mathieu--Drif --- include/exec/memory.h | 26 ++ system/memory.c

[PATCH ats_vtd v2 10/25] pcie: helper functions to check if PASID and ATS are enabled

ats_enabled and pasid_enabled check whether the capabilities are present or not. If so, we read the configuration space to get the status of the feature (enabled or not). Signed-off-by: Clément Mathieu--Drif --- hw/pci/pcie.c | 18 ++ include/hw/pci/pcie.h | 3 +++ 2 fil

[PATCH ats_vtd v2 03/25] intel_iommu: check if the input address is canonical

First stage translation must fail if the address to translate is not canonical. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 21 + hw/i386/intel_iommu_internal.h | 2 ++ 2 files changed, 23 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i

[PATCH ats_vtd v2 06/25] intel_iommu: extract device IOTLB invalidation logic

This piece of code can be shared by both IOTLB invalidation and PASID-based IOTLB invalidation Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 57 +-- 1 file changed, 33 insertions(+), 24 deletions(-)

[PATCH ats_vtd v2 11/25] intel_iommu: declare supported PASID size

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 2 +- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 373f3d254a..3bb4d385a8 100644 --- a/hw/i386/intel_iommu.c +++ b/h

[PATCH ats_vtd v2 14/25] pci: cache the bus mastering status in the device

Signed-off-by: Clément Mathieu--Drif --- hw/pci/pci.c| 24 ++-- include/hw/pci/pci_device.h | 1 + 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 045d69f4c1..e5f72f9f1d 100644 --- a/hw/pci/pci.c +++ b/hw/pci/

[PATCH ats_vtd v2 08/25] memory: add permissions in IOMMUAccessFlags

This will be necessary for devices implementing ATS. We also define a new macro IOMMU_ACCESS_FLAG_FULL in addition to IOMMU_ACCESS_FLAG to support more access flags. IOMMU_ACCESS_FLAG is kept for convenience and backward compatibility. Here are the flags added (defined by the PCIe 5 specification)

[PATCH ats_vtd v2 23/25] pci: add a pci-level API for ATS

Devices implementing ATS can send translation requests using pci_ats_request_translation_pasid. The invalidation events are sent back to the device using the iommu notifier managed with pci_register_iommu_tlb_event_notifier and pci_unregister_iommu_tlb_event_notifier Signed-off-by: Clément Mathie

[PATCH ats_vtd v2 15/25] pci: add IOMMU operations to get address spaces and memory regions with PASID

Signed-off-by: Clément Mathieu--Drif --- hw/pci/pci.c | 19 +++ include/hw/pci/pci.h | 34 ++ 2 files changed, 53 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index e5f72f9f1d..2b42b4e4cc 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci

Re: [PATCH ats_vtd v1 03/24] intel_iommu: check if the input address is canonical

Hi, On 16/05/2024 08:41, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > >> -Original Message- >> From: CLEMENT MATHIEU--DRIF >>

Re: [PATCH ats_vtd v2 20/25] intel_iommu: fill the PASID field when creating an instance of IOMMUTLBEntry

On 17/05/2024 12:40, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > >> -Original Message- >> From: CLEMENT MATHIEU--DRIF >> Su

Re: [PATCH ats_vtd v2 21/25] atc: generic ATC that can be used by PCIe devices that support SVM

On 17/05/2024 12:44, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > >> -Original Message- >> From: CLEMENT MATHIEU--DRIF >> Su

Re: [PATCH] intel_iommu: Use the latest fault reasons defined by spec

Hi Zhenzhong On 17/05/2024 12:23, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > From: Yu Zhang > > Currently we use only VTD_FR_PASID_TABLE_INV as fault reason. > Upda

Re: [PATCH] intel_iommu: Use the latest fault reasons defined by spec

> From: CLEMENT MATHIEU--DRIF > Sent: Friday, May 17, 2024 9:13 PM > > Hi Zhenzhong > > On 17/05/2024 12:23, Zhenzhong Duan wrote: > > Caution: External email. Do not open attachments or click links, unless > > this email > comes from a known sender

Re: [PATCH ats_vtd v2 20/25] intel_iommu: fill the PASID field when creating an instance of IOMMUTLBEntry

On 21/05/2024 05:11, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > >> -Original Message- >> From: CLEMENT MATHIEU--DRIF >> Subjec

[PATCH ats_vtd 19/22] memory: add an API for ATS support

IOMMU have to implement iommu_ats_request_translation to support ATS. Devices can use IOMMU_TLB_ENTRY_TRANSLATION_ERROR to check the tlb entries returned by a translation request. Signed-off-by: Clément Mathieu--Drif --- include/exec/memory.h | 26 ++ system/memory.c

[PATCH ats_vtd 13/22] intel_iommu: implement the get_address_space_pasid iommu operation

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 13 ++--- include/hw/i386/intel_iommu.h | 2 +- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 7d86a31bea..e83985f2f7 100644 --- a/hw/i386/intel_i

[PATCH ats_vtd 05/22] memory: add permissions in IOMMUAccessFlags

This will be necessary for devices implementing ATS. We also define a new macro IOMMU_ACCESS_FLAG_FULL in addition to IOMMU_ACCESS_FLAG to support more access flags. IOMMU_ACCESS_FLAG is kept for convenience and backward compatibility. Here are the flags added (defined by the PCIe 5 specification)

[PATCH ats_vtd 06/22] pcie: add helper to declare PASID capability for a pcie device

Signed-off-by: Clément Mathieu--Drif --- hw/pci/pcie.c | 24 +++ include/hw/pci/pcie.h | 6 +- include/hw/pci/pcie_regs.h| 3 +++ include/standard-headers/linux/pci_regs.h | 1 + 4 files changed, 33 inserti

[PATCH ats_vtd 14/22] intel_iommu: implement the get_memory_region_pasid iommu operation

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index e83985f2f7..a42938aacd 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -5975,9 +5975,24 @@ stat

[PATCH ats_vtd 07/22] pcie: helper functions to check if PASID and ATS are enabled

ats_enabled and pasid_enabled check whether the capabilities are present or not. If so, we read the configuration space to get the status of the feature (enabled or not). Signed-off-by: Clément Mathieu--Drif --- hw/pci/pcie.c | 18 ++ include/hw/pci/pcie.h | 3 +++ 2 fil

[PATCH ats_vtd 00/22] ATS support for VT-d

This series belongs to a list of series that add SVM support for VT-d. As a starting point, we use the series called 'intel_iommu: Enable stage-1 translation for passthrough device' by Zhenzhong Duan and Yi Liu. Here we focus on the implementation of ATS support in the IOMMU and on a PCI-level

[PATCH ats_vtd 11/22] memory: store user data pointer in the IOMMU notifiers

This will help developers of svm devices to track a state Signed-off-by: Clément Mathieu--Drif --- include/exec/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/memory.h b/include/exec/memory.h index 0067b2266a..359bca2ae2 100644 --- a/include/exec/memory.h +++ b/include

[PATCH ats_vtd 01/22] intel_iommu: fix FRCD construction macro.

The constant must be unsigned, otherwise the two's complement overrides the other fields when a PASID is present Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu_internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/in

[PATCH ats_vtd 15/22] memory: Allow to store the PASID in IOMMUTLBEntry

This will be useful for devices that support ATS Signed-off-by: Clément Mathieu--Drif --- include/exec/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/memory.h b/include/exec/memory.h index 359bca2ae2..56ef48780f 100644 --- a/include/exec/memory.h +++ b/include/exec/mem

[PATCH ats_vtd 20/22] pci: add a pci-level API for ATS

Devices implementing ATS can send translation requests using pci_ats_request_translation_pasid. The invalidation events are sent back to the device using the iommu notifier managed with pci_register_iommu_tlb_event_notifier and pci_unregister_iommu_tlb_event_notifier Signed-off-by: Clément Mathie

[PATCH ats_vtd 08/22] intel_iommu: declare supported PASID size

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 2 +- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index f71c04d370..7d86a31bea 100644 --- a/hw/i386/intel_iommu.c +++ b/h

[PATCH ats_vtd 17/22] atc: generic ATC that can be used by PCIe devices that support SVM

As the SVM-capable devices will need to cache translations, we provide an first implementation. This cache uses a two-level design based on hash tables. The first level is indexed by a PASID and the second by a virtual addresse. Signed-off-by: Clément Mathieu--Drif --- util/atc.c | 211 ++

[PATCH ats_vtd 22/22] intel_iommu: add support for ATS

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 75 -- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 73 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 496bed9447..2e78ebe6d2 100644

[PATCH ats_vtd 16/22] intel_iommu: fill the PASID field when creating an instance of IOMMUTLBEntry

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 9 + 1 file changed, 9 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index a42938aacd..f08c3e8f00 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2187,6 +2187,9 @@ static bool v

[PATCH ats_vtd 12/22] pci: add a pci-level initialization function for iommu notifiers

We add a convenient way to initialize an device-iotlb notifier. This is meant to be used by ATS-capable devices. pci_device_iommu_memory_region_pasid is introduces in this commit and will be used in several other SVM-related functions exposed in the PCI API. Signed-off-by: Clément Mathieu--Drif

[PATCH ats_vtd 09/22] pci: cache the bus mastering status in the device

Signed-off-by: Clément Mathieu--Drif --- hw/pci/pci.c| 24 ++-- include/hw/pci/pci_device.h | 1 + 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index c8a8aab306..51feede3cf 100644 --- a/hw/pci/pci.c +++ b/hw/pci/

[PATCH ats_vtd 18/22] atc: add unit tests

Signed-off-by: Clément Mathieu--Drif --- tests/unit/meson.build | 1 + tests/unit/test-atc.c | 527 + 2 files changed, 528 insertions(+) create mode 100644 tests/unit/test-atc.c diff --git a/tests/unit/meson.build b/tests/unit/meson.build index 26c109c

[PATCH ats_vtd 03/22] intel_iommu: return page walk level even when the translation fails

We use this information in vtd_do_iommu_translate to populate the IOMMUTLBEntry and indicate the correct page mask. This prevents ATS devices from sending many useless translation requests when a megapage or gigapage iova is not mapped to a physical address. Signed-off-by: Clément Mathieu--Drif -

[PATCH ats_vtd 02/22] intel_iommu: make types match

The 'level' field in vtd_iotlb_key is an uint8_t. We don't need to store level as an int in vtd_lookup_iotlb (avoids a 'loosing precision' warning). VTDIOTLBPageInvInfo.mask is used in binary operations with addresses. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 2

[PATCH ats_vtd 21/22] intel_iommu: set the address mask even when a translation fails

Implements the behavior defined in section 10.2.3.5 of PCIe spec rev 5. This is needed by devices that support ATS. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_

[PATCH ats_vtd 04/22] intel_iommu: do not consider wait_desc as an invalid descriptor

Signed-off-by: Clément Mathieu--Drif Reviewed-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index a2b275016c..f71c04d370 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3476,6

[PATCH ats_vtd 10/22] pci: add IOMMU operations to get address spaces and memory regions with PASID

Signed-off-by: Clément Mathieu--Drif --- hw/pci/pci.c | 19 +++ include/hw/pci/pci.h | 34 ++ 2 files changed, 53 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 51feede3cf..3fe47d4002 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci

Re: [PATCH rfcv2 15/17] intel_iommu: Set default aw_bits to 48 in scalable modren mode

Hi Zhenzhong On 22/05/2024 08:23, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > According to VTD spec, stage-1 page table could support 4-level and > 5-level paging. >

Re: [PATCH rfcv2 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation

Hi Zhenzhong On 22/05/2024 08:23, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > According to spec, Page-Selective-within-Domain Invalidation (11b): > > 1. IOTLB entries

Re: [PATCH rfcv2 06/17] intel_iommu: Implement stage-1 translation

Hi Zhenzhong, I already sent you my comments about this patch earlier (question about checking pgtt) but here is a style review On 22/05/2024 08:23, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you kno

Re: [PATCH rfcv2 15/17] intel_iommu: Set default aw_bits to 48 in scalable modren mode

On 27/05/2024 05:16, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Hi Clement, > >> -Original Message- >> From: CLEMENT MATHIEU-

Re: [PATCH v1 0/8] PRI support for VT-d

Hi, Just adding Michael in Cc: Thanks >cmd On 30/05/2024 14:24, CLEMENT MATHIEU--DRIF wrote: > This series belongs to a list of series that add SVM support for VT-d. > > Here we focus on the implementation of PRI support in the IOMMU and on a > PCI-level > API for PRI to

Re: [PATCH v2 00/17] intel_iommu: Enable stage-1 translation for emulated device

Hi Zhenzhong, Do you plan to post a v3 for this series? Thanks >cmd On 05/08/2024 08:27, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Hi, > > Per Jason Wang's sugge

Re: [PATCH v3 03/17] intel_iommu: Add a placeholder variable for scalable modern mode

On 11/09/2024 07:22, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Add an new element scalable_mode in IntelIOMMUState to mark scalable > modern mode, this element wil

Re: [PATCH v3 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation

Reviewed-by: Clément Mathieu--Drif On 11/09/2024 07:22, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Per spec 6.5.2.4, PADID-selective PASID-based iotlb invalidation

Re: [PATCH v3 15/17] intel_iommu: Modify x-scalable-mode to be string option to expose scalable modern mode

Reviewed-by: Clément Mathieu--Drif On 11/09/2024 07:22, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > From: Yi Liu > > Intel VT-d 3.0 introduces scalable mode, and i

Re: [PATCH v3 00/17] intel_iommu: Enable stage-1 translation for emulated device

Hi Zhenzhong, Thanks for posting a new version. I think it starting to look good. Just a few comments. >cmd On 11/09/2024 07:22, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is sa

[PATCH v1 1/3] intel_iommu: fix FRCD construction macro.

From: Clément Mathieu--Drif The constant must be unsigned, otherwise the two's complement overrides the other fields when a PASID is present Fixes: 1b2b12376c ("intel-iommu: PASID support") Signed-off-by: Clément Mathieu--Drif Reviewed-by: Yi Liu --- hw/i386/intel_iommu_internal.h | 2 +- 1

[PATCH v1 0/3] VT-d minor fixes

From: Clement Mathieu--Drif Various fixes for VT-d This series contains fixes that will be necessary when adding in-guest (fully emulated) SVM support. Clement Mathieu--Drif (2): intel_iommu: make types match intel_iommu: Bypass barrier wait descriptor Clément Mathieu--Drif (1

[PATCH v1 2/3] intel_iommu: make types match

From: Clement Mathieu--Drif The 'level' field in vtd_iotlb_key is an unsigned integer. We don't need to store level as an int in vtd_lookup_iotlb. VTDIOTLBPageInvInfo.mask is used in binary operations with addresses. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu

[PATCH v1 3/3] intel_iommu: Bypass barrier wait descriptor

From: Clement Mathieu--Drif wait_desc with SW=0,IF=0,FN=1 must not be considered as an invalid descriptor as it is used to implement section 7.10 of the VT-d spec Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/hw/i386

Re: [PATCH v1 0/8] PRI support for VT-d

From: Michael S. Tsirkin Sent: 04 July 2024 08:24 To: CLEMENT MATHIEU--DRIF Cc: qemu-devel@nongnu.org ; jasow...@redhat.com ; zhenzhong.d...@intel.com ; kevin.t...@intel.com ; yi.l@intel.com ; joao.m.mart...@oracle.com ; pet...@redhat.com Subject: Re

[PATCH v2 1/3] intel_iommu: fix FRCD construction macro.

From: Clément Mathieu--Drif The constant must be unsigned, otherwise the two's complement overrides the other fields when a PASID is present Fixes: 1b2b12376c ("intel-iommu: PASID support") Signed-off-by: Clément Mathieu--Drif Reviewed-by: Yi Liu --- hw/i386/intel_iommu_internal.h | 2 +- 1

[PATCH v2 0/3] VT-d minor fixes

From: Clément Mathieu--Drif Various fixes for VT-d This series contains fixes that will be necessary when adding in-guest (fully emulated) SVM support. v2 Make commit author consistent Clément Mathieu--Drif (3): intel_iommu: fix FRCD construction macro. intel_iommu: make types match

[PATCH v2 2/3] intel_iommu: make types match

From: Clément Mathieu--Drif The 'level' field in vtd_iotlb_key is an unsigned integer. We don't need to store level as an int in vtd_lookup_iotlb. VTDIOTLBPageInvInfo.mask is used in binary operations with addresses. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 2

[PATCH v2 3/3] intel_iommu: Bypass barrier wait descriptor

From: Clément Mathieu--Drif wait_desc with SW=0,IF=0,FN=1 must not be considered as an invalid descriptor as it is used to implement section 7.10 of the VT-d spec Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/hw/i386/in

[PATCH v3 3/3] intel_iommu: make types match

From: Clément Mathieu--Drif The 'level' field in vtd_iotlb_key is an unsigned integer. We don't need to store level as an int in vtd_lookup_iotlb. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/intel_io

<    1   2   3   4   5   >