Hi Shiva,
>-Original Message-
>From: Shiva sagar Myana
>Sent: Friday, May 31, 2024 1:56 PM
>To: Iglesias, Francisco ; jasow...@redhat.com;
>qemu-devel@nongnu.org; p...@cmp.felk.cvut.cz
>Cc: peter.mayd...@linaro.org; Boddu, Sai Pavan ;
>Myana, Shivasagar
>Subject:
Hi Edgar,
From: Edgar E. Iglesias
Sent: Friday, June 14, 2024 4:38 PM
To: Boddu, Sai Pavan
Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Alistair Francis
; Peter Maydell ; Iglesias,
Francisco
Subject: Re: [PATCH 2/2] hw/arm/xilinx_zynq: Add boot-mode property
On Thu, Jun 13, 2024 at 5
Hi Edgar,
From: Boddu, Sai Pavan
Sent: Friday, June 14, 2024 8:37 PM
To: Edgar E. Iglesias
Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Alistair Francis
; Peter Maydell ; Iglesias,
Francisco
Subject: RE: [PATCH 2/2] hw/arm/xilinx_zynq: Add boot-mode property
Hi Edgar,
I examined -boot
il.com; peter.mayd...@linaro.org; Konrad, Frederic
>; Boddu, Sai Pavan
>; Ho, Tong ; Garhwal,
>Vikram
>Subject: [PATCH v1 1/8] hw/misc: Introduce the Xilinx CFI interface
>
>Introduce the Xilinx Configuration Frame Interface (CFI) for transmitting CFI
>data packets between the Xilinx C
Hi Peter,
>-Original Message-
>From: Peter Maydell
>Sent: Tuesday, December 12, 2023 10:12 PM
>To: Boddu, Sai Pavan
>Cc: qemu-devel@nongnu.org; qemu-...@nongnu.org; qemu-
>bl...@nongnu.org; Alistair Francis ; Edgar E. Iglesias
>; Kevin Wolf ; Francisco
&
ason Wang
>; Philippe Mathieu-Daudé ;
>Iglesias, Francisco ; Konrad, Frederic
>; Boddu, Sai Pavan
>
>Subject: [PATCH 01/11] hw/net/cadence_gem: use REG32 macro for register
>definitions
>
>Replace register defines with the REG32 macro from registerfields.h in the
>
rancisco ; Konrad, Frederic
>; Boddu, Sai Pavan
>
>Subject: [PATCH 02/11] hw/net/cadence_gem: use FIELD for screening registers
>
>Describe screening registers fields using the FIELD macros.
>
>Signed-off-by: Luc Michel
Reviewed-by: sai.pavan.bo...@amd.com
Reg
rancisco ; Konrad, Frederic
>; Boddu, Sai Pavan
>
>Subject: [PATCH 03/11] hw/net/cadence_gem: use FIELD to describe NWCTRL
>register fields
>
>Use the FIELD macro to describe the NWCTRL register fields.
>
>Signed-off-by: Luc Michel
Reviewed-by: sai.pavan.bo...@amd.com
R
rancisco ; Konrad, Frederic
>; Boddu, Sai Pavan
>
>Subject: [PATCH 04/11] hw/net/cadence_gem: use FIELD to describe NWCFG
>register fields
>
>Use de FIELD macro to describe the NWCFG register fields.
>
>Signed-off-by: Luc Michel
Reviewed-by: sai.pavan.bo...@amd.com
rancisco ; Konrad, Frederic
>; Boddu, Sai Pavan
>
>Subject: [PATCH 05/11] hw/net/cadence_gem: use FIELD to describe DMACFG
>register fields
>
>Use de FIELD macro to describe the DMACFG register fields.
>
>Signed-off-by: Luc Michel
Reviewed-by: sai.pa
rancisco ; Konrad, Frederic
>; Boddu, Sai Pavan
>
>Subject: [PATCH 06/11] hw/net/cadence_gem: use FIELD to describe
>[TX|RX]STATUS register fields
>
>Use de FIELD macro to describe the TXSTATUS and RXSTATUS register fields.
>
>Signed-off-by: Luc Michel
Reviewed-by: sai.pav
rancisco ; Konrad, Frederic
>; Boddu, Sai Pavan
>
>Subject: [PATCH 07/11] hw/net/cadence_gem: use FIELD to describe IRQ
>register fields
>
>Use de FIELD macro to describe the IRQ related register fields.
>
>Signed-off-by: Luc Michel
Reviewed-by: sai.pav
rancisco ; Konrad, Frederic
>; Boddu, Sai Pavan
>
>Subject: [PATCH 09/11] hw/net/cadence_gem: use FIELD to describe
>PHYMNTNC register fields
>
>Use the FIELD macro to describe the PHYMNTNC register fields.
>
>Signed-off-by: Luc Michel
Reviewed-by: sai.pa
rancisco ; Konrad, Frederic
>; Boddu, Sai Pavan
>
>Subject: [PATCH 10/11] hw/net/cadence_gem: perform PHY access on write
>only
>
>The MDIO access is done only on a write to the PHYMNTNC register. A
>subsequent read is used to retrieve the result but does not trigger an MDIO
>
rancisco ; Konrad, Frederic
>; Boddu, Sai Pavan
>
>Subject: [PATCH 11/11] hw/net/cadence_gem: enforce 32 bits variable size for
>CRC
>
>The CRC was stored in an unsigned variable in gem_receive. Change it for a
>uint32_t to ensure we have the correct variable size here.
>
>
Hi Daniel,
Thanks for the review, I will send a V2 addressing the comments.
Regards,
Sai Pavan
>-Original Message-
>From: Daniel Henrique Barboza
>Sent: Wednesday, October 16, 2024 1:28 AM
>To: Boddu, Sai Pavan ; qemu-devel@nongnu.org;
>qemu-ri...@nongnu.org
>Cc: Paol
Hi Alistair,
Thanks for the review, I will send a v3 as follow-up.
Regards,
Sai Pavan
>-Original Message-
>From: Alistair Francis
>Sent: Thursday, October 31, 2024 10:01 AM
>To: Philippe Mathieu-Daudé
>Cc: Simek, Michal ; Boddu, Sai Pavan
>; qemu-devel@nongnu.org; qem
Thanks Phil, I will send a v3 for follow-up.
Regards,
Sai Pavan
>-Original Message-
>From: Philippe Mathieu-Daudé
>Sent: Thursday, October 31, 2024 9:30 PM
>To: Simek, Michal ; Alistair Francis
>; Boddu, Sai Pavan
>Cc: qemu-devel@nongnu.org; qemu-ri...@nongnu.
Hi,
I would be out of office first half, will connect online post lunch.
Regards,
Sai Pavan
Hi Alistair,
Thanks for Review. I will address below comments in V4.
Regards,
Sai Pavan
>-Original Message-
>From: Alistair Francis
>Sent: Monday, November 18, 2024 11:37 AM
>To: Boddu, Sai Pavan
>Cc: qemu-devel@nongnu.org; qemu-ri...@nongnu.org; Paolo Bonzini
>; Pa
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