On Tue, Mar 25, 2014 at 09:49:21AM +1000, Peter Crosthwaite wrote:
> On Fri, Mar 21, 2014 at 7:25 AM, Beniamino Galvani
> wrote:
> > This implements the prescaler and source fields of the timer control
> > register. The source for each timer can be selected among 4 cloc
tch 5)
v2: Address comments from Li Guang:
* make pic vector register read-only
* allow writing to pic pending register
Beniamino Galvani (7):
allwinner-a10-pic: set vector address when an interrupt is pending
allwinner-a10-pic: fix behaviour of pending register
allwinner-a10-pit:
The irq line status must be updated after writes to the INT_CTL and
INT_STA registers.
Signed-off-by: Beniamino Galvani
Reviewed-by: Peter Crosthwaite
---
hw/net/allwinner_emac.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/net/allwinner_emac.c b/hw/net/allwinner_emac.c
index
.
Signed-off-by: Beniamino Galvani
Reviewed-by: Peter Crosthwaite
Reviewed-by: Li Guang
---
hw/intc/allwinner-a10-pic.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c
index 407d563..00f3c11 100644
--- a/hw
Convert the interrupt generation logic to the use of level triggered
interrupts.
Signed-off-by: Beniamino Galvani
Reviewed-by: Peter Crosthwaite
---
hw/timer/allwinner-a10-pit.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/hw/timer/allwinner-a10-pit.c b
The pending register is read-only and the value returned upon a read
reflects the state of irq input pins (interrupts are level triggered).
This patch implements such behaviour.
Signed-off-by: Beniamino Galvani
Reviewed-by: Li Guang
Reviewed-by: Peter Crosthwaite
---
hw/intc/allwinner-a10
The model was generating interrupts for all enabled timers after the
expiration of one of them. Avoid this by passing explicitly the timer
index to the callback function.
Signed-off-by: Beniamino Galvani
Reviewed-by: Li Guang
Reviewed-by: Peter Crosthwaite
---
hw/timer/allwinner-a10-pit.c
This implements the prescaler and source fields of the timer control
register. The source for each timer can be selected among 4 clock
inputs whose frequencies are set through model properties.
Signed-off-by: Beniamino Galvani
Reviewed-by: Peter Crosthwaite
---
hw/arm/cubieboard.c
Signed-off-by: Beniamino Galvani
Reviewed-by: Peter Crosthwaite
---
hw/net/allwinner_emac.c |4 ++--
include/hw/net/allwinner_emac.h |1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/net/allwinner_emac.c b/hw/net/allwinner_emac.c
index 469f2f0..91931ac
alue.
> */
>
> -uint8_t fifo8_pop(Fifo8 *fifo);
> +uint8_t fifo_pop(Fifo *fifo);
>
> /**
> - * fifo8_pop_buf:
> + * fifo_pop_buf:
> * @fifo: FIFO to pop from
> * @max: maximum number of bytes to pop
> * @num: actual number of returned bytes
Perhaps these and the remaining occurrences of 'bytes' should be
replaced as well.
Otherwise:
Reviewed-by: Beniamino Galvani
On Mon, Apr 07, 2014 at 07:05:18PM -0700, Peter Crosthwaite wrote:
> Add support for 16, 32 and 64 bit width FIFOs. The push and pop
> functions are patched to accept uint64_t always to support up to 64bit
> integer elements. The element width is set at creation time.
>
> The backing storage for a
NC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
> gem_phy_write(s, reg_num, val);
> }
Although 802.3 standard dictates that PHYs must always respond to
address 0, AFAIK not all PHYs do this.
In this case, if the Marvell PHY complies with standard:
Reviewed-by: Beniamino Galvani
e(struct PHY *phy, unsigned int req, unsigned int
> data)
> phy->regs[regnum] = data;
> break;
> }
> +
> +/* Unconditionally clear regs[BMCR][BMCR_RESET] */
> + phy->regs[0] &= ~0x8000;
> }
>
> static void
> --
On Wed, Apr 09, 2014 at 11:42:31PM -0700, Peter Crosthwaite wrote:
> Add support for 16, 32 and 64 bit width FIFOs. The push and pop
> functions are replicated to accept all four different integer types.
> The element width of the FIFO is set at creation time.
>
> The backing storage for all eleme
This patch series adds support for the EMAC Fast Ethernet controller
found on Allwinner SoCs to the Allwinner A10.
Beniamino Galvani (2):
hw/net: add support for Allwinner EMAC Fast Ethernet controller
hw/arm/allwinner-a10: initialize EMAC
default-configs/arm-softmmu.mak |1 +
hw/arm
Signed-off-by: Beniamino Galvani
---
hw/arm/allwinner-a10.c | 20
include/hw/arm/allwinner-a10.h |4
2 files changed, 24 insertions(+)
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index 4658e19..155e026 100644
--- a/hw/arm/allwinner-a10.c
This patch adds support for the Fast Ethernet MAC found on Allwinner
SoCs, together with a basic emulation of Realtek RTL8201CP PHY.
Since there is no public documentation of the Allwinner controller, the
implementation is based on Linux kernel driver.
Signed-off-by: Beniamino Galvani
.fields = (VMStateField[]) {
> > +VMSTATE_UINT16(bmcr, AwEmacMii),
> > +VMSTATE_UINT16(bmsr, AwEmacMii),
> > +VMSTATE_UINT16(anar, AwEmacMii),
> > +VMSTATE_UINT16(anlpar, AwEmacMii),
> > +VMSTATE_BOOL(link_ok, AwEmacMii),
> > +
On Thu, Jan 02, 2014 at 08:20:12PM +1000, Peter Crosthwaite wrote:
> On Thu, Jan 2, 2014 at 7:18 PM, Beniamino Galvani wrote:
> > Signed-off-by: Beniamino Galvani
> > ---
> > hw/arm/allwinner-a10.c | 20
> > include/hw/arm/allwinner-a10
On Fri, Jan 03, 2014 at 11:26:01AM +1000, Peter Crosthwaite wrote:
> >> > +static const VMStateDescription vmstate_tx_fifo = {
> >> > +.name = "allwinner_emac_tx_fifo",
> >> > +.version_id = 1,
> >> > +.minimum_version_id = 1,
> >> > +.fields = (VMStateField[]) {
> >> > +VMS
On Sat, Jan 04, 2014 at 10:56:13AM +1000, Peter Crosthwaite wrote:
> On Thu, Jan 2, 2014 at 7:18 PM, Beniamino Galvani wrote:
> > This patch adds support for the Fast Ethernet MAC found on Allwinner
> > SoCs, together with a basic emulation of Realtek RTL8201CP PHY.
> >
On Mon, Jan 06, 2014 at 08:49:18AM +0800, Li Guang wrote:
> Hi,
> please use prefix AwA10 for names instead of Aw,
> also PATCH 1/2.
Hi,
I agree with you that there is an inconsistency in the naming of EMAC
and other A10 devices (timer, interrupt controller).
But the EMAC core is used not only o
On Mon, Jan 06, 2014 at 02:12:27PM +0800, Stefan Hajnoczi wrote:
> > >> More a comment for net in general, but I think sooner or later we need
> > >> to move towards a split between phy and mac on the device level.
> > >> continuing the phy-within-mac philosophy is going to make the
> > >> socifica
This patch adds support for the Fast Ethernet MAC found on Allwinner
SoCs, together with a basic emulation of Realtek RTL8201CP PHY.
Since there is no public documentation of the Allwinner controller, the
implementation is based on Linux kernel driver.
Signed-off-by: Beniamino Galvani
reate EMAC instance in SoC
* Use uint8 arrays for fifos
* Minor cleanups
Beniamino Galvani (2):
hw/net: add support for Allwinner EMAC Fast Ethernet controller
hw/arm/allwinner-a10: initialize EMAC
default-configs/arm-softmmu.mak |1 +
hw/arm/allwinner-a10.c | 16 ++
h
Signed-off-by: Beniamino Galvani
---
hw/arm/allwinner-a10.c | 16
hw/arm/cubieboard.c|7 +++
include/hw/arm/allwinner-a10.h |3 +++
3 files changed, 26 insertions(+)
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index 4658e19
On Mon, Jan 13, 2014 at 11:15:17PM +1000, Peter Crosthwaite wrote:
> On Sat, Jan 11, 2014 at 8:13 PM, Beniamino Galvani
> wrote:
> > This patch adds support for the Fast Ethernet MAC found on Allwinner
> > SoCs, together with a basic emulation of Realtek RTL8201CP PHY.
> &g
This patch adds support for the Fast Ethernet MAC found on Allwinner
SoCs, together with a basic emulation of Realtek RTL8201CP PHY.
Since there is no public documentation of the Allwinner controller, the
implementation is based on Linux kernel driver.
Signed-off-by: Beniamino Galvani
eate EMAC instance in SoC
* Use uint8 arrays for fifos
* Minor cleanups
Beniamino Galvani (2):
hw/net: add support for Allwinner EMAC Fast Ethernet controller
hw/arm/allwinner-a10: initialize EMAC
default-configs/arm-softmmu.mak |1 +
hw/arm/allwinner-a10.c | 16 ++
Signed-off-by: Beniamino Galvani
---
hw/arm/allwinner-a10.c | 16
hw/arm/cubieboard.c|7 +++
include/hw/arm/allwinner-a10.h |3 +++
3 files changed, 26 insertions(+)
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index 4658e19
This implements the prescaler and source fields of the timer control
register as described in the A10 user manual.
Signed-off-by: Beniamino Galvani
---
hw/timer/allwinner-a10-pit.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/hw/timer/allwinner-a10
Signed-off-by: Beniamino Galvani
---
hw/intc/allwinner-a10-pic.c |6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c
index bb2351f..afd57ef 100644
--- a/hw/intc/allwinner-a10-pic.c
+++ b/hw/intc/allwinner-a10-pic.c
.
Signed-off-by: Beniamino Galvani
---
hw/intc/allwinner-a10-pic.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c
index 407d563..bb2351f 100644
--- a/hw/intc/allwinner-a10-pic.c
+++ b/hw/intc/allwinner-a10-pic.c
The irq line status must be updated after writes to the INT_CTL and
INT_STA registers.
Signed-off-by: Beniamino Galvani
---
hw/net/allwinner_emac.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/net/allwinner_emac.c b/hw/net/allwinner_emac.c
index 91931ac..d780ba0 100644
--- a/hw
Converts the interrupt generation logic to the use of level triggered
interrupts.
Signed-off-by: Beniamino Galvani
---
hw/timer/allwinner-a10-pit.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c
Signed-off-by: Beniamino Galvani
---
hw/net/allwinner_emac.c |4 ++--
include/hw/net/allwinner_emac.h |1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/net/allwinner_emac.c b/hw/net/allwinner_emac.c
index 469f2f0..91931ac 100644
--- a/hw/net
a NFS root:
https://gist.github.com/anonymous/3e09495652009c6b9da4
Beniamino Galvani (7):
allwinner-a10-pic: set vector address when an interrupt is pending
allwinner-a10-pic: fix interrupt clear behaviour
allwinner-a10-pit: avoid generation of spurious interrupts
allwinner-a10-pit: use
The model was generating interrupts for all enabled timers after the
expiration of one of them. Avoid this by passing to the timer callback
function a structure containing the index of the expired timer.
Signed-off-by: Beniamino Galvani
---
hw/timer/allwinner-a10-pit.c | 30
On Tue, Feb 18, 2014 at 11:27:11AM +0800, Li Guang wrote:
> Hi,
>
> Beniamino Galvani wrote:
> >This patch implements proper updating of the vector register which
> >should hold, according to the A10 user manual, the vector address for
> >the interrupt currently
On Tue, Feb 18, 2014 at 11:49:51AM +0800, Li Guang wrote:
> Beniamino Galvani wrote:
> >According to this mail thread [1], writing to pending register seems
> >to have no effect on actual pending status of interrupts. This means
> >that the only way to clear a pending inte
On Tue, Feb 18, 2014 at 12:17:04PM +0800, Li Guang wrote:
> Beniamino Galvani wrote:
> >The model was generating interrupts for all enabled timers after the
> >expiration of one of them. Avoid this by passing to the timer callback
> >function a structure containing the index
On Tue, Feb 18, 2014 at 11:51:42AM +0800, Li Guang wrote:
> Beniamino Galvani wrote:
> >Converts the interrupt generation logic to the use of level triggered
> >interrupts.
>
> any real difference, or block something?
This is a consequence of the change to the implementatio
On Wed, Feb 19, 2014 at 10:02:36AM +0800, Li Guang wrote:
> Beniamino Galvani wrote:
> >On Tue, Feb 18, 2014 at 11:49:51AM +0800, Li Guang wrote:
> >>Beniamino Galvani wrote:
> >>>According to this mail thread [1], writing to pending register seems
> >>>
On Mon, Feb 24, 2014 at 02:45:06PM +0800, Li Guang wrote:
> Beniamino Galvani wrote:
> >On Wed, Feb 19, 2014 at 10:02:36AM +0800, Li Guang wrote:
> >>Beniamino Galvani wrote:
> >>>On Tue, Feb 18, 2014 at 11:49:51AM +0800, Li Guang wrote:
> >>>>Beniamino
4-rc2 using a NFS root:
https://gist.github.com/anonymous/3e09495652009c6b9da4
Changelog:
v2: Address comments from Li Guang:
* make pic vector register read-only
* allow writing to pic pending register
Beniamino Galvani (7):
allwinner-a10-pic: set vector address when an interrupt is pe
This implements the prescaler and source fields of the timer control
register as described in the A10 user manual.
Signed-off-by: Beniamino Galvani
---
hw/timer/allwinner-a10-pit.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/hw/timer/allwinner-a10
.
Signed-off-by: Beniamino Galvani
---
hw/intc/allwinner-a10-pic.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c
index 407d563..00f3c11 100644
--- a/hw/intc/allwinner-a10-pic.c
+++ b/hw/intc/allwinner-a10
Convert the interrupt generation logic to the use of level triggered
interrupts.
Signed-off-by: Beniamino Galvani
---
hw/timer/allwinner-a10-pit.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c
The irq line status must be updated after writes to the INT_CTL and
INT_STA registers.
Signed-off-by: Beniamino Galvani
---
hw/net/allwinner_emac.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/net/allwinner_emac.c b/hw/net/allwinner_emac.c
index 91931ac..d780ba0 100644
--- a/hw
The value of pending register was updated only when an irq was raised
from a device; it should also be updated when an interrupt is cleared.
Signed-off-by: Beniamino Galvani
---
hw/intc/allwinner-a10-pic.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/intc/allwinner-a10-pic.c b/hw
Signed-off-by: Beniamino Galvani
---
hw/net/allwinner_emac.c |4 ++--
include/hw/net/allwinner_emac.h |1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/net/allwinner_emac.c b/hw/net/allwinner_emac.c
index 469f2f0..91931ac 100644
--- a/hw/net/allwinner_emac.c
The model was generating interrupts for all enabled timers after the
expiration of one of them. Avoid this by passing to the timer callback
function a structure containing the index of the expired timer.
Signed-off-by: Beniamino Galvani
---
hw/timer/allwinner-a10-pit.c | 30
On Mon, Mar 03, 2014 at 09:56:07PM +1000, Peter Crosthwaite wrote:
> On Mon, Mar 3, 2014 at 12:06 AM, Beniamino Galvani
> wrote:
> > The value of pending register was updated only when an irq was raised
> > from a device; it should also be updated when an interrupt is cleared.
On Mon, Mar 03, 2014 at 09:16:13PM +1000, Peter Crosthwaite wrote:
> On Mon, Mar 3, 2014 at 12:06 AM, Beniamino Galvani
> wrote:
> > This patch implements proper updating of the vector register which
> > should hold, according to the A10 user manual, the vector address for
On Mon, Mar 03, 2014 at 09:08:27PM +1000, Peter Crosthwaite wrote:
> On Mon, Mar 3, 2014 at 12:06 AM, Beniamino Galvani
> wrote:
> > The model was generating interrupts for all enabled timers after the
> > expiration of one of them. Avoid this by passing to the timer callb
On Mon, Mar 03, 2014 at 08:57:33PM +1000, Peter Crosthwaite wrote:
> On Mon, Mar 3, 2014 at 12:06 AM, Beniamino Galvani
> wrote:
> > This implements the prescaler and source fields of the timer control
> > register as described in the A10 user manual.
> >
> > Si
On Thu, Jan 23, 2014 at 11:04:32PM +1000, Peter Crosthwaite wrote:
> On Mon, Jan 20, 2014 at 9:25 AM, Beniamino Galvani
> wrote:
> > This patch adds support for the Fast Ethernet MAC found on Allwinner
> > SoCs, together with a basic emulation of Realtek RTL8201CP PHY.
> &g
On Sun, Jan 26, 2014 at 12:42:59AM +0100, Andreas Färber wrote:
> Am 20.01.2014 00:25, schrieb Beniamino Galvani:
> > Signed-off-by: Beniamino Galvani
> > ---
> > hw/arm/allwinner-a10.c | 16
> > hw/arm/cubieboard.c|7
This patch adds support for the Fast Ethernet MAC found on Allwinner
SoCs, together with a basic emulation of Realtek RTL8201CP PHY.
Since there is no public documentation of the Allwinner controller, the
implementation is based on Linux kernel driver.
Signed-off-by: Beniamino Galvani
Call qemu_flush_queued_packets() when rx becomes possible
* Always create EMAC instance in SoC
* Use uint8 arrays for fifos
* Minor cleanups
Beniamino Galvani (3):
util/fifo8: implement push/pop of multiple bytes
hw/net: add support for Allwinner EMAC Fast Ethernet controller
hw
function fifo8_pop_buf() can be used instead to pop multiple bytes
from the fifo, returning a pointer to the backing buffer.
Signed-off-by: Beniamino Galvani
---
include/qemu/fifo8.h | 43 +++
util/fifo8.c | 44
Signed-off-by: Beniamino Galvani
---
hw/arm/allwinner-a10.c | 16
hw/arm/cubieboard.c| 11 +--
include/hw/arm/allwinner-a10.h |3 +++
3 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10
On Tue, Jan 28, 2014 at 10:04:09AM +1000, Peter Crosthwaite wrote:
> On Tue, Jan 28, 2014 at 4:32 AM, Peter Maydell
> wrote:
> > On 26 January 2014 21:39, Beniamino Galvani wrote:
> >> In some circumstances it is useful to be able to push the entire
> >> content
On Tue, Jan 28, 2014 at 10:43:28AM +, Peter Maydell wrote:
> On 28 January 2014 00:04, Peter Crosthwaite
> wrote:
> > On Tue, Jan 28, 2014 at 4:32 AM, Peter Maydell
> > wrote:
> >>> void fifo8_reset(Fifo8 *fifo)
> >>> {
> >>> fifo->num = 0;
> >>> +fifo->head = 0;
> >>
> >> This is
e EMAC instance in SoC
* Use uint8 arrays for fifos
* Minor cleanups
Beniamino Galvani (4):
util/fifo8: implement push/pop of multiple bytes
util/fifo8: clear fifo head upon reset
hw/net: add support for Allwinner EMAC Fast Ethernet controller
hw/arm/allwinner-a10: initialize EMAC
check if a multi-byte operation can be performed.
Signed-off-by: Beniamino Galvani
---
include/qemu/fifo8.h | 61 ++
util/fifo8.c | 46 +
2 files changed, 107 insertions(+)
diff --git a/include/qemu
Signed-off-by: Beniamino Galvani
Reviewed-by: Peter Crosthwaite
Reviewed-by: Peter Maydell
---
hw/arm/allwinner-a10.c | 16
hw/arm/cubieboard.c| 11 +--
include/hw/arm/allwinner-a10.h |3 +++
3 files changed, 28 insertions(+), 2 deletions
This patch adds support for the Fast Ethernet MAC found on Allwinner
SoCs, together with a basic emulation of Realtek RTL8201CP PHY.
Since there is no public documentation of the Allwinner controller, the
implementation is based on Linux kernel driver.
Signed-off-by: Beniamino Galvani
Reviewed
To improve the predictability of fifo8_pop_buf(), the fifo head is set
to start of data buffer upon a reset so that the first call to the
function will be able to retrieve all data in the fifo.
Signed-off-by: Beniamino Galvani
---
util/fifo8.c |1 +
1 file changed, 1 insertion(+)
diff
different bit width variants.
>
> Signed-off-by: Peter Crosthwaite
Reviewed-by: Beniamino Galvani
nx_spi.c | 4 +-
> hw/ssi/xilinx_spips.c | 4 +-
> include/qemu/fifo.h | 33 ++---
> util/fifo.c | 121
> +---
> 6 files changed, 128 insertions(+), 44 deletions(-)
Looks good to me,
Reviewed-by: Beniamino Galvani
quot; fmt , ## __VA_ARGS__); } while (0)
> #define BADF(fmt, ...) \
> do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__); exit(1);} while
> (0)
> #else
> --
> 1.9.2.1.g06c4abd
>
Reviewed-by: Beniamino Galvani
t; hw/ssi/pl022.c | 101
> -
> 1 file changed, 42 insertions(+), 59 deletions(-)
Reviewed-by: Beniamino Galvani
.
Signed-off-by: Beniamino Galvani
Reviewed-by: Peter Crosthwaite
---
hw/intc/allwinner-a10-pic.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c
index 407d563..00f3c11 100644
--- a/hw/intc/allwinner-a10
Convert the interrupt generation logic to the use of level triggered
interrupts.
Signed-off-by: Beniamino Galvani
---
hw/timer/allwinner-a10-pit.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c
)
v2: Address comments from Li Guang:
* make pic vector register read-only
* allow writing to pic pending register
Beniamino Galvani (7):
allwinner-a10-pic: set vector address when an interrupt is pending
allwinner-a10-pic: fix behaviour of pending register
allwinner-a10-pit:
The pending register is read-only and the value returned upon a read
reflects the state of irq input pins (interrupts are level triggered).
This patch implements such behaviour.
Signed-off-by: Beniamino Galvani
---
hw/intc/allwinner-a10-pic.c |8 +++-
1 file changed, 7 insertions(+), 1
The model was generating interrupts for all enabled timers after the
expiration of one of them. Avoid this by passing explicitly the timer
index to the callback function.
Signed-off-by: Beniamino Galvani
---
hw/timer/allwinner-a10-pit.c | 25 ++---
include/hw/timer
The irq line status must be updated after writes to the INT_CTL and
INT_STA registers.
Signed-off-by: Beniamino Galvani
Reviewed-by: Peter Crosthwaite
---
hw/net/allwinner_emac.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/net/allwinner_emac.c b/hw/net/allwinner_emac.c
index
This implements the prescaler and source fields of the timer control
register as described in the A10 user manual.
Signed-off-by: Beniamino Galvani
---
hw/timer/allwinner-a10-pit.c | 30 +-
include/hw/timer/allwinner-a10-pit.h |8
2 files
Signed-off-by: Beniamino Galvani
---
hw/net/allwinner_emac.c |4 ++--
include/hw/net/allwinner_emac.h |1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/net/allwinner_emac.c b/hw/net/allwinner_emac.c
index 469f2f0..91931ac 100644
--- a/hw/net/allwinner_emac.c
On Mon, Mar 17, 2014 at 11:27:01AM +1000, Peter Crosthwaite wrote:
> On Sat, Mar 15, 2014 at 11:01 PM, Beniamino Galvani
> wrote:
> > This implements the prescaler and source fields of the timer control
> > register as described in the A10 user manual.
> >
> > Si
Convert the interrupt generation logic to the use of level triggered
interrupts.
Signed-off-by: Beniamino Galvani
Reviewed-by: Peter Crosthwaite
---
hw/timer/allwinner-a10-pit.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/hw/timer/allwinner-a10-pit.c b
The irq line status must be updated after writes to the INT_CTL and
INT_STA registers.
Signed-off-by: Beniamino Galvani
Reviewed-by: Peter Crosthwaite
---
hw/net/allwinner_emac.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/net/allwinner_emac.c b/hw/net/allwinner_emac.c
index
Signed-off-by: Beniamino Galvani
Reviewed-by: Peter Crosthwaite
---
hw/net/allwinner_emac.c |4 ++--
include/hw/net/allwinner_emac.h |1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/net/allwinner_emac.c b/hw/net/allwinner_emac.c
index 469f2f0..91931ac
The pending register is read-only and the value returned upon a read
reflects the state of irq input pins (interrupts are level triggered).
This patch implements such behaviour.
Signed-off-by: Beniamino Galvani
Reviewed-by: Li Guang
Reviewed-by: Peter Crosthwaite
---
hw/intc/allwinner-a10
.
Signed-off-by: Beniamino Galvani
Reviewed-by: Peter Crosthwaite
Reviewed-by: Li Guang
---
hw/intc/allwinner-a10-pic.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c
index 407d563..00f3c11 100644
--- a/hw
ng to pic pending register
Beniamino Galvani (7):
allwinner-a10-pic: set vector address when an interrupt is pending
allwinner-a10-pic: fix behaviour of pending register
allwinner-a10-pit: avoid generation of spurious interrupts
allwinner-a10-pit: use level triggered interrupts
allwinne
The model was generating interrupts for all enabled timers after the
expiration of one of them. Avoid this by passing explicitly the timer
index to the callback function.
Signed-off-by: Beniamino Galvani
Reviewed-by: Li Guang
Reviewed-by: Peter Crosthwaite
---
hw/timer/allwinner-a10-pit.c
This implements the prescaler and source fields of the timer control
register. The source for each timer can be selected among 4 clock
inputs whose frequencies are set through model properties.
Signed-off-by: Beniamino Galvani
---
hw/arm/cubieboard.c | 13 ++
hw/timer
On Sat, Oct 03, 2015 at 02:31:08PM -0700, Peter Crosthwaite wrote:
> QEMU cubieboard has no usable storage media, but the real hardware
> does have AHCI sata. I added sysbus-ahci at the right place but turns
> out the SATA controller has some custom power/clock (not really
> sure??) registers speci
On Sun, Oct 04, 2015 at 02:11:35PM -0700, Guenter Roeck wrote:
> What is your qemu command line ?
qemu-system-arm \
-M cubieboard \
-kernel ../linux/zImage-dtb \
-serial stdio \
-append "console=ttyS0 rw root=/dev/nfs nfsroot=10.0.0.1:/nfs,v3
ip=10.
On Mon, Oct 05, 2015 at 11:13:33AM -0400, John Snow wrote:
> I'm looking into the cubieboard now. Is our emulation based on any
> particular model? (1-4?)
The first model, the one with Allwinner A10.
> I'm trying to see if I can find anything that resembles a spec to see
> what kind of registers
On Sun, Oct 11, 2015 at 09:21:32AM -0700, Peter Crosthwaite wrote:
> Hi John and Beniamino,
>
> This patch series adds bear-minimum Allwinner SATA support.
Hi Peter,
can you suggest a qemu command line to test this?
Beniamino
On Sun, Oct 11, 2015 at 09:21:35AM -0700, Peter Crosthwaite wrote:
> --- a/hw/ide/ahci.c
> +++ b/hw/ide/ahci.c
> @@ -1692,9 +1692,107 @@ static const TypeInfo sysbus_ahci_info = {
> .class_init= sysbus_ahci_class_init,
> };
>
> +#define ALLWINNER_AHCI_MMIO_OFF 0x80
> +#define ALLWINNER
On Fri, Sep 18, 2015 at 03:29:49PM +0200, Markus Armbruster wrote:
> E-mail to our maintainer for Allwinner-a10 Li Guang
> bounces. Need a new one. Since you've done
> substantial work on it relatively recently, you seem to be the obvious
> victim. Would you be willing to serve?
Hi Markus,
if
Change the maintainer for Allwinner A10 to myself as Li Guang's mail
address bounces. While at it, extend the file pattern for the entry to
include allwinner_emac.[ch].
Signed-off-by: Beniamino Galvani
---
MAINTAINERS | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --
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