Thanks for the effort cleaning up the cpu-exec file. This looks good to
me. I'll add it again, in the next TriCore patchset.
Reviewed-by: Bastian Koppelmann
On 09/13/2014 05:45 PM, Richard Henderson wrote:
It can go back in when it actually does something.
Cc: Bastian Koppelmann
Signe
Every QEMU_ARCH is now in (1 << n) notation, instead of a mixture of decimal
and hexadecimal.
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- As Michael suggested it is now in (1 << n) notation.
include/sysemu/arch_init.h | 32
1 f
Hi guys,
here is the next round of TriCore patches. The first patch addresses a clang
issue mentioned by Peter Maydell and
some bugfixes. And the other four add instructions of the ABS, ABSB, B, BIT and
BO opcode format.
Thanks,
Bastian
Bastian Koppelmann (5):
target-tricore: Cleanup and
: save_context_lower now saves a[11] instead of PSW.
Fix: MASK_OP_ABSB_BPOS starting at wrong offset.
Signed-off-by: Bastian Koppelmann
---
target-tricore/op_helper.c | 47 ++--
target-tricore/tricore-opcodes.h | 2 +-
2 files changed, 22 insertions(+), 27 deletions
Add instructions of BIT opcode format.
Add microcode generator functions gen_bit_1/2op to do 1/2 bit operations on the
last bit.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 349 +
1 file changed, 349 insertions(+)
diff --git a
Add instructions of ABS, ABSB opcode format.
Add microcode generator functions for ld/st of two 32bit reg as one 64bit value.
Add microcode generator functions for ldmst and swap.
Add helper ldlcx, lducx, stlcx and stucx.
Signed-off-by: Bastian Koppelmann
---
target-tricore/helper.h| 4
Add instructions of B opcode format.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 3ec5ca7..871c3cd 100644
--- a/target-tricore
Add instructions of BO opcode format.
Add microcode generator functions gen_swap, gen_ldmst.
Add helper for loading/storing byte, halfword, upper halfword word, dword in
circular and bit reverse addr mode
Add sign extended bitmask for BO_OFF10 field.
Signed-off-by: Bastian Koppelmann
On 09/28/2014 06:22 AM, Richard Henderson wrote:
+case OPC2_32_BIT_XNOR_T:
+gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
+pos1, pos2, &tcg_gen_xor_tl);
tcg_gen_eqv_tl
I often don't use the optimal tcg-frontend operation, since the
documentation I mo
: save_context_lower now saves a[11] instead of PSW.
Fix: MASK_OP_ABSB_BPOS starting at wrong offset.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/op_helper.c | 47 ++--
target-tricore/tricore-opcodes.h | 2 +-
2 files changed
Add instructions of B opcode format.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index fc89a43..830bcd0
Add instructions of ABS, ABSB opcode format.
Add microcode generator functions for ld/st of two 32bit reg as one 64bit value.
Add microcode generator functions for ldmst and swap.
Add helper ldlcx, lducx, stlcx and stucx.
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- Fix whitespa
Add instructions of BIT opcode format.
Add microcode generator functions gen_bit_1/2op to do 1/2 bit operations on the
last bit.
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- gen_bit_2op: Now uses deposit and two shifts.
- gen_bit_1op: Now masks output instead of inputs
Add instructions of BO opcode format.
Add microcode generator functions gen_swap, gen_ldmst.
Add helper for circular and bit reverse addr mode calculation.
Add sign extended bitmask for BO_OFF10 field.
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- Replace helper for every
ery ld/st_bitreverse/circular instruction with a
general helper + tcg-op.
Bastian Koppelmann (5):
target-tricore: Cleanup and Bugfixes
target-tricore: Add instructions of ABS, ABSB opcode format
target-tricore: Add instructions of B opcode format
target-tricore: Add instructions of BIT opc
On 08/08/2014 03:28 AM, Richard Henderson wrote:
On 08/07/2014 04:34 AM, Bastian Koppelmann wrote:
+/* PSW flag cache for faster execution
+ if flag != 0 then flag is set. Else flag is not set.
+*/
+target_ulong PSW_USB_C;
+target_ulong PSW_USB_V;
+target_ulong
Add instructions of SRR opcode format.
Add helper for add/sub_ssov.
Signed-off-by: Bastian Koppelmann
---
v4 -> v5:
- gen_sub_d now saves result of substraction into tcg temp to handle ret =
r1 cases.
- gen_mul_i32s now calculates V, SV bits in bit 31.
- SSOV makro now compute
Add tcg and cpu model initialization.
Add gen_intermediate_code function.
Activate target in configure and add softmmu config.
Signed-off-by: Bastian Koppelmann
---
v4 -> v5:
- gen_intermediate_code_internal: Move calculation of next_pc after the ifs
for singlestep and long tbs.
config
Add instructions of SC opcode format.
Add helper for begin interrupt service routine.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/helper.h| 1 +
target-tricore/op_helper.c | 59 ++
target-tricore
Add masks and opcodes for decoding TriCore instructions.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c |1 +
target-tricore/tricore-opcodes.h | 1406 ++
2 files changed, 1407 insertions(+)
create mode 100644 target-tricore
Add instructions of SLR, SSRO and SRO opcode format.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 121 +
1 file changed, 121 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore
Add instructions of SB opcode format.
Add helper call/ret.
Add micro-op generator functions for branches.
Add makro to generate helper functions.
Signed-off-by: Bastian Koppelmann
---
v4 -> v5:
- Change int cond to TCGCond in functions gen_branch_cond, gen_branch_co
Add instructions of SRC opcode format.
Add micro-op generator functions for add, conditional add/sub and shi/shai.
Signed-off-by: Bastian Koppelmann
---
v4 -> v5:
- gen_shaci: Change case of shift_count == 32 to shift_count == -32 and add
the clear of V bit.
- gen_shaci: Move creat
Add TriCore target stubs, and QOM cpu.
Signed-off-by: Bastian Koppelmann
---
v4 -> v5:
- Change documentation of S, SV bits to use bit 31.
- psw_read/_write now uses only bit 31 of S, SV bits.
arch_init.c | 2 +
cpu-exec.c| 11 +-
cpu
Add instructions of SBR opcode format.
Add gen_loop micro-op generator function.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 66 +-
1 file changed, 65 insertions(+), 1 deletion(-)
diff --git a
Add instructions of SBC and SBRN opcode format.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 36
1 file changed, 36 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
Add instructions of SSRS and SLRO opcode format.
Add micro-op generator functions for offset loads.
Signed-off-by: Bastian Koppelmann
---
v4 -> v5:
- decode_16Bit_opc: Add if to handle ADDSC.A opcode being 6 bit instead of
7 bit long
target-tricore/translate.c |
Add instructions of SSR opcode format.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 50 ++
1 file changed, 50 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
Add basic board to allow systemmode emulation
Signed-off-by: Bastian Koppelmann
---
hw/tricore/Makefile.objs | 1 +
hw/tricore/tricore_testboard.c | 129 +
include/hw/tricore/tricore.h | 54 +
3 files changed, 184 insertions
Add instructions of SR opcode format.
Add micro-op generator functions for saturate.
Add helper return from exception (rfe).
Signed-off-by: Bastian Koppelmann
---
v4 -> v5:
- Switched sat_neg and arg in first movcond in function gen_saturate.
- SR_NOT: Remove if checking OP2.
tar
Add basic softmmu support for TriCore
Signed-off-by: Bastian Koppelmann
---
target-tricore/helper.c| 54 +-
target-tricore/op_helper.c | 33 +++-
2 files changed, 85 insertions(+), 2 deletions(-)
diff --git a/target
diate_code_internal: Add gen_goto_tb so qemu finds new tb on
singlestep and after long tbs without branch.
- Switched sat_neg and arg in first movcond in function gen_saturate.
- SR_NOT: Remove if checking OP2.
Bastian Koppelmann (15):
target-tricore: Add target stubs and qom-cpu
target
/
12: https://patchwork.ozlabs.org/patch/379595/
13: https://patchwork.ozlabs.org/patch/379586/
14: https://patchwork.ozlabs.org/patch/379590/
15: https://patchwork.ozlabs.org/patch/379599/
Thanks,
Bastian
On 08/13/2014 01:07 PM, Bastian Koppelmann wrote:
Hi,
my aim is to add
Hi Andreas,
On 08/20/2014 02:17 PM, Andreas Färber wrote:
Hi,
Am 13.08.2014 14:07, schrieb Bastian Koppelmann:
arch_init.c |2 +
configure |5 +
cpu-exec.c | 11 +-
cpus.c
On 08/21/2014 09:48 PM, Richard Henderson wrote:
On 08/13/2014 05:07 AM, Bastian Koppelmann wrote:
+/* SR-format */
+case OPCM_16_SR_SYSTEM:
+decode_sr_system(env, ctx);
+ break;
+case OPCM_16_SR_ACCU:
+decode_sr_accu(env, ctx);
+ break;
Formatting is
g blanks.
- get_physical_address: Add PAGE_EXEC permission.
- gen_shaci: Add calculation of PSW.C to shift_count = -32 case.
- gen_intermediate_code_internal: Replace gen_goto_tb with setting of
next_pc and exit_tb(0).
- SBC/SBR_JEQ: Negate condition.
- Formating fixes.
Bastian Koppel
Add TriCore target stubs, and QOM cpu, and Maintainer
Signed-off-by: Bastian Koppelmann
---
v5 -> v6:
- Add myself to MAINTAINERS
MAINTAINERS | 6 +
arch_init.c | 2 +
cpu-exec.c| 11 +-
cpus.c|
Add masks and opcodes for decoding TriCore instructions.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c |1 +
target-tricore/tricore-opcodes.h | 1406 ++
2 files changed, 1407 insertions(+)
create
Add tcg and cpu model initialization.
Add gen_intermediate_code function.
Activate target in configure and add softmmu config.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
configure | 5 ++
default-configs/tricore-softmmu.mak | 3 +
target
Add basic softmmu support for TriCore
Signed-off-by: Bastian Koppelmann
---
v5 -> v6:
- get_physical_address: Add PAGE_EXEC permission.
target-tricore/helper.c| 54 +-
target-tricore/op_helper.c | 33 +++-
2 fi
Add basic board to allow systemmode emulation
Signed-off-by: Bastian Koppelmann
---
v5 -> v6:
- tricore_testboard: Fix machine name containing blanks.
hw/tricore/Makefile.objs | 1 +
hw/tricore/tricore_testboard.c | 129 +
include/hw/tric
Add instructions of SRC opcode format.
Add micro-op generator functions for add, conditional add/sub and shi/shai.
Signed-off-by: Bastian Koppelmann
---
v5 -> v6:
- gen_shaci: Add calculation of PSW.C to shift_count = -32 case.
- Remove useless parenthesis.
target-tricore/helpe
Add instructions of SBC and SBRN opcode format.
Signed-off-by: Bastian Koppelmann
---
v5 -> v6:
- SBC_JEQ: Negate condition.
target-tricore/translate.c | 36
1 file changed, 36 insertions(+)
diff --git a/target-tricore/translate.c b/target-tric
Add instructions of SB opcode format.
Add helper call/ret.
Add micro-op generator functions for branches.
Add makro to generate helper functions.
Signed-off-by: Bastian Koppelmann
---
v5 -> v6:
- gen_intermediate_code_internal: Replace gen_goto_tb with setting of
next_pc and exit_t
Add instructions of SSRS and SLRO opcode format.
Add micro-op generator functions for offset loads.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 59 ++
1 file changed, 59 insertions(+)
diff --git
Add instructions of SRR opcode format.
Add helper for add/sub_ssov.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/helper.h| 4 ++
target-tricore/op_helper.c | 43
target-tricore/translate.c | 164
Add instructions of SR opcode format.
Add micro-op generator functions for saturate.
Add helper return from exception (rfe).
Signed-off-by: Bastian Koppelmann
---
v5 -> v6:
- Fix formating.
target-tricore/helper.h| 1 +
target-tricore/op_helper.c | 52 +
tar
Add instructions of SSR opcode format.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 50 ++
1 file changed, 50 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
Add instructions of SLR, SSRO and SRO opcode format.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 121 +
1 file changed, 121 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore
Add instructions of SC opcode format.
Add helper for begin interrupt service routine.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/helper.h| 1 +
target-tricore/op_helper.c | 59 ++
target-tricore
Add instructions of SBR opcode format.
Add gen_loop micro-op generator function.
Signed-off-by: Bastian Koppelmann
---
v5 -> v6:
- SBR_JEQ: Negate condition.
target-tricore/translate.c | 66 +-
1 file changed, 65 insertions(+), 1 delet
: save_context_lower now saves a[11] instead of PSW.
Fix: MASK_OP_ABSB_BPOS starting at wrong offset.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/op_helper.c | 47 ++--
target-tricore/tricore-opcodes.h | 2 +-
2 files changed
Add instructions of ABS, ABSB opcode format.
Add microcode generator functions for ld/st of two 32bit reg as one 64bit value.
Add microcode generator functions for ldmst and swap.
Add helper ldlcx, lducx, stlcx and stucx.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
mal conditionals instead of preprocessor.
- Add microcode generator functions gen_st/ld_preincr, which write back the
address after the memory access.
- ST/LD_PREINC insn now use gen_st/ld_preincr or write back the address
after
after the memory access.
Bastian Koppelmann
Add instructions of B opcode format.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index fc89a43..830bcd0
Add instructions of BIT opcode format.
Add microcode generator functions gen_bit_1/2op to do 1/2 bit operations on the
last bit.
Signed-off-by: Bastian Koppelmann
---
v2 -> v3:
- OR_NOR_T, AND_NOR_T: Now uses normal conditionals instead of preprocessor.
target-tricore/translate.c |
BO_OFF10 field.
Signed-off-by: Bastian Koppelmann
---
v2 -> v3:
- Add microcode generator functions gen_st/ld_preincr, which write back the
address after the memory access.
- ST/LD_PREINC insn now use gen_st/ld_preincr or write back the address
after
after the memory acc
Peter, how do I go on from here? Do you apply the patches or do I send a
pull-request?
Thanks,
Bastian
On 10/13/2014 05:26 PM, Bastian Koppelmann wrote:
Hi guys,
here is the next round of TriCore patches. The first patch addresses a clang
issue mentioned by Peter Maydell and
some bugfixes
Add instructions of BIT opcode format.
Add microcode generator functions gen_bit_1/2op to do 1/2 bit operations on the
last bit.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 312 +
1 file changed
Bastian Koppelmann (5):
target-tricore: Cleanup and Bugfixes
target-tricore: Add instructions of ABS, ABSB opcode format
target-tricore: Add instructions of B opcode format
target-tricore: Add instructions of BIT opcode format
target-tricore
: save_context_lower now saves a[11] instead of PSW.
Fix: MASK_OP_ABSB_BPOS starting at wrong offset.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/op_helper.c | 47 ++--
target-tricore/tricore-opcodes.h | 2 +-
2 files changed
Add instructions of ABS, ABSB opcode format.
Add microcode generator functions for ld/st of two 32bit reg as one 64bit value.
Add microcode generator functions for ldmst and swap.
Add helper ldlcx, lducx, stlcx and stucx.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
Add instructions of B opcode format.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index fc89a43..830bcd0
BO_OFF10 field.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/helper.h | 3 +
target-tricore/op_helper.c | 36 +++
target-tricore/translate.c | 663 +++
target-tricore/tricore-opcodes.h | 2 +
4 files
Add instructions of BRR opcode format.
Add MASK_OP_BRR_DISP15_SEXT.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 89 +++-
target-tricore/tricore-opcodes.h | 1 +
2 files changed, 88 insertions(+), 2 deletions(-)
diff --git a
Add instructions of BRC opcode format.
Fixed OP2_BRC_JGE -> OP2_32_BRC_JGE.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 53 +++-
target-tricore/tricore-opcodes.h | 6 +++--
2 files changed, 56 insertions(+), 3 deletions(-)
d
Add instructions of BOL opcode format.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 48
target-tricore/tricore-opcodes.h | 4 +++-
2 files changed, 51 insertions(+), 1 deletion(-)
diff --git a/target-tricore/translate.c b
.
* gen_sh_cond, which shifts left a reg by one and writes the result of cond
into the lsb.
* gen_accumulating_cond, which ands/ors/xors the result of cond of the lsbs
with the lsb of the result.
* gen_eqany_bi/hi, which checks ever byte/hword on equality.
Signed-off-by: Bastian
Add instructions of BRN opcode format.
Add MASK_OP_BRN_DISP15_SEXT.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 30 ++
target-tricore/tricore-opcodes.h | 1 +
2 files changed, 31 insertions(+)
diff --git a/target-tricore/translate.c b
Hi,
this is the next round of TriCore patches, which adds BOL, BRC, BRN, BRR and RC
instructions.
I'm not quite sure about the softfreeze. Since this patch has not been
announced after
the softfreeze, do I have to wait with a pull-request to after the release of
2.2?
thanks,
Bastian
Ba
Geez, thanks. I wonder how I missed that.
Reviewed-by: Bastian Koppelmann
On 10/30/2014 02:03 AM, zhanghailiang wrote:
We reference the return value of cpu before checking whether it is NULL,
The checking code is after that which violates code style.
It makes no difference if the cpu is NULL
for high in case shift <= 0, since deposit
handles that.
Bastian Koppelmann (5):
target-tricore: Add instructions of BOL opcode format
target-tricore: Add instructions of BRC opcode format
target-tricore: Add instructions of BRN opcode format
target-tricore: Add instructions of BRR opcode f
Add instructions of BOL opcode format.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 48
target-tricore/tricore-opcodes.h | 4 +++-
2 files changed, 51 insertions(+), 1 deletion(-)
diff --git a
Add instructions of BRN opcode format.
Add MASK_OP_BRN_DISP15_SEXT.
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- OPC2_32_BRN_JNZ_T now uses gen_branch_condi.
target-tricore/translate.c | 26 ++
target-tricore/tricore-opcodes.h | 1 +
2 files changed,
Add instructions of BRR opcode format.
Add MASK_OP_BRR_DISP15_SEXT.
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- OPC2_32_BRR_LOOPU now uses gen_goto_tb.
- else of OPC2_32_BRR_LOOPU now has comment identifying it.
target-tricore/translate.c |
.
* gen_sh_cond, which shifts left a reg by one and writes the result of cond
into the lsb.
* gen_accumulating_cond, which ands/ors/xors the result of cond of the lsbs
with the lsb of the result.
* gen_eqany_bi/hi, which checks ever byte/hword on equality.
Signed-off-by: Bastian
Add instructions of BRC opcode format.
Fixed OP2_BRC_JGE -> OP2_32_BRC_JGE
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 53 +++-
target-tricore/tricore-opcodes.h | 6 +++--
2 files changed,
Hi Peter,
On 08/29/2014 03:30 PM, Peter Maydell wrote:
+
+dinfo = drive_get(IF_PFLASH, 0, 0);
+if (!pflash_cfi01_register(TRICORE_FLASH_ADDR, NULL,
+ "tricore_testboard.flash",
+ TRICORE_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL,
+
Add basic board to allow systemmode emulation
Signed-off-by: Bastian Koppelmann
---
v6 -> v7:
- TRICORECPU -> TriCoreCPU.
- CPUTRICOREState -> CPUTriCoreState.
- tricore_testboard.c: Change Licence to GPL v2.
- fprintf(stderr, ..) -> error_report(..).
- trico
Add TriCore target stubs, and QOM cpu, and Maintainer
Signed-off-by: Bastian Koppelmann
---
v6 -> v7:
- TRICORECPU -> TriCoreCPU.
- TRICORECPUClass -> TriCoreCPUClass.
- CPUTRICOREState -> CPUTriCoreState.
- TRICORECPUInfo: Add terminator.
- TRICORECPUInfo ->
Add masks and opcodes for decoding TriCore instructions.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c |1 +
target-tricore/tricore-opcodes.h | 1406 ++
2 files changed, 1407 insertions(+)
create
e_boot_info: Remove unused fields.
- tricore_testboard.c: Remove flash drive.
- tricore_testboard.c: Is not default anymore, change desc.
- configure: Remove empty disas case. Remove target_phys_bits=32.
- tricore-softmmu.mak: Remove pci, SMC91C111 and PFLASH_CFI01.
Bastian Koppelmann (
Add instructions of SBC and SBRN opcode format.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 36
1 file changed, 36 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
Add instructions of SRC opcode format.
Add micro-op generator functions for add, conditional add/sub and shi/shai.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/helper.h| 16 +++
target-tricore/translate.c | 251
Add basic softmmu support for TriCore
Signed-off-by: Bastian Koppelmann
---
v6 -> v7:
- TRICORECPU -> TriCoreCPU.
- CPUTRICOREState -> CPUTriCoreState.
target-tricore/helper.c| 54 +-
target-tricore/op_help
Add tcg and cpu model initialization.
Add gen_intermediate_code function.
Activate target in configure and add softmmu config.
Signed-off-by: Bastian Koppelmann
---
v6 -> v7:
- configure: Remove empty disas case. Remove target_phys_bits=32.
- tricore-softmmu.mak: Remove pci, SMC91C
Add instructions of SB opcode format.
Add helper call/ret.
Add micro-op generator functions for branches.
Add makro to generate helper functions.
Signed-off-by: Bastian Koppelmann
---
v6 -> v7:
- CPUTRICOREState -> CPUTriCoreState.
target-tricore/helper.h| 3 +
target-t
Add instructions of SSRS and SLRO opcode format.
Add micro-op generator functions for offset loads.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 59 ++
1 file changed, 59 insertions(+)
diff --git
Add instructions of SSR opcode format.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 50 ++
1 file changed, 50 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
Add instructions of SBR opcode format.
Add gen_loop micro-op generator function.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 66 +-
1 file changed, 65 insertions(+), 1 deletion(-)
diff --git a
Add instructions of SLR, SSRO and SRO opcode format.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 121 +
1 file changed, 121 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore
Add instructions of SRR opcode format.
Add helper for add/sub_ssov.
Signed-off-by: Bastian Koppelmann
---
v6 -> v7:
- CPUTRICOREState -> CPUTriCoreState.
target-tricore/helper.h| 4 ++
target-tricore/op_helper.c | 43
target-tricore/translate.c
Add instructions of SR opcode format.
Add micro-op generator functions for saturate.
Add helper return from exception (rfe).
Signed-off-by: Bastian Koppelmann
---
v6 -> v7:
- CPUTRICOREState -> CPUTriCoreState.
target-tricore/helper.h| 1 +
target-tricore/op_helper.c
Add instructions of SC opcode format.
Add helper for begin interrupt service routine.
Signed-off-by: Bastian Koppelmann
---
v6 -> v7:
- CPUTRICOREState -> CPUTriCoreState.
target-tricore/helper.h| 1 +
target-tricore/op_helper.
Hi Peter,
On 09/01/2014 01:48 PM, Peter Maydell wrote:
On 1 September 2014 12:59, Bastian Koppelmann
wrote:
Add basic board to allow systemmode emulation
Signed-off-by: Bastian Koppelmann
---
v6 -> v7:
- TRICORECPU -> TriCoreCPU.
- CPUTRICOREState -> CPUTri
Every QEMU_ARCH is now hexadecimal instead of a mixture of decimal and
hexadecimal.
Signed-off-by: Bastian Koppelmann
---
include/sysemu/arch_init.h | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/include/sysemu/arch_init.h b/include/sysemu
Add instructions of SRC opcode format.
Add helper for sh arithmetic carry.
Add micro-op generator functions for conditional add/sub and shi.
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- helper_shac uses sextract32 for the constant and add len parameter.
- Replace else case w
Add instructions of SC opcode format.
Add helper for begin interrupt service routine.
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- Add save_context_lower. (see patch v2 10/15)
- Remove printfs in helper_bisr.
- Add one decode function for all SC instructions.
target-tric
Add TriCore target stubs, and QOM cpu.
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- Move activation of target patch1->patch4.
- Remove host related in configure.
- Remove host related code in user-exec.
- Remove active_tc struct.
- Change define GPR first, the
Add tcg and cpu model initialization.
Add gen_intermediate_code function.
Activate target in configure and add softmmu config.
Signed-off-by: Bastian Koppelmann
---
v1 -> v2:
- Add next_pc to DisasContext and change pc calculation.
- Remove insn_bytes.
config
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