[PATCH v3 3/7] target/i386: Add PerfMonV2 feature bit

determine the number of available counters for different PMUs. It also denotes the availability of global control and status registers. Add the required CPUID feature word and feature bit to allow guests to make use of the PerfMonV2 features. Signed-off-by: Sandipan Das Signed-off-by: Babu Moger

[PATCH v3 7/7] target/i386: Add support for EPYC-Turin model

RAP Link: https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip Link: https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf Signed-off-by: Babu Moger --- v3: Removed Zhao's Reviewed-by a

[PATCH v3 6/7] target/i386: Expose new feature bits in CPUID 8000_0021_EAX/EBX

-technical-docs/programmer-references/57238.zip Signed-off-by: Babu Moger --- v3: New patch --- target/i386/cpu.c | 11 +-- target/i386/cpu.h | 9 + 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 642e71b636..5bfa07adbf 100644

[PATCH v4 5/5] target/i386: Update EPYC-Genoa for Cache property, perfmon-v2, RAS and SVM feature bits

Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Babu Moger --- target/i386/cpu.c | 78 +++ 1 file changed, 78 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 107ecd2bde..1d241fcd13 100644 --- a/target/i386/

[PATCH v4 2/5] target/i386: Update EPYC-Rome CPU model for Cache property, RAS, SVM feature bits

-off-by: Babu Moger --- target/i386/cpu.c | 73 +++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index a632c8030c..c21b232e75 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2343,6 +2343,60 @@ static

[PATCH v4 3/5] target/i386: Update EPYC-Milan CPU model for Cache property, RAS, SVM feature bits

Signed-off-by: Babu Moger --- target/i386/cpu.c | 73 +++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c21b232e75..4a4e9b81d8 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2505,6 +2505,60

[PATCH v4 4/5] target/i386: Add feature that indicates WRMSR to BASE reg is non-serializing

/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip Signed-off-by: Babu Moger --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4a4e9b81d8..107ecd2bde

[PATCH v4 1/5] target/i386: Update EPYC CPU model for Cache property, RAS, SVM feature bits

Signed-off-by: Babu Moger --- target/i386/cpu.c | 73 +++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 58c96eafea..a632c8030c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2181,6 +2181,60 @@ static

[PATCH v4 0/5] target/i386: Update EPYC CPU models for Cache property, RAS, SVM feature bits

t.babu.mo...@amd.com/ v2: https://lore.kernel.org/kvm/cover.1723068946.git.babu.mo...@amd.com/ v1: https://lore.kernel.org/qemu-devel/cover.1718218999.git.babu.mo...@amd.com/ Babu Moger (5): target/i386: Update EPYC CPU model for Cache property, RAS, SVM feature bits target/i386: Update EPY

[PATCH v5 0/6] target/i386: Update EPYC CPU models for Cache property, RAS, SVM feature and add EPYC-Turin CPU model

ps://lore.kernel.org/kvm/cover.1729807947.git.babu.mo...@amd.com/ v2: https://lore.kernel.org/kvm/cover.1723068946.git.babu.mo...@amd.com/ v1: https://lore.kernel.org/qemu-devel/cover.1718218999.git.babu.mo...@amd.com/ Babu Moger (6): target/i386: Update EPYC CPU model for Cache property, RAS,

[PATCH v5 2/6] target/i386: Update EPYC-Rome CPU model for Cache property, RAS, SVM feature bits

-off-by: Babu Moger Reviewed-by: Maksim Davydov --- target/i386/cpu.c | 73 +++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 94292bfaa2..e2c3c797ed 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c

[PATCH v5 3/6] target/i386: Update EPYC-Milan CPU model for Cache property, RAS, SVM feature bits

Signed-off-by: Babu Moger Reviewed-by: Maksim Davydov --- target/i386/cpu.c | 73 +++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e2c3c797ed..7d18557877 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c

[PATCH v5 6/6] target/i386: Add support for EPYC-Turin model

vulnerable to SRSO at the user-kernel boundary Link: https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip Link: https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf Signed-off-by: Babu Moger

[PATCH v5 1/6] target/i386: Update EPYC CPU model for Cache property, RAS, SVM feature bits

Signed-off-by: Babu Moger Reviewed-by: Maksim Davydov --- target/i386/cpu.c | 73 +++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b5dd60d281..94292bfaa2 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c

[PATCH v5 5/6] target/i386: Update EPYC-Genoa for Cache property, perfmon-v2, RAS and SVM feature bits

Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Babu Moger Reviewed-by: Maksim Davydov --- target/i386/cpu.c | 78 +++ 1 file changed, 78 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 710b862eec..3b6a6

[PATCH v5 4/6] target/i386: Add feature that indicates WRMSR to BASE reg is non-serializing

/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip Signed-off-by: Babu Moger Reviewed-by: Maksim Davydov --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index

[PATCH v6 2/6] target/i386: Update EPYC-Rome CPU model for Cache property, RAS, SVM feature bits

-off-by: Babu Moger Reviewed-by: Maksim Davydov Reviewed-by: Zhao Liu --- target/i386/cpu.c | 73 +++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 7908b90b77..be8dcf9739 100644 --- a/target/i386/cpu.c +++ b

[PATCH v6 4/6] target/i386: Add feature that indicates WRMSR to BASE reg is non-serializing

/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip Signed-off-by: Babu Moger Reviewed-by: Maksim Davydov Reviewed-by: Zhao Liu --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b

[PATCH v6 3/6] target/i386: Update EPYC-Milan CPU model for Cache property, RAS, SVM feature bits

Signed-off-by: Babu Moger Reviewed-by: Maksim Davydov Reviewed-by: Zhao Liu --- target/i386/cpu.c | 73 +++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index be8dcf9739..a5427620d0 100644 --- a/target/i386/cpu.c

[PATCH v6 1/6] target/i386: Update EPYC CPU model for Cache property, RAS, SVM feature bits

Signed-off-by: Babu Moger Reviewed-by: Maksim Davydov Reviewed-by: Zhao Liu --- target/i386/cpu.c | 73 +++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 72ab147e85..7908b90b77 100644 --- a/target/i386/cpu.c

[PATCH v6 5/6] target/i386: Update EPYC-Genoa for Cache property, perfmon-v2, RAS and SVM feature bits

Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Babu Moger Reviewed-by: Maksim Davydov Reviewed-by: Zhao Liu --- target/i386/cpu.c | 78 +++ 1 file changed, 78 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c

[PATCH v6 6/6] target/i386: Add support for EPYC-Turin model

vulnerable to SRSO at the user-kernel boundary Link: https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip Link: https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf Signed-off-by: Babu Moger

[PATCH v6 0/6] target/i386: Update EPYC CPU models for Cache property, RAS, SVM feature and add EPYC-Turin CPU model

bu.mo...@amd.com/ v1: https://lore.kernel.org/qemu-devel/cover.1718218999.git.babu.mo...@amd.com/ Babu Moger (6): target/i386: Update EPYC CPU model for Cache property, RAS, SVM feature bits target/i386: Update EPYC-Rome CPU model for Cache property, RAS, SVM feature bits target/i386: U

[PATCH v7 3/6] target/i386: Update EPYC-Milan CPU model for Cache property, RAS, SVM feature bits

Signed-off-by: Babu Moger Reviewed-by: Maksim Davydov Reviewed-by: Zhao Liu --- target/i386/cpu.c | 73 +++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3f64293ba5..98fad3a2f9 100644 --- a/target/i386/cpu.c

[PATCH v7 6/6] target/i386: Add support for EPYC-Turin model

-overflow-whitepaper.pdf Signed-off-by: Babu Moger Reviewed-by: Zhao Liu --- target/i386/cpu.c | 138 ++ 1 file changed, 138 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 8384ad6eff..247dcdbc34 100644 --- a/target/i386/cpu.c

[PATCH v7 2/6] target/i386: Update EPYC-Rome CPU model for Cache property, RAS, SVM feature bits

-off-by: Babu Moger Reviewed-by: Maksim Davydov Reviewed-by: Zhao Liu --- target/i386/cpu.c | 73 +++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 49d3ae8aac..3f64293ba5 100644 --- a/target/i386/cpu.c +++ b

[PATCH v7 1/6] target/i386: Update EPYC CPU model for Cache property, RAS, SVM feature bits

Signed-off-by: Babu Moger Reviewed-by: Maksim Davydov Reviewed-by: Zhao Liu --- target/i386/cpu.c | 73 +++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6f21d5ed22..49d3ae8aac 100644 --- a/target/i386/cpu.c

[PATCH v7 4/6] target/i386: Add couple of feature bits in CPUID_Fn80000021_EAX

. WRMSR to FS_BASE, GS_BASE and KernelGSbase are non-serializing. Link: https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip Signed-off-by: Babu Moger Reviewed-by: Maksim Davydov Reviewed-by: Zhao Liu --- target/i386/cpu.c | 4 ++-- target/i386

[PATCH v7 5/6] target/i386: Update EPYC-Genoa for Cache property, perfmon-v2, RAS and SVM feature bits

Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Babu Moger Reviewed-by: Maksim Davydov Reviewed-by: Zhao Liu --- target/i386/cpu.c | 78 +++ 1 file changed, 78 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c

[PATCH v7 0/6] target/i386: Update EPYC CPU models for Cache property, RAS, SVM feature and add EPYC-Turin CPU model

m/ v3: https://lore.kernel.org/kvm/cover.1729807947.git.babu.mo...@amd.com/ v2: https://lore.kernel.org/kvm/cover.1723068946.git.babu.mo...@amd.com/ v1: https://lore.kernel.org/qemu-devel/cover.1718218999.git.babu.mo...@amd.com/ Babu Moger (6): target/i386: Update EPYC CPU model for Cache prope

[PATCH v2 2/2] target/i386: Add TSA feature flag verw-clear

: Borislav Petkov (AMD) Signed-off-by: Borislav Petkov (AMD) Signed-off-by: Babu Moger --- v2: Split the patches into two. Not adding the feature bit in CPU model now. Users can add the feature bits by using the option "-cpu EPYC-Genoa,+verw-clear". v1: https://lore.kernel.org/

[PATCH v2 1/2] target/i386: Add TSA attack variants TSA-SQ and TSA-L1

: Babu Moger --- v2: Split the patches into two. Not adding the feature bit in CPU model now. Users can add the feature bits by using the option "-cpu EPYC-Genoa,+tsa-sq-no,+tsa-l1-no". v1: https://lore.kernel.org/qemu-devel/20250709104956.GAaG5JVO-74EF96hHO@fat_crate.local/ --- t

<    1   2   3   4   5