On Thu, 4 Aug 2022, Mark Cave-Ayland wrote:
On 04/08/2022 00:04, BALATON Zoltan wrote:
On Wed, 3 Aug 2022, Cédric Le Goater wrote:
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405.h | 16 +++
hw/ppc/ppc405_uc.c | 71
On Thu, 4 Aug 2022, Cédric Le Goater wrote:
On 8/4/22 01:31, BALATON Zoltan wrote:
On Wed, 3 Aug 2022, Cédric Le Goater wrote:
Having an explicit I2C model object will help if one day we want to
add I2C devices on the bus.
Same here as with the UIC in previous patch, it's not QOMifying
paths
are always the same so it could resolve an absolute path. Don't know how
it looks buth something like /machine/soc/cpu or similar to get to the cpu
to get the env. This could work as long as we assume we only have one cpu
but these SoC all have. Then no cpu link is needed and could get
On Thu, 4 Aug 2022, Cédric Le Goater wrote:
[ Replying to all ]
On 8/4/22 16:26, BALATON Zoltan wrote:
On Thu, 4 Aug 2022, Cédric Le Goater wrote:
On 8/4/22 14:09, BALATON Zoltan wrote:
On Thu, 4 Aug 2022, Cédric Le Goater wrote:
On 8/4/22 01:36, Daniel Henrique Barboza wrote:
Cedric,
On
On Thu, 4 Aug 2022, Peter Maydell wrote:
On Thu, 4 Aug 2022 at 19:03, BALATON Zoltan wrote:
I was trying to find out how to do it but I don't understand QOM enough to
answer the simple question of how to get the cpu object from QOM. My
guesses are:
object_resolve_path_type(&quo
On Fri, 5 Aug 2022, Cédric Le Goater wrote:
On 8/4/22 21:26, BALATON Zoltan wrote:
On Thu, 4 Aug 2022, Peter Maydell wrote:
On Thu, 4 Aug 2022 at 19:03, BALATON Zoltan wrote:
I was trying to find out how to do it but I don't understand QOM enough
to
answer the simple question of how t
On Fri, 5 Aug 2022, Peter Maydell wrote:
On Fri, 5 Aug 2022 at 13:55, BALATON Zoltan wrote:
I know this is a mess curently but QOM is full of boilerplate code which
is confusing for new people and makes it hard to undestand the code. So
cutting down the boilerplate and making things simpler
On Fri, 5 Aug 2022, Peter Maydell wrote:
On Fri, 5 Aug 2022 at 17:50, BALATON Zoltan wrote:
This also
allows to get the cpu without a link with something like:
PPC4XX_MACHINE(current_machine /* or qdev_get_machine() */)->soc.cpu
...and now you have device code that's making ass
On Fri, 5 Aug 2022, BALATON Zoltan wrote:
On Fri, 5 Aug 2022, Peter Maydell wrote:
On Fri, 5 Aug 2022 at 17:50, BALATON Zoltan wrote:
This also
allows to get the cpu without a link with something like:
PPC4XX_MACHINE(current_machine /* or qdev_get_machine() */)->soc.cpu
...and now you h
6 but
still did not make Coverity happy :-)
Regards,
BALATON Zoltan
Cc: BALATON Zoltan
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc440_uc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 11fdb88c22..31eeffa946 100644
---
On Fri, 5 Aug 2022, BALATON Zoltan wrote:
On Fri, 5 Aug 2022, Peter Maydell wrote:
On Fri, 5 Aug 2022 at 17:50, BALATON Zoltan wrote:
This also
allows to get the cpu without a link with something like:
PPC4XX_MACHINE(current_machine /* or qdev_get_machine() */)->soc.cpu
...and now you h
we have xferlen = count * width it could be used elsewehere where
that product appears for example. At that point I'll see if the type can
be changed too. Until then it's fine as it is now.
Regards,
BALATON Zoltan
On Sat, 6 Aug 2022, Peter Maydell wrote:
On Sat, 6 Aug 2022 at 12:24, BALATON Zoltan wrote:
I may look at it later when Peter's second patch changing
this code lands if there are any cleanups possible
You mean the 2nd patch I sent in that RFC series? I'm not
Yes I mean
t before all the above steps to cut down complexity; even if
this is the final goal the basis should be there first so concentrate on
those now).
But you know better what and how you want to do, I just shared my thoughts
in the hope it might be useful. If not you're free to ignore it.
Regards,
BALATON Zoltan
hine.
Not sure how this works but pc and pseries machines seem to have imply
VIRTIO_VGA so probably that's what you need to add to config MAC_NEWWORLD
or just try qemu-system-ppc64 -machine mac99,via=pmu -cpu G4 which should
already have it due so pseries but may otherwise be equivalent to the one
in qemu-system-ppc.
Regards,
BALATON Zoltan
On Sun, 7 Aug 2022, BALATON Zoltan wrote:
On Sun, 7 Aug 2022, Mark Cave-Ayland wrote:
On 07/08/2022 12:47, Elliot Nunn wrote:
I want to give Mac OS 9 clients access to hardware cursor support, to
improve
responsiveness in absolute-cursor mode.
Would it be acceptable to add a hardware cursor
ne
could check and ajust it so we can only adjust it by wasting some. Take
this into account and check the ppc4xx_sdram_banks() function and 440
machines before changing this.
Regards,
BALATON Zoltan
Thanks,
C.
Changes in v3 :
- New device model Ppc4xxDcrDeviceState
- Removal of
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
We will use this machine as a base to define the ref405ep and possibly
the PPC405 hotfoot board as found in the Linux kernel.
Signed-off-by: Cédric Le Goater
Reviewed-by: BALATON Zoltan
---
hw/ppc/ppc405_boards.c | 31
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Reviewed-by: BALATON Zoltan
---
hw/ppc/ppc405_boards.c | 31 +++
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/hw/ppc
AM_SIZE,
+ &error_fatal);
+memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram);
+
/* Register FPGA */
ref405ep_fpga_init(get_system_memory(), PPC405EP_FPGA_BASE);
or use it everywhere consistently.
Regards,
BALATON Zoltan
/* Register NVRAM */
we separately need to set its size or we could use memory_region_size()
instead?
+
+static void ppc405_soc_class_init(ObjectClass *oc, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(oc);
+
+dc->realize = ppc405_soc_realize;
+dc->user_creatable = false;
May need a
ename != NULL
Is there a problem with indentation in this patch? Does it pass
checkpatch.pl?
Regards,
BALATON Zoltan
+object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", ,
+ &error_abort);
qdev_realize(DEVICE(&ppc405-&g
rror.h"
#include "trace.h"
-static void ppc4xx_reset(void *opaque)
+void ppc4xx_reset(void *opaque)
{
PowerPCCPU *cpu = opaque;
This just calls cpu_reset() and does nothing else. Can't that be
registered directly so this could be kept static to this file? Why do we
need this at all? Isn't the cpu object reset automatically? Why do we need
to register it separately?
Regards,
BALATON Zoltan
= TYPE_PPC4xx_DCR_DEVICE,
+.parent = TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(Ppc4xxDcrDeviceState),
+.class_init = ppc4xx_dcr_class_init,
+.abstract = true,
Oh, it's abstract already. So does it also need user_creatable for an
abstract class then? Maybe you can drop the user_creatable.
Regards,
BALATON Zoltan
+}
+};
+
+DEFINE_TYPES(ppc4xx_types)
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
On 8/8/22 14:16, BALATON Zoltan wrote:
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
Hello,
Here is large series QOM'ifying the PPC405 board. It introduces a new
generic machine and SoC models, converts the current device models to
QOM and popu
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
On 8/8/22 14:43, BALATON Zoltan wrote:
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
It is an initial model to start QOMification of the PPC405 board.
QOM'ified devices will be reintroduced one by one. Start with the
memory regions, which name p
C405EP_CPC0_EPCTL, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
-ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
-ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
+assert(dcr->cpu);
So if you move th
ct_irq(SYS_BUS_DEVICE(&s->gpt), i,
+ qdev_get_gpio_in(s->uic, 19 + i));
Maybe you should have a SysBusDevice *sbd local here and cast only once if
you need it several times. It's also more readable that way.
Regards,
BALATON Zoltan
+}
/*
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
The GPIO controller is currently modeled as a DCR device with a couple
It's the DMA already not the GPIU.
Regards,
BALATON Zoltan
of IRQs.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405.h
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
The GPIO controller is currently modeled as a simple SysBus device
with a unique memory region.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405.h| 21 +++
hw/ppc/ppc405_uc.c | 50 +
TYPE_PPC405_FPGA "ppc405-fpga"
If this is specific to ref405ep maybe it should be named accordingly.
Regards,
BALATON Zoltan
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405FpgaState, PPC405_FPGA);
+struct Ppc405FpgaState {
+SysBusDevice parent_obj;
+
+MemoryRegion iomem;
+
uint8_t reg0;
ui
It's not that it's now explicitly typed as PPCUIC but more that it's now
embedded in soc state instead of dynamically allocated. So Embed UIC in
soc state may be a better patch title.
Regards,
BALATON Zoltan
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
Reviewed-by: Daniel H
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
On 8/8/22 15:17, BALATON Zoltan wrote:
Patch title is wrong. It should be Embed CPU object in SoC as it's not
QOMifies the CPU just moves it from dinamically allocated to embedded.
On Mon, 8 Aug 2022, Cédric Le Goater wrote:
Drop the u
On Mon, 8 Aug 2022, Peter Maydell wrote:
On Mon, 8 Aug 2022 at 18:05, BALATON Zoltan wrote:
But the handler we register here just calls cpu_reset which seems to just
call the reset method of the CPU object. If we have nothing else to do
here do we need to explicitly call cpi_reset like this
On Mon, 8 Aug 2022, BALATON Zoltan wrote:
On Sun, 7 Aug 2022, BALATON Zoltan wrote:
On Sun, 7 Aug 2022, Mark Cave-Ayland wrote:
On 07/08/2022 12:47, Elliot Nunn wrote:
I want to give Mac OS 9 clients access to hardware cursor support, to
improve
responsiveness in absolute-cursor mode.
Would
r_fatal);
Do you need to set an owner while at it? Anyway,
Reviewed-by: BALATON Zoltan
Regards,
BALATON Zoltan
-memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram);
-
/* allocate and load BIOS */
if (machine->firmware) {
MemoryRegion *bios = g_new(Memory
econd bank is a dummy one
(zero size) which is here to match the hard coded number of banks in
ppc405ep_init().
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Reviewed-by: BALATON Zoltan
---
hw/ppc/ppc405.h| 16
hw/ppc/ppc405_boards.c | 23 +++
initializer of the CPU families needing it.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Reviewed-by: BALATON Zoltan
---
hw/ppc/ppc405.h | 2 +-
include/hw/ppc/ppc4xx.h | 5 -
hw/ppc/ppc405_boards.c | 2 +-
hw/ppc/ppc405_uc.c | 40
On Tue, 9 Aug 2022, Cédric Le Goater wrote:
This moves all the code previously done in the ppc405ep_init() routine
under ppc405_soc_realize(). We can also adjust the number of banks now
that we have control on ppc4xx_sdram_init().
Signed-off-by: Cédric Le Goater
Reviewed-by: BALATON Zoltan
frequently so I'd not add unnecessary overhead without a good
reason.)
Otherwise:
Reviewed-by: BALATON Zoltan
Regards,
BALATOn Zoltan
+{
+CPUPPCState *env;
+
+assert(dev->cpu);
+
+env = &dev->cpu->env;
+
+ppc_dcr_register(env, dcrn, dev, dcr_read, dcr_write);
+}
s
hunk belong to an earlier patch? (Have you verified that each step
compiles so it can be bisected?)
Regards,
BALATON Zoltan
#include "exec/memory.h"
#include "hw/sysbus.h"
@@ -40,9 +41,6 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int
nbanks,
p_fpga_realize;
+dc->user_creatable = false;
Comment missing (and I'd drop unnecessary QOM casts) but otherwise:
Reviewed-by: BALATON Zoltan
Regards,
BALATON Zoltan
+dc->reset = ref405ep_fpga_reset;
}
+static const TypeInfo ref405ep_fpga_type = {
+.name = TYPE_R
Since maybe there will be another version, this patch is still misnamed, I
think it's not QOMifying but embeds the cpu in the soc.
Regards,
BALATON Zoltan
On Tue, 9 Aug 2022, Cédric Le Goater wrote:
Drop the use of ppc4xx_init() and duplicate a bit of code related to
clocks in th
h makes it more difficult to access things than it should be. There
should be a way to get a bus without havnig to have a pointer to the
controller or again we need a way to navigate the qom three here.
But this is only a comment not a complaint as I've said above I don't
mind.
Reg
ne in ppc4xx_devs.c and another in ppc440_uc.c) that are slightly
different due to the differences of the memory controllers of later SoCs.
I'm not sure how to clean this up and forgot most of the details about
this.
Regards,
BALATON Zoltan
Signed-off-by: Cédric Le Goater
---
hw/pp
On Tue, 9 Aug 2022, Cédric Le Goater wrote:
Signed-off-by: Cédric Le Goater
Reviewed-by: BALATON Zoltan
---
hw/ppc/ppc4xx_devs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 8a8a87b03b28..c06c20b195cd 100644
--- a/hw
On Tue, 9 Aug 2022, Cédric Le Goater wrote:
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Reviewed-by: BALATON Zoltan
---
hw/ppc/ppc405.h| 3 ++-
hw/ppc/ppc405_uc.c | 26 +-
2 files changed, 15 insertions(+), 14 deletions(-)
diff --git a
On Tue, 9 Aug 2022, Cédric Le Goater wrote:
The check on invalid RAM size is now performed in the SDRAM controller
but not all values will boot a machine. A minimum of 2*16 is required.
2*16 or 16 MiB? The code has the latter which does not match commit
message.
Regards,
BALATON Zoltan
On Wed, 10 Aug 2022, Cédric Le Goater wrote:
On 8/9/22 19:53, BALATON Zoltan wrote:
On Tue, 9 Aug 2022, Cédric Le Goater wrote:
This is an initial change of the SDRAM controller preserving the
compatibility with the current modeling. Further cleanup will be
possible after conversion of the
On Wed, 10 Aug 2022, Cédric Le Goater wrote:
On 8/9/22 19:37, BALATON Zoltan wrote:
On Tue, 9 Aug 2022, Cédric Le Goater wrote:
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405_boards.c | 55 +-
1 file changed, 38
On Wed, 10 Aug 2022, Cédric Le Goater wrote:
On 8/9/22 19:21, BALATON Zoltan wrote:
On Tue, 9 Aug 2022, Cédric Le Goater wrote:
The Device Control Registers (DCR) of on-SoC devices are accessed by
software through the use of the mtdcr and mfdcr instructions. These
are converted in transactions
On Wed, 10 Aug 2022, Cédric Le Goater wrote:
On 8/10/22 15:28, BALATON Zoltan wrote:
On Wed, 10 Aug 2022, Cédric Le Goater wrote:
On 8/9/22 19:21, BALATON Zoltan wrote:
On Tue, 9 Aug 2022, Cédric Le Goater wrote:
The Device Control Registers (DCR) of on-SoC devices are accessed by
software
On Wed, 10 Aug 2022, Daniel Henrique Barboza wrote:
On 8/9/22 14:37, BALATON Zoltan wrote:
On Tue, 9 Aug 2022, Cédric Le Goater wrote:
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405_boards.c | 55 +-
1 file
nt8_t rxcnum,
+ qemu_irq irqs[4]);
The ppc4xx_mal_init func is gone so this declaration should also be
dropped.
Regards,
BALATON Zoltan
+
#endif /* PPC4XX_H */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 7f4c616da67c..290cfa352bed 100644
--- a/hw/ppc/ppc405_uc.
On Thu, 11 Aug 2022, Cédric Le Goater wrote:
On 8/10/22 16:48, BALATON Zoltan wrote:
On Wed, 10 Aug 2022, Cédric Le Goater wrote:
On 8/10/22 15:28, BALATON Zoltan wrote:
On Wed, 10 Aug 2022, Cédric Le Goater wrote:
On 8/9/22 19:21, BALATON Zoltan wrote:
On Tue, 9 Aug 2022, Cédric Le Goater
github.com/legoater/qemu/tree/ppc-ref405ep
I have done the minor fixes already.
OK, thanks. I'll send an updated version in the weekend.
Regards,
BALATON Zoltan
The register offset of the ROM BAR is 0x30 not 0x28. This fixes the
reg property entry of the ROM region in the device tree.
Signed-off-by: BALATON Zoltan
---
hw/ppc/pegasos2.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index
: BALATON Zoltan
---
hw/ppc/pegasos2.c | 8
1 file changed, 8 insertions(+)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index 8ed13a42a2..6475acfbed 100644
--- a/hw/ppc/pegasos2.c
+++ b/hw/ppc/pegasos2.c
@@ -739,6 +739,13 @@ static void add_pci_device(PCIBus *bus, PCIDevice *d, void
used with VOF only so I'd like these to be
merged for 8.1.
Regards,
BALATON Zoltan (3):
ppc/pegasos2: Fix reset state of USB functions
ppc/pegasos2: Fix reg property of ROM BARs
ppc/pegasos2: Fix naming of device tree nodes
hw/ppc/pegasos2.c | 18 +-
1 file change
The original non-free board firmware sets the command register of the
USB functions to 7 and some guests rely on this for working USB. Match
what the board firmware does when using VOF instead.
Signed-off-by: BALATON Zoltan
---
hw/ppc/pegasos2.c | 4
1 file changed, 4 insertions(+)
diff
The board firmware handles this correctly following the Open Firmware
standard which we missed. This fixes 64 bit BARs when using VOF.
Signed-off-by: BALATON Zoltan
---
hw/ppc/pegasos2.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2
On Fri, 21 Jul 2023, Daniel Henrique Barboza wrote:
On 7/18/23 21:32, BALATON Zoltan wrote:
These are some small fixes when using pegasos2 with the QEMU built in
VOF instead of the non-free board firmware that fix bugs in the
generated device tree and matches the board firmware in the reset
On Sat, 22 Jul 2023, BALATON Zoltan wrote:
The board firmware handles this correctly following the Open Firmware
standard which we missed. This fixes 64 bit BARs when using VOF.
In case it helps review this is defined in page 5 of this document:
https://www.openbios.org/data/docs/bus.pci.pdf
The clock and data values were logged swapped. Correct the trace event
text to match what is logged. Also fix a typo in a comment nearby.
Signed-off-by: BALATON Zoltan
---
By the way, get_maintainer.pl does not find a maintainer for
bitbang_i2c.c, should it be added somewhere with the rest of hw
Other headers now use dash instead of underscore. Rename
ahci_internal.h accordingly for consistency.
Signed-off-by: BALATON Zoltan
---
hw/ide/{ahci_internal.h => ahci-internal.h} | 0
hw/ide/ahci.c | 2 +-
hw/ide/ich.c| 2 +-
ge it.
[balaton: added commit message]
Signed-off-by: BALATON Zoltan
---
target/ppc/excp_helper.c | 2 +-
target/ppc/translate.c | 6 +-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index f1e62d9878..6cf4542e7e 100644
--- a/t
After previous changes the hypercall handling in 7xx and 74xx
exception handlers can be folded into one if statement to simplify
this code. Also add "unlikely" to mark the less frequently used branch
for the compiler.
Signed-off-by: BALATON Zoltan
Reviewed-by: Harsh Prateek Bora
---
Use the env_cpu function to get the CPUState for cpu_abort. These are
only needed in case of fatal errors so this allows to avoid casting
and storing CPUState in a local variable wnen not needed.
Signed-off-by: BALATON Zoltan
Reviewed-by: Harsh Prateek Bora
Reviewed-by: Philippe Mathieu-Daudé
code duplication from those too while at it.
Suggested-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
---
target/ppc/translate.c | 28 +++-
1 file changed, 15 insertions(+), 13 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 28fc7791af
Use #ifdef, #ifndef for brevity and add comments to #endif that are
more than a few lines apart for clarity.
Signed-off-by: BALATON Zoltan
Reviewed-by: Harsh Prateek Bora
---
target/ppc/excp_helper.c | 49
1 file changed, 24 insertions(+), 25 deletions
Remove check for !defined(CONFIG_USER_ONLY) as this is already within
an #ifndef CONFIG_USER_ONLY block.
Signed-off-by: BALATON Zoltan
Reviewed-by: Harsh Prateek Bora
---
target/ppc/excp_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/excp_helper.c b
Concatenate #if blocks that are ending then beginning on the next line
again.
Signed-off-by: BALATON Zoltan
Reviewed-by: Harsh Prateek Bora
---
target/ppc/excp_helper.c | 15 ++-
1 file changed, 2 insertions(+), 13 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc
Improve readability by shortening some long comments, removing
comments that state the obvious and dropping some empty lines so they
don't distract when reading the code.
Signed-off-by: BALATON Zoltan
Acked-by: Nicholas Piggin
---
target/ppc/cpu.h | 1 +
target/ppc/excp_hel
is in the exception handlers.
Signed-off-by: BALATON Zoltan
---
target/ppc/excp_helper.c | 43 ++--
target/ppc/translate.c | 6 ++
2 files changed, 4 insertions(+), 45 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
BALATON Zoltan (10):
target/ppc: Use env_cpu for cpu_abort in excp_helper
target/ppc: Readability improvements in exception handlers
target/ppc: Add gen_exception_err_nip() function
target/ppc: Fix gen_sc to use correct nip
target/ppc: Move patching nip from exception handler to helper_scv
0 () 00c01374
Invalid read at addr 0x4F700, size 4, region '(null)', reason: rejected
invalid/unsupported opcode: 00 - 00 - 00 - 00 () 0700
Not sure what it's trying to do here, maybe decompressing some code and
then trying to execute it? Any idea what could be the problem or what to
check further?
Regards,
BALATON Zoltan
On Tue, 27 Feb 2024, Peter Maydell wrote:
On Tue, 27 Feb 2024 at 15:10, BALATON Zoltan wrote:
Improve readability by shortening some long comments, removing
comments that state the obvious and dropping some empty lines so they
don't distract when reading the code.
Signed-off-by: BA
avoids one indirection and entirely
compiles out the switch without TARGET_PPC64.
Signed-off-by: BALATON Zoltan
Reviewed-by: Harsh Prateek Bora
---
target/ppc/excp_helper.c | 67 +---
1 file changed, 28 insertions(+), 39 deletions(-)
diff --git a/target/ppc
On Tue, 27 Feb 2024, BALATON Zoltan wrote:
On Tue, 27 Feb 2024, Peter Maydell wrote:
On Tue, 27 Feb 2024 at 15:10, BALATON Zoltan wrote:
Improve readability by shortening some long comments, removing
comments that state the obvious and dropping some empty lines so they
don't distract
re, in
the hope that this will lend itself for configuration-driven machine
creation. It is also about identifying obstacles towards this goal. Does
it make sense to deprecate some machine-specific options such as i8042?
Only if you want to break downsteam users of those options but maybe they
wo
On Tue, 27 Feb 2024, Bernhard Beschow wrote:
Am 27. Februar 2024 21:54:19 UTC schrieb BALATON Zoltan :
On Tue, 27 Feb 2024, Bernhard Beschow wrote:
Am 21. Februar 2024 11:53:21 UTC schrieb Mark Cave-Ayland
:
On 18/02/2024 13:16, Bernhard Beschow wrote:
Port 92 is an integral part of the
On Wed, 28 Feb 2024, BALATON Zoltan wrote:
On Tue, 27 Feb 2024, Bernhard Beschow wrote:
Am 27. Februar 2024 21:54:19 UTC schrieb BALATON Zoltan
:
On Tue, 27 Feb 2024, Bernhard Beschow wrote:
Am 21. Februar 2024 11:53:21 UTC schrieb Mark Cave-Ayland
:
On 18/02/2024 13:16, Bernhard Beschow
On Wed, 21 Feb 2024, BALATON Zoltan wrote:
Documentation on how to run Linux on the amigaone, pegasos2 and
sam460ex machines is currently buried in the depths of the qemu-devel
mailing list and in the source code. Let's collect the information in
the QEMU handbook for a one stop solution.
ay what the code does now?
Regards,
BALATON Zoltan
if (++insn_processed > LSI_MAX_INSN || reentrancy_level > 8) {
-if (!(s->sien0 & LSI_SIST0_UDC)) {
-qemu_log_mask(LOG_GUEST_ERROR,
- "lsi_scsi: inf. loop with UDC masked");
-
On Thu, 29 Feb 2024, Sven Schnelle wrote:
BALATON Zoltan writes:
On Thu, 29 Feb 2024, Sven Schnelle wrote:
Some OS's like HP-UX 10.20 are spinn
I guess the above line is left here by accident.
Yes.
HP-UX 10.20 seems to make the lsi53c895a spinning on a memory location
under ce
The output of info qtree monitor command is very long. Add an option
to print a brief overview omitting all the details.
Signed-off-by: BALATON Zoltan
---
hmp-commands-info.hx | 6 +++---
system/qdev-monitor.c | 24 +---
2 files changed, 16 insertions(+), 14 deletions
On Sat, 2 Mar 2024, Bernhard Beschow wrote:
Am 28. Februar 2024 13:02:55 UTC schrieb BALATON Zoltan :
On Wed, 28 Feb 2024, BALATON Zoltan wrote:
On Tue, 27 Feb 2024, Bernhard Beschow wrote:
Am 27. Februar 2024 21:54:19 UTC schrieb BALATON Zoltan :
On Tue, 27 Feb 2024, Bernhard Beschow wrote
Signed-off-by: BALATON Zoltan
---
hw/scsi/lsi53c895a.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c
index d607a5f9fb..4f784be749 100644
--- a/hw/scsi/lsi53c895a.c
+++ b/hw/scsi/lsi53c895a.c
@@ -225,7 +225,7 @@ struct LSIState
what could it be and what could be done about it?
Regards,
BALATON Zoltan
On Sun, 3 Mar 2024, Sven Schnelle wrote:
BALATON Zoltan writes:
AmigaOS4 also has a driver for this card so I've tried to test it but
it trips an assert. Does anybody have an idea why and how it could be
fixed? Sven's recent patches don't seem to have an effect on this, i
On Sun, 3 Mar 2024, BALATON Zoltan wrote:
On Sun, 3 Mar 2024, Sven Schnelle wrote:
BALATON Zoltan writes:
AmigaOS4 also has a driver for this card so I've tried to test it but
it trips an assert. Does anybody have an idea why and how it could be
fixed? Sven's recent patches don
On Sun, 3 Mar 2024, Sven Schnelle wrote:
BALATON Zoltan writes:
Hello,
AmigaOS4 also has a driver for this card so I've tried to test it but
it trips an assert. Does anybody have an idea why and how it could be
fixed? Sven's recent patches don't seem to have an effect on
On Sun, 3 Mar 2024, BALATON Zoltan wrote:
On Sun, 3 Mar 2024, Sven Schnelle wrote:
BALATON Zoltan writes:
Hello,
AmigaOS4 also has a driver for this card so I've tried to test it but
it trips an assert. Does anybody have an idea why and how it could be
fixed? Sven's recent pat
Having to use -drive if=none,... and -device ide-[cd,hd] is
inconvenient. Add support for shorter convenience options such as
-cdrom and -drive media=disk. Also adjust two nearby comments for code
style.
Signed-off-by: BALATON Zoltan
---
hw/ppc/sam460ex.c | 24 +++-
1 file
The output of info qtree monitor command is very long. Add an option
to print a brief overview omitting all the details.
Signed-off-by: BALATON Zoltan
Reviewed-by: Dr. David Alan Gilbert
---
v2:
- Change the variable name to deails too
- Add braces to if (checkpatch did not warn for this so
On Tue, 13 Feb 2024, Philippe Mathieu-Daudé wrote:
We should not wire IRQs on unrealized device.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: BALATON Zoltan
---
hw/i386/pc_q35.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/i386/pc_q35.c b/hw/i386
On Tue, 13 Feb 2024, Philippe Mathieu-Daudé wrote:
We should not wire IRQs on unrealized device.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Mark Cave-Ayland
Reviewed-by: BALATON Zoltan
---
hw/misc/macio/macio.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff
peek into the
object that owns the usb_bus or try using qdev_get_child_bus() but that
needs the name of the bus which might change if other usb hosts are added
so neither of these options seem better than this function. What would it
bring to remove this function other than more complex or uglier code? I
don't mind if you remove it just don't see the benefit in that.
Regards,
BALATON Zoltan
ff-by: BALATON Zoltan
---
Supersedes: <20231216123013.67978-1-shen...@gmail.com>
MAINTAINERS | 1 +
docs/system/ppc/amigang.rst | 160
docs/system/target-ppc.rst | 1 +
3 files changed, 162 insertions(+)
create mode 100644 docs
On Fri, 16 Feb 2024, Thomas Huth wrote:
On 16/02/2024 01.10, BALATON Zoltan wrote:
Documentation on how to run Linux on the amigaone, pegasos2 and
sam460ex machines is currently burried in the depths of the qemu-devel
s/burried/buried/
mailing list and in the source code. Let's collec
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