Hi Shameer,
On 6/22/20 2:41 PM, Shameer Kolothum wrote:
> This adds support for memory(pc-dimm) hot remove on arm/virt that
> uses acpi ged device.
>
> NVDIMM hot removal is not yet supported.
>
> Signed-off-by: Shameer Kolothum
Works fine for me when passing "movable_node" in the guest kernel
Hi Markus,
On 6/23/20 5:15 PM, Markus Armbruster wrote:
> Auger Eric writes:
>
>> Hi Markus,
>>
>> On 6/22/20 1:22 PM, Markus Armbruster wrote:
>>> Eric Auger writes:
>>>
>>>> Introduce a new property defining a reserved region:
>>&g
Hi Markus,
On 6/23/20 5:13 PM, Markus Armbruster wrote:
> Eric Auger writes:
>
>> Introduce a new property defining a reserved region:
>> ::.
>>
>> This will be used to encode reserved IOVA regions.
>>
>> For instance, in virtio-iommu use case, reserved IOVA regions
>> will be passed by the mach
Hi Paolo,
On 6/23/20 6:22 PM, Paolo Bonzini wrote:
> On 23/06/20 17:54, Eric Auger wrote:
>> This patch introduces two new functions, object_property_add_err() and
>> object_property_add_child_err() whose prototype features an error handle.
>> object_property_add_child_err() now gets called from u
Hi Markus,
On 6/24/20 10:10 AM, Markus Armbruster wrote:
> Auger Eric writes:
>
>> Hi Markus,
>>
>> On 6/23/20 5:13 PM, Markus Armbruster wrote:
>>> Eric Auger writes:
>>>
>>>> Introduce a new property defining a reserved region:
>&g
Hi Markus,
On 6/24/20 10:22 AM, Markus Armbruster wrote:
> Eric Auger writes:
>
>> object_property_add() does not allow object_property_try_add()
>> to gracefully fail as &error_abort is passed as an error handle.
>>
>> However such failure can easily be triggered from the QMP shell when,
>> for
Hi,
On 6/24/20 3:35 PM, no-re...@patchew.org wrote:
> Patchew URL:
> https://patchew.org/QEMU/20200624124301.7112-1-eric.au...@redhat.com/
>
>
>
> Hi,
>
> This series failed the docker-quick@centos7 build test. Please find the
> testing commands and
> their output below. If you have Docker i
Hi Paolo,
On 6/24/20 4:12 PM, Paolo Bonzini wrote:
> On 24/06/20 14:43, Eric Auger wrote:
>> +op = object_property_try_add(obj, name, type, object_get_child_property,
>> + NULL, object_finalize_child_property,
>> + child, errp);
>
Hi Paolo,
On 6/24/20 4:17 PM, Auger Eric wrote:
> Hi Paolo,
>
> On 6/24/20 4:12 PM, Paolo Bonzini wrote:
>> On 24/06/20 14:43, Eric Auger wrote:
>>> +op = object_property_try_add(obj, name, type,
>>> object_get_child_property,
>>&
Hi Thomas,
On 6/24/20 2:43 PM, Eric Auger wrote:
> This new test checks that attempting to create an object
> with an existing ID gracefully fails.
>
> Signed-off-by: Eric Auger
> ---
> tests/qtest/qmp-cmd-test.c | 18 ++
> 1 file changed, 18 insertions(+)
>
> diff --git a/test
Hi Paolo,
On 6/24/20 6:16 PM, Paolo Bonzini wrote:
> On 24/06/20 18:02, Auger Eric wrote:
>> Hi Paolo,
>>
>> On 6/24/20 4:17 PM, Auger Eric wrote:
>>> Hi Paolo,
>>>
>>> On 6/24/20 4:12 PM, Paolo Bonzini wrote:
>>>> On 24/06/20 14:43, E
Hi Peter,
On 7/5/20 8:21 PM, Peter Maydell wrote:
> On Fri, 3 Jul 2020 at 17:54, Peter Maydell wrote:
>>
>> From: Eric Auger
>>
>> This patch implements the PROBE request. At the moment,
>> only THE RESV_MEM property is handled. The first goal is
>> to report iommu wide reserved regions such as
Hi Peter,
On 7/10/20 11:47 AM, Peter Maydell wrote:
> On Wed, 8 Jul 2020 at 15:20, Eric Auger wrote:
>>
>> Expose the RIL bit so that the guest driver uses range
>> invalidation. Range invalidation being an SMMU3.2 feature,
>> let AIDR advertise SMMUv3.2 support.
>>
>> Signed-off-by: Eric Auger
Hi Li,
On 7/14/20 7:15 PM, Li Qiang wrote:
> Fixes: 5b88849e7b9("tests/qmp-cmd-test: Add
> qmp/object-add-failure-modes"
Thank you for fixing this.
Adding a commit message generally is welcome such as for example:
properly free each test response and separate qtest_qmp() calls with
spare lines,
Hi Li,
On 7/14/20 5:35 PM, Li Qiang wrote:
> Fixes: 5da7c35e25a("bios-tables-test: Add Q35/TPM-TIS test")
> Signed-off-by: Li Qiang
> ---
> tests/qtest/bios-tables-test.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
> i
Hi Peter,
On 7/13/20 7:57 PM, Peter Maydell wrote:
> Document the arm 'virt' board, which has been undocumented
> for far too long given that it is the main recommended board
> type for arm guests.
>
> Signed-off-by: Peter Maydell
> ---
> docs/system/arm/virt.rst | 157
Hi Peter,
On 7/10/20 11:47 AM, Peter Maydell wrote:
> On Wed, 8 Jul 2020 at 15:20, Eric Auger wrote:
>>
>> Expose the RIL bit so that the guest driver uses range
>> invalidation. Range invalidation being an SMMU3.2 feature,
>> let AIDR advertise SMMUv3.2 support.
>>
>> Signed-off-by: Eric Auger
Hi Peter,
On 7/30/20 3:38 PM, Peter Maydell wrote:
> On Tue, 28 Jul 2020 at 16:09, Eric Auger wrote:
>>
>> At the moment each entry in the IOTLB corresponds to a page sized
>> mapping (4K, 16K or 64K), even if the page belongs to a mapped
>> block. In case of block mapping this unefficiently cons
Hi Drew,
On 8/5/20 11:16 AM, Andrew Jones wrote:
> Move the KVM PMU setup part of fdt_add_pmu_nodes() to
> virt_cpu_post_init(), which is a more appropriate location. Now
> fdt_add_pmu_nodes() is also named more appropriately, because it
> no longer does anything but fdt node creation.
>
> No func
Hi Drew,
On 8/5/20 11:16 AM, Andrew Jones wrote:
> When we compile without KVM support !defined(CONFIG_KVM) we generate
> stubs for functions that the linker will still encounter. Sometimes
> these stubs can be executed safely and are placed in paths where they
> get executed with or without KVM.
Maydell
Reviewed-by: Eric Auger
Eric
> ---
> hw/arm/virt.c | 43 +++
> 1 file changed, 27 insertions(+), 16 deletions(-)
>
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index acf9bfbeceaf..2cba21fe3ad9 100644
> --- a/hw/arm/vir
Drew,
On 8/5/20 11:16 AM, Andrew Jones wrote:
> We add the kvm-steal-time CPU property and implement it for machvirt.
> A tiny bit of refactoring was also done to allow pmu and pvtime to
> use the same vcpu device helper functions.
>
> Signed-off-by: Andrew Jones
> ---
> docs/system/arm/cpu-fea
Hi,
On 8/13/20 9:37 AM, Chen Qun wrote:
> Clang static code analyzer show warning:
> hw/vfio/platform.c:239:9: warning: Value stored to 'ret' is never read
> ret = event_notifier_test_and_clear(intp->interrupt);
> ^ ~~
>
> Reported-b
Hi Peter,
On 6/25/20 12:08 PM, Peter Maydell wrote:
> Fix a typo in an error message in virtio_iommu_pci_realize():
> "Check you machine" should be "Check your machine".
>
> Reported-by: Markus Armbruster
> Signed-off-by: Peter Maydell
Reviewed-by: Eric Auger
Thanks
Eric
> ---
> hw/virtio/
Hi Markus,
On 6/25/20 9:05 AM, Markus Armbruster wrote:
> Eric Auger writes:
>
>> This patch implements the PROBE request. At the moment,
>> only THE RESV_MEM property is handled. The first goal is
>> to report iommu wide reserved regions such as the MSI regions
>> set by the machine code. On x86
Hi Peter,
On 6/25/20 12:01 PM, Peter Maydell wrote:
> On Wed, 24 Jun 2020 at 14:27, Eric Auger wrote:
>>
>> At the moment the virtio-iommu translates MSI transactions.
>> This behavior is inherited from ARM SMMU. The virt machine
>> code knows where the guest MSI doorbells are so we can easily
>>
Hi Peter,
On 6/25/20 12:12 PM, Peter Maydell wrote:
> On Thu, 25 Jun 2020 at 08:06, Markus Armbruster wrote:
>> $ qemu-system-x86_64 -nodefaults -S -display none -device
>> virtio-iommu-pci,len-reserved-regions=1,reserved-regions[0]=0xfee0:0xfeef:99
>> qemu-system-x86_64: -device
Hi Markus
On 6/26/20 10:53 AM, Markus Armbruster wrote:
> Auger Eric writes:
>
>> Hi Markus,
>> On 6/25/20 9:05 AM, Markus Armbruster wrote:
>>> Eric Auger writes:
>>>
>>>> This patch implements the PROBE request. At the moment,
>>>&
Hi Peter,
On 6/25/20 5:03 PM, Peter Maydell wrote:
> On Thu, 11 Jun 2020 at 17:15, Eric Auger wrote:
>>
>> Instead of using a Jenkins hash function to generate
>> the key let's just use a 64 bit unsigned integer that
>> contains the asid and the 40 upper bits of the iova.
>> A maximum of 52-bit I
Hi Peter,
On 6/25/20 5:30 PM, Peter Maydell wrote:
> On Thu, 11 Jun 2020 at 17:16, Eric Auger wrote:
>>
>> At the moment each entry in the IOTLB corresponds to a page sized
>> mapping (4K, 16K or 64K), even if the page belongs to a mapped
>> block. In case of block mapping this unefficiently cons
Hi Peter,
On 6/25/20 4:49 PM, Peter Maydell wrote:
> On Thu, 11 Jun 2020 at 17:15, Eric Auger wrote:
>>
>> Page and block PTE decoding can share some code. Let's
>> first handle table PTE and factorize some code shared by
>> page and block PTEs.
>>
>> Signed-off-by: Eric Auger
>> ---
>> hw/arm/
Hi Peter,
On 6/25/20 5:15 PM, Peter Maydell wrote:
> On Thu, 11 Jun 2020 at 17:15, Eric Auger wrote:
>>
>> Compute the starting level on CD decoding and store it
>> into SMMUTransTableInfo. We will need this information
>> on IOTLB lookup so let's avoid to recompute it each time.
>>
>> Signed-off
Hi Markus,
On 6/27/20 9:03 AM, Markus Armbruster wrote:
> Eric Auger writes:
>
>> The machine may need to pass reserved regions to the
>> virtio-iommu-pci device (such as the MSI window on x86
>> or the MSI doorbells on ARM).
>>
>> So let's add an array of Interval properties.
>>
>> Note: if som
Hi Markus,
On 6/27/20 9:08 AM, Markus Armbruster wrote:
> Eric Auger writes:
>
>> This patch implements the PROBE request. At the moment,
>> only THE RESV_MEM property is handled. The first goal is
>> to report iommu wide reserved regions such as the MSI regions
>> set by the machine code. On x8
Hi Markus
On 6/25/20 11:24 AM, Markus Armbruster wrote:
> Eric Auger writes:
>
>> object_property_add() does not allow object_property_try_add()
>> to gracefully fail as &error_abort is passed as an error handle.
>>
>> However such failure can easily be triggered from the QMP shell when,
>> for
Hi Paolo,
On 6/29/20 5:30 PM, Paolo Bonzini wrote:
> On 29/06/20 13:23, Eric Auger wrote:
>> Attempting to add an object through QMP with an id that is
>> already used leads to a qemu abort. This is a regression since
>> d2623129a7de ("qom: Drop parameter @errp of object_property_add()
>> & friend
Hi Peter,
On 6/26/20 3:53 PM, Auger Eric wrote:
> Hi Peter,
>
> On 6/25/20 5:30 PM, Peter Maydell wrote:
>> On Thu, 11 Jun 2020 at 17:16, Eric Auger wrote:
>>>
>>> At the moment each entry in the IOTLB corresponds to a page sized
>>> mapping (4K,
Hi Peter,
On 6/30/20 5:50 PM, Peter Maydell wrote:
> On Fri, 26 Jun 2020 at 14:53, Auger Eric wrote:
>> On 6/25/20 5:30 PM, Peter Maydell wrote:
>>> Rather than looping around doing multiple hash table lookups like
>>> this, why not just avoid including the tg and le
Hi Paolo,
On 6/29/20 5:30 PM, Paolo Bonzini wrote:
> On 29/06/20 13:23, Eric Auger wrote:
>> Attempting to add an object through QMP with an id that is
>> already used leads to a qemu abort. This is a regression since
>> d2623129a7de ("qom: Drop parameter @errp of object_property_add()
>> & friend
Hi Greg,
On 6/30/20 3:41 PM, Greg Kurz wrote:
> On Mon, 29 Jun 2020 21:34:22 +0200
> Eric Auger wrote:
>
>> object_property_add() does not allow object_property_try_add()
>> to gracefully fail as &error_abort is passed as an error handle.
>>
>> However such failure can easily be triggered from t
Hi,
On 6/29/20 9:03 AM, Eric Auger wrote:
> By default the virtio-iommu translates MSI transactions. This
> behavior is inherited from ARM SMMU. However the virt machine
> code knows where the MSI doorbells are, so we can easily
> declare those regions as VIRTIO_IOMMU_RESV_MEM_T_MSI. With that
> s
Hi Michael,
On 7/2/20 1:28 PM, Michael S. Tsirkin wrote:
> On Mon, Jun 29, 2020 at 09:03:59AM +0200, Eric Auger wrote:
>> By default the virtio-iommu translates MSI transactions. This
>> behavior is inherited from ARM SMMU. However the virt machine
>> code knows where the MSI doorbells are, so we
Hi Alex,
On 9/24/19 1:05 AM, Alex Williamson wrote:
> On Mon, 23 Sep 2019 08:55:51 +0200
> Eric Auger wrote:
>
>> The container error integer field is currently used to store
>> the first error potentially encountered during any
>> vfio_listener_region_add() call. However this fails to propagate
Hi Thomas,
On 9/23/19 8:09 PM, Thomas Huth wrote:
> On 23/09/2019 16.31, Auger Eric wrote:
>> Hi Thomas,
>>
>> On 9/21/19 5:04 PM, Thomas Huth wrote:
>>> We are going to make CONFIG_ARM_V7M optional, so the related cortex-m
>>> CPUs should only be created
Hi Thomas,
On 9/24/19 1:06 PM, Thomas Huth wrote:
> On 24/09/2019 13.02, Auger Eric wrote:
>> Hi Thomas,
>>
>> On 9/23/19 8:09 PM, Thomas Huth wrote:
>>> On 23/09/2019 16.31, Auger Eric wrote:
>>>> Hi Thomas,
>>>>
>>>>
'sve=on|off'
> property to give it that flexibility. We also rename
> cpu_max_get/set_sve_vq to cpu_max_get/set_sve_max_vq in order for them
> to follow the typical *_get/set_ pattern.
>
> Signed-off-by: Andrew Jones
> Reviewed-by: Richard Henderson
Reviewed-by: Eric Auger
Er
Hi Drew,
On 9/24/19 1:30 PM, Andrew Jones wrote:
> Add support for the query-cpu-model-expansion QMP command to Arm. We
> do this selectively, only exposing CPU properties which represent
> optional CPU features which the user may want to enable/disable.
> Additionally we restrict the list of quer
Hi Drew,
On 9/24/19 1:31 PM, Andrew Jones wrote:
> Introduce cpu properties to give fine control over SVE vector lengths.
> We introduce a property for each valid length up to the current
> maximum supported, which is 2048-bits. The properties are named, e.g.
> sve128, sve256, sve384, sve512, ...,
Richard Henderson
Reviewed-by: Eric Auger
Eric
> ---
> target/arm/kvm64.c | 137 +++--
> 1 file changed, 133 insertions(+), 4 deletions(-)
>
> diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
> index 28f6db57d5ee..ea454c613919 10064
ing all vector lengths the host CPU supports
> when on. We'll add the other SVE CPU properties in later patches.
>
> Signed-off-by: Andrew Jones
> Reviewed-by: Richard Henderson
Reviewed-by: Eric Auger
Eric
> ---
> target/arm/cpu64.c | 17 ++---
> t
Hi Drew,
On 9/24/19 1:31 PM, Andrew Jones wrote:
> Extend the SVE vq map initialization and validation with KVM's
> supported vector lengths when KVM is enabled. In order to determine
> and select supported lengths we add two new KVM functions for getting
> and setting the KVM_REG_ARM64_SVE_VLS ps
Hi Drew,
On 9/24/19 1:31 PM, Andrew Jones wrote:
> Allow cpu 'host' to enable SVE when it's available, unless the
> user chooses to disable it with the added 'sve=off' cpu property.
> Also give the user the ability to select vector lengths with the
> sve properties. We don't adopt 'max' cpu's othe
On 9/26/19 10:21 AM, Andrew Jones wrote:
> On Wed, Sep 25, 2019 at 03:53:42PM +0200, Auger Eric wrote:
>> Hi Drew,
>>
>> On 9/24/19 1:31 PM, Andrew Jones wrote:
>>> Introduce cpu properties to give fine control over SVE vector lengths.
>>> We introduce a p
On 9/26/19 10:41 AM, Andrew Jones wrote:
> On Thu, Sep 26, 2019 at 08:52:55AM +0200, Auger Eric wrote:
>> Hi Drew,
>>
>> On 9/24/19 1:31 PM, Andrew Jones wrote:
>>> Extend the SVE vq map initialization and validation with KVM's
>>> supported vec
Hi Drew,
On 9/26/19 1:40 PM, Andrew Jones wrote:
> On Thu, Sep 26, 2019 at 12:01:36PM +0200, Auger Eric wrote:
>>
>>
>> On 9/26/19 10:41 AM, Andrew Jones wrote:
>>> On Thu, Sep 26, 2019 at 08:52:55AM +0200, Auger Eric wrote:
>>>> Hi Drew,
>&g
Hi Cleber,
On 3/23/21 11:15 PM, Cleber Rosa wrote:
> If the vmlinuz variable is set to anything that evaluates to True,
> then the respective arguments should be set. If the variable contains
> an empty string, than it will evaluate to False, and the extra
s/than/then
> arguments will not be set.
Hi Cleber,
On 3/23/21 11:15 PM, Cleber Rosa wrote:
> The tag is useful to select tests that depend/use a particular
> feature.
>
> Signed-off-by: Cleber Rosa
> Reviewed-by: Wainer dos Santos Moschetta
> Reviewed-by: Willian Rampazzo
> ---
> tests/acceptance/virtiofs_submounts.py | 1 +
> 1 fi
Hi Cleber,
On 3/23/21 11:15 PM, Cleber Rosa wrote:
> Slightly different versions for the same utility code are currently
> present on different locations. This unifies them all, giving
> preference to the version from virtiofs_submounts.py, because of the
> last tweaks added to it.
>
> While at
Hi Cleber,
On 3/23/21 11:15 PM, Cleber Rosa wrote:
> Both the virtiofs submounts and the linux ssh mips malta tests
> contains useful methods related to ssh that deserve to be made
> available to other tests. Let's move them to the base LinuxTest
nit: strictly speaking they are moved to another c
Hi Cleber,
On 3/23/21 11:15 PM, Cleber Rosa wrote:
> For users of the LinuxTest class, let's set up the VM with the port
> redirection for SSH, instead of requiring each test to set the same
also sets the network device to virtio-net. This may be worth mentioning
here in the commit msg.
> argument
sa
Reviewed-by: Eric Auger
Eric
> ---
> tests/acceptance/avocado_qemu/__init__.py | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/tests/acceptance/avocado_qemu/__init__.py
> b/tests/acceptance/avocado_qemu/__init__.py
> index e75b002
Hi Cleber,
On 3/23/21 11:15 PM, Cleber Rosa wrote:
> The LinuxTest specifically targets users that need to interact with Linux
> guests. So, it makes sense to give a connection by default, and avoid
> requiring it as boiler-plate code.
>
> Signed-off-by: Cleber Rosa
> ---
> tests/acceptance/av
Hi,
On 3/23/21 11:15 PM, Cleber Rosa wrote:
> The LinuxTest class' launch_and_wait() method now behaves the same way
> as this test's custom launch_vm(), so let's just use the upper layer
> (common) method.
>
> Signed-off-by: Cleber Rosa
Reviewed-by: Eric Auger
Hi,
On 3/23/21 11:15 PM, Cleber Rosa wrote:
> Signed-off-by: Cleber Rosa
> Reviewed-by: Marc-André Lureau
> Reviewed-by: Willian Rampazzo
Reviewed-by: Eric Auger
Eric
> ---
> docs/devel/testing.rst | 25 +
> 1 file changed, 25 insertions(+)
>
ollow a similar
> pattern and need to interact with QEMU (via qmp) and with the Linux
> guest via SSH.
>
> Signed-off-by: Cleber Rosa
> Reviewed-by: Marc-André Lureau
> Reviewed-by: Willian Rampazzo
Reviewed-by: Eric Auger
Eric
> ---
>
Hi Cleber,
On 3/23/21 11:15 PM, Cleber Rosa wrote:
> For users of the LinuxTest class, let's set up the VM with the port
> redirection for SSH, instead of requiring each test to set the same
> arguments.
>
> Signed-off-by: Cleber Rosa
> ---
> tests/acceptance/avocado_qemu/__init__.py | 4 +++-
>
Hi Cleber,
On 3/24/21 11:23 PM, Cleber Rosa wrote:
> On Wed, Mar 24, 2021 at 10:07:31AM +0100, Auger Eric wrote:
>> Hi Cleber,
>>
>> On 3/23/21 11:15 PM, Cleber Rosa wrote:
>>> Both the virtiofs submounts and the linux ssh mips malta tests
>>> contains use
Hi Cleber,
On 3/25/21 3:36 PM, Cleber Rosa wrote:
> On Thu, Mar 25, 2021 at 10:57:12AM +0100, Eric Auger wrote:
>> Add new tests checking the good behavior of the SMMUv3 protecting
>> 2 virtio pci devices (block and net). We check the guest boots and
>> we are able to install a package. Different
Hi Zenghui,
On 3/25/21 3:27 PM, Zenghui Yu wrote:
> They were introduced in commit 9bde7f0674fe ("hw/arm/smmuv3: Implement
> translate callback") but never actually used. Drop them.
>
> Signed-off-by: Zenghui Yu
> ---
> hw/arm/smmuv3-internal.h | 7 ---
> 1 file changed, 7 deletions(-)
>
>
Hi Zenghui,
On 3/25/21 3:18 PM, Zenghui Yu wrote:
> On 2021/3/9 18:27, Eric Auger wrote:
>> If the whole SID range (32b) is invalidated (SMMU_CMD_CFGI_ALL),
>> @end overflows and we fail to handle the command properly.
>>
>> Once this gets fixed, the current code really is awkward in the
>> sense
Hi Wainer,
On 3/25/21 8:45 PM, Wainer dos Santos Moschetta wrote:
> Hi,
>
> On 3/23/21 7:15 PM, Cleber Rosa wrote:
>> This introduces a base class for tests that need to interact with a
>> Linux guest. It generalizes the "boot_linux.py" code, already been
>> used by the "virtiofs_submounts.py" a
Hi Peter,
On 3/25/21 4:33 PM, Peter Maydell wrote:
> The function machine_class_allow_dynamic_sysbus_dev() is currently
> undocumented; add a doc comment.
>
> Signed-off-by: Peter Maydell
> ---
> include/hw/boards.h | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/inclu
Hi Peter,
On 3/25/21 4:33 PM, Peter Maydell wrote:
> Provide a new function dynamic_sysbus_dev_allowed() which checks
> the per-machine whitelist of dynamic sysbus devices and returns
> a boolean result indicating whether the device is whitelisted.
> We can use this in the implementation of valida
Hi Peter,
On 3/25/21 4:33 PM, Peter Maydell wrote:
> The virt machine device plug callback currently calls
> platform_bus_link_device() for any sysbus device. This is overly
> broad, because platform_bus_link_device() will unconditionally grab
> the IRQs and MMIOs of the device it is passed, whet
is not supported by this machine yet.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Eric Auger
Eric
> ---
> hw/ppc/e500plat.c | 8 ++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c
> index bddd5e7c48f..fc911b
Hi Peter,
On 3/26/21 11:20 AM, Peter Maydell wrote:
> On Fri, 26 Mar 2021 at 09:27, Auger Eric wrote:
>>
>> Hi Peter,
>>
>> On 3/25/21 4:33 PM, Peter Maydell wrote:
>>> The function machine_class_allow_dynamic_sysbus_dev() is currently
>>> undocumen
Hi Zenghui,
On 4/2/21 12:04 PM, Zenghui Yu wrote:
> In emulation of the CFGI_STE_RANGE command, we now take StreamID as the
> start of the invalidation range, regardless of whatever the Range is,
> whilst the spec clearly states that
>
> - "Invalidation is performed for an *aligned* range of 2^(
Hi Zenghui,
On 4/2/21 10:47 AM, Zenghui Yu wrote:
> The GSIV values in SMMUv3 IORT node are not correct as they don't match
> the SMMUIrq enumeration, which describes the IRQ<->PIN mapping used by
> our emulated vSMMU.
>
> Fixes: a703b4f6c1ee ("hw/arm/virt-acpi-build: Add smmuv3 node in IORT tabl
Hi Peter,
On 4/6/21 12:44 PM, Peter Maydell wrote:
> On Tue, 6 Apr 2021 at 11:10, Auger Eric wrote:
>>
>> Hi Zenghui,
>>
>> On 4/2/21 10:47 AM, Zenghui Yu wrote:
>>> The GSIV values in SMMUv3 IORT node are not correct as they don't match
>>> the
Hi Peter,
On 4/6/21 2:31 PM, Peter Maydell wrote:
> On Tue, 6 Apr 2021 at 13:23, Auger Eric wrote:
>>
>> Hi Peter,
>>
>> On 4/6/21 12:44 PM, Peter Maydell wrote:
>>> On Tue, 6 Apr 2021 at 11:10, Auger Eric wrote:
>>>>
>>>> Hi Zenghu
Hi Kunkun,
On 3/27/21 3:24 AM, Kunkun Jiang wrote:
> Hi all,
>
> Recently, I did some tests on SMMU nested mode. Here is
> a question about the translation granule size supported by
> vSMMU.
>
> There is such a code in SMMUv3_init_regs():
>
>> /* 4K and 64K granule support */
>> s->idr[5
Hi Kunkun,
On 3/31/21 8:47 AM, Kunkun Jiang wrote:
> The driver can query some bits in SMMUv3 IDR5 to learn which
> translation granules are supported. Arm recommends that SMMUv3
> implementations support at least 4K and 64K granules. But in
> the vSMMUv3, there seems to be no reason not to suppor
Hi Kunkun,
On 4/7/21 11:26 AM, Kunkun Jiang wrote:
> Hi Eric,
>
> On 2021/4/7 3:50, Auger Eric wrote:
>> Hi Kunkun,
>>
>> On 3/27/21 3:24 AM, Kunkun Jiang wrote:
>>> Hi all,
>>>
>>> Recently, I did some tests on SMMU nested mode. Her
Hi Kunkun,
On 2/19/21 10:42 AM, Kunkun Jiang wrote:
> Extract part of the code from vfio_sync_dirty_bitmap to form a
> new helper, which allows to mark dirty pages of a RAM section.
> This helper will be called for nested stage.
>
> Signed-off-by: Kunkun Jiang
> ---
> hw/vfio/common.c | 22
Hi Kunkun,
On 2/19/21 10:42 AM, Kunkun Jiang wrote:
> On Intel, the DMA mapped through the host single stage. Instead
> we set up the stage 2 and stage 1 separately in nested mode as there
> is no "Caching Mode".
You need to rewrite the above sentences, Missing ARM and also the 1st
sentences miss
Hi Kunkun,
On 2/19/21 10:42 AM, Kunkun Jiang wrote:
> In nested mode, we call the set_pasid_table() callback on each STE
> update to pass the guest stage 1 configuration to the host and
> apply it at physical level.
>
> In the case of live migration, we need to manual call the
s/manual/manually
>
Hi Kunkun,
On 2/19/21 10:42 AM, Kunkun Jiang wrote:
> Hi all,
>
> Since the SMMUv3's nested translation stages[1] has been introduced by Eric,
> we
> need to pay attention to the migration of VFIO PCI devices in SMMUv3 nested
> stage
> mode. At present, it is not yet supported in QEMU. There ar
Hi Wang,
On 3/25/21 8:22 AM, Wang Xingang wrote:
> From: Xingang Wang
>
> The pci host iommu property is useful to check whether
> the iommu is enabled on the pci root bus.
>
> Signed-off-by: Xingang Wang
> Signed-off-by: Jiahui Cen
> ---
> hw/pci/pci.c | 18 +-
>
Hi Wang,
On 3/25/21 8:22 AM, Wang Xingang wrote:
> From: Xingang Wang
>
> This add iommu option for pci root bus, including primary bus
> and pxb root bus. The option is valid only if there is a virtual
> iommu device.
>
> Signed-off-by: Xingang Wang
> Signed-off-by: Jiahui Cen
same in this
Hi Xingang,
On 3/25/21 8:22 AM, Wang Xingang wrote:
> From: Xingang Wang
>
> This helps to find max bus number of a root bus.
s/max bus number of a root bus/highest bus number of a bridge hierarchy?
>
> Signed-off-by: Xingang Wang
> Signed-off-by: Jiahui Cen
> ---
> hw/pci/pci.c | 34
Hi Xingang,
On 3/25/21 8:22 AM, Wang Xingang wrote:
> From: Xingang Wang
>
> The idmap of smmuv3 and root complex covers the whole RID space for now,
> this patch add explicit idmap info according to root bus number range.
> This add smmuv3 idmap for certain bus which has enabled the iommu prope
Hi Kunkun,
On 4/13/21 2:10 PM, Kunkun Jiang wrote:
> Hi Eric,
>
> On 2021/4/11 20:08, Eric Auger wrote:
>> In nested mode, legacy vfio_iommu_map_notify cannot be used as
>> there is no "caching" mode and we do not trap on map.
>>
>> On Intel, vfio_iommu_map_notify was used to DMA map the RAM
>> t
Hi Kunkun,
On 4/14/21 3:45 AM, Kunkun Jiang wrote:
> On 2021/4/13 20:57, Auger Eric wrote:
>> Hi Kunkun,
>>
>> On 4/13/21 2:10 PM, Kunkun Jiang wrote:
>>> Hi Eric,
>>>
>>> On 2021/4/11 20:08, Eric Auger wrote:
>>>> In nested mode, leg
Hi Xingang,
On 3/11/21 12:57 PM, Wang Xingang wrote:
> Hi Eric,
>
> On 2021/3/10 18:18, Auger Eric wrote:
>> Hi Xingang,
>>
>> On 3/10/21 3:13 AM, Wang Xingang wrote:
>>> Hi Eric,
>>>
>>> On 2021/3/9 22:36, Auger Eric wrote:
>>&g
Hi Xingang
On 3/11/21 1:24 PM, Wang Xingang wrote:
> Hi Eric,
>
> On 2021/3/10 18:24, Auger Eric wrote:
>> Hi Xingang,
>>
>> On 2/27/21 9:33 AM, Wang Xingang wrote:
>>> From: Xingang Wang
>>>
>>> This add iommu option for pci root bus, incl
Hi Peter,
On 3/8/21 5:37 PM, Peter Maydell wrote:
> On Thu, 25 Feb 2021 at 09:15, Eric Auger wrote:
>>
>> If the asid is not set, do not attempt to locate the key directly
>> as all inserted keys have a valid asid.
>>
>> Use g_hash_table_foreach_remove instead.
>>
>> Signed-off-by: Eric Auger
>>
Hi,
On 2/27/21 9:33 AM, Wang Xingang wrote:
> From: Xingang Wang
>
> These patches add support for configure iommu on/off for pci root bus,
> including primary bus and pxb root bus. At present, All root bus will go
> through iommu when iommu is configured, which is not flexible.
>
> So this add
Hi Xingang,
On 2/27/21 9:33 AM, Wang Xingang wrote:
> From: Xingang Wang
>
> This add iommu option for pci root bus, including primary bus
> and pxb root bus. Default option is set to true, and the option
> is valid only if the iommu option for machine is properly set.
>
> Signed-off-by: Xingan
Hi Xingang,
On 3/10/21 3:13 AM, Wang Xingang wrote:
> Hi Eric,
>
> On 2021/3/9 22:36, Auger Eric wrote:
>> Hi,
>> On 2/27/21 9:33 AM, Wang Xingang wrote:
>>> From: Xingang Wang
>>>
>>> These patches add support for configure iommu on/off for pci
Hi Xingang,
On 2/27/21 9:33 AM, Wang Xingang wrote:
> From: Xingang Wang
>
> This Property can be useful to check whether this bus is attached to iommu.
Strictly speaking this is not a Property (QEMU property) but a flag
>
> Signed-off-by: Xingang Wang
> Signed-off-by: Jiahui Cen
> ---
> in
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